Prosecution Insights
Last updated: May 04, 2026
Application No. 18/498,008

DISTRIBUTED PROGRAMMABLE GAIN AMPLIFIER

Non-Final OA §103§112
Filed
Oct 30, 2023
Examiner
NGUYEN, KHANH V
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Avago Technologies International Sales Pte. Ltd.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
1107 granted / 1183 resolved
+25.6% vs TC avg
Minimal +2% lift
Without
With
+1.9%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
25 currently pending
Career history
1208
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
28.8%
-11.2% vs TC avg
§102
39.5%
-0.5% vs TC avg
§112
27.2%
-12.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1183 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, 2 nd limitation, lines 9-11, discloses “ the second circuit (221) being configured to transmit the first signal (V1) from the first terminal (P0) to the second terminal (P1) and provide a gain to a second signal (V2) at the third terminal (P2) over the first signal ”, this is incorrect. Based on applicant’s Figure 2 and specification, disclose first signal (V1) is at second terminal (P1) and NOT at the first terminal (P0) as claimed and second signal (V2) is at third terminal (P2). Clarification is needed. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 1 , 8-11 , 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raviprakash et al. (10,862,521) , hereafter called RAVIPRAKASH , in view of Li et al. (12,283,930) hereafter called LI . Regarding claim s 1 and 15 , RAVIPRAKASH discloses claimed invention except having the source is grounded via a resistor. RAVIPRAKASH (Fig. 6, 9 and 10 ) discloses a circuit comprising: a first circuit (1001) comprising a first transmission line ( L1) starting from a first terminal and terminating at a second terminal, the first terminal being coupled to a source (Vs) to receive a first signal, the source being coupled to ground via a first resistor (Rs) characterized by a first resistance the first transmission line being characterized by a first impedance equal to the first resistance , see column 6, lines 30-38 ; a second circuit (1002) comprising at least a second resistor (R1) characterized by a second resistance and a third resistor (R2) characterized by a third resistance , see 920 of Figure 9B , the second resistor being coupled between the second terminal and ground, the third resistor being coupled between the second terminal and a third terminal, the second circuit being configured to transmit the first signal from the first second terminal to the second third terminal and provide a gain to a second signal at the third terminal over the first signal; and a third circuit (1003) comprising a second transmission line ( L2 ) starting from the third terminal and terminating with a fourth resistor (R T ) , the fourth resistor being grounded and characterized by a fourth resistance, the second transmission line being characterized by a second impedance equal to the fourth resistance. LI (Fig. 3) discloses a circuit having source grounded via resistor (Rs). Accordingly, it would have been obvious in view of the reference, taken as a whole, to have modified the circuit of RAVIPRAKASH to have included a grounded source via a resistor, as taught by LI, since LI disclose their used in a similar context, also see col. 10, line 62 to col. 11, line 14, thereby suggesting the obviousness of such a modification. Regarding claims 8-10, wherein the claimed subject matters are considered a matter of design engineering and configuration in the field of RF power amplifier, see details description of Figures 7 and 8. Regarding claim 11 , wherein the third resistor comprises an array of resistors with different resistances controlled by respective switches. This is well-known configuration of a variable resistor, wherein RAVIPRAKASH ’s attenuator is also disclosed variable resistor. Regarding claim 14, LI (Fig. 3) discloses a fourth circuit (300) having the connection as claimed. Allowable Subject Matter Claims 2-7 , 12, 13 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claims 2-7 and 16-20 , prior art(s) does not disclose the second transmission line comprises one or more inductor-capacitor segments coupled in series, wherein the each inductor in the one or more inductor-capacitor segments is arranged in series in the second transmission line and each capacitor of the one or more inductor-capacitor segments is arranged in parallel between the second transmission line and the ground to configure the second transmission line with an impedance-matched termination. Regarding claim 12, prior art(s) does not disclose the switch comprises a transistor with a gate terminal coupled to a first terminal of a fifth resistor with a resistance greater than 100 KOhm, the fifth resistor having a second terminal coupled to a control signal. Regarding claim 13, prior art(s) does not disclose the first transmission line comprises one or more inductor-capacitor segments coupled in series, wherein each inductor in the one or more inductor-capacitor segments is arranged in series in the first transmission line and each capacitor of the one or more inductor-capacitor segments is arranged in parallel between the first transmission line and the ground. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference ( s ) cited in PTO-892 show further analogous prior art circuitry. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767 . The examiner can normally be reached from 8:3 0 AM – 5 :00 PM EST. Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LINDGREN BALTZELL ANDREA can be reached on (571) 272- 5918 . The fax phone numbers for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application lnformation Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (E BC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Oct 30, 2023
Application Filed
Mar 19, 2026
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
96%
With Interview (+1.9%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1183 resolved cases by this examiner. Grant probability derived from career allowance rate.

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