Prosecution Insights
Last updated: May 29, 2026
Application No. 18/498,051

METHOD OF MANUFACTURING DISPLAY DEVICE

Non-Final OA §103
Filed
Oct 31, 2023
Priority
Nov 25, 2022 — JP 2022-188205
Examiner
PUNCHBEDDELL, SEYON ALI-SIMAH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Maqnolia White Corporation
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
58 granted / 76 resolved
+8.3% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
20 currently pending
Career history
107
Total Applications
across all art units

Statute-Specific Performance

§103
91.9%
+51.9% vs TC avg
§102
4.1%
-35.9% vs TC avg
§112
3.3%
-36.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 76 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3-6, 10-12, 16-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Choung et al. (US 2022/0077251 A1; hereinafter “Choung”), and further in view of Park et al. (US 2021/0384465 A1; hereinafter “Park”). In regard to claim 1, Choung teaches a method of manufacturing a display device, comprising: forming a lower electrode (metal layers 104 ) on a base (a substrate 102) including a first main surface (the top surface of the substrate 102) on which a plurality of display elements (elements that comprise a sub-pixel 106) are formed and a side surface connected to the first main surface (the side surface of the substrate would be connected to the top surface due to being a single structure) (Fig. 1B, Fig. 4A and paragraphs 37 and 45), the lower electrode being on the first main surface of the base (the metal layer 104 is shown on the top surface of the substrate in Fig. 4A); forming a rib (PDL structures 126) including a pixel aperture which overlaps the lower electrode (an opening between PDL structures 126 that correlates to a sub-pixel 108a is shown in Fig. 4C) (Fig. 4C and paragraph 47); forming a partition on the rib (inorganic overhang structures 110) (Fig. 4C and paragraph 47); forming a first deposition film (OLED material 112) which includes a first organic layer which covers the lower electrode via the pixel aperture and a first upper electrode (a cathode 114) which covers the first organic layer (the organic material in the OLED material 112 is shown over the lower electrode in the opening wit that corresponds to the first sub-pixel 108a, with the cathode 114 disposed over the OLED material 112 in Fid. 4F) (Fig. 4F and paragraph 47); and forming a first sealing layer (an encapsulation layer 116) which covers the first deposition film (the encapsulation layer 116 is shown over the OLED material 112 in Fig. 4D) (Fig. 4D and paragraph 48), the first sealing layer including a first upper end portion (the top surface of the encapsulation layer 116 that extend across the device not over the sub-pixel 108a) which covers the first deposition film and a first side end portion (the side surface of the encapsulation layer 116 that extend across the device not over the sub-pixel 108a) connected to the first upper end portion (the top surface of the encapsulation layer 116 would be connected to the side surface of the encapsulation layer 116 due to it being one whole structure) (Fig. 4D). However, Choung fails to explicitly teach the first sealing layer including the first upper end portion which covers the first deposition film and the first side end portion connected to the first upper end portion, which covers the side surface. Park teaches a method of manufacturing a display device, comprising: a first sealing layer (a first inorganic encapsulation layer 310) including a first upper end portion (the top surface of the first inorganic encapsulation layer 310) which covers a first deposition film (a display element layer DEL) and a first side end portion (the side surface of the first inorganic encapsulation layer 310) connected to the first upper end portion (the side surface of the first inorganic encapsulation layer 310 is shown connected to the top surface in Fig. 10A) (Fig. 10A and paragraphs 188 and 198), which covers a side surface (a side surface of a substrate 100 is shown covered in Fig. 10A). It would’ve been obvious to one skilled in the art to combine the teachings of Choung in view of Park to have the first sealing layer including the first upper end portion cover the first deposition film and the first side end portion connected to the first upper end portion, which covers the side surface since this allows for moisture and oxygen protection of pixels as taught by Park (paragraph 156). In regard to claim 3, Choung teaches forming a first resist (a resist 408) on the first sealing layer after forming the first sealing layer (a resist 408 is formed in a well 410 of the first sub-pixel 108a) (Fig. 4E and paragraph 49); removing parts of the first sealing layer and the first deposition film, which are exposed from the first resist by etching (the encapsulation layer 116, the cathode 114, and the OLED material 112 exposed by resist 408 may be removed by wet etch processes) (Fig. 4F and paragraph 49); and removing the first resist (the resist 408 is removed, as shown in FIG. 4F) (Fig. 4F and paragraph 49). In regard to claim 4, Choung teaches wherein the removing the parts of the first sealing layer and the first deposition film, which are exposed from the first resist includes removing the first upper end portion and the first side end portion (the portions of the encapsulation layer 116 the that extend across the device not disposed over the sub-pixel 108a are removed as shown in Fig. 4G). In regard to claim 5, Choung teaches wherein the first deposition film further includes a cap layer (a plug 122) which covers the first upper electrode (the plug the resist 408 is corresponds to the plug 122) (Fig. 4I and paragraph 49). In regard to claim 6, Choung teaches wherein the first sealing layer is formed of an inorganic insulating material (the encapsulation layer 116 includes the non-conductive inorganic material) (paragraph 34). In regard to claim 10, Choung teaches wherein the partition includes a lower portion (a lower portion 110A) disposed on the rib and an upper portion (an upper portion 110B) disposed on the lower portion and having a width greater than that of the lower portion (the upper portion 110B is shown with a greater width than the lower portion 110A in Fig. 4E) (Fig. 4E and paragraphs 30 and 37). In regard to claim 11, Choung teaches wherein the partition surrounds the pixel aperture in plan view (the inorganic overhang structures 110 is shown surrounding the opening between PDL structures 126 in Fig. 1C). In regard to claim 12, Choung teaches wherein the first upper end portion and the first side end portion are formed to be integrated with each other (the top surface and side surface of the encapsulation layer 116 are integrated with one another due to being a single layer). In regard to claim 16, Choung in view of Park teaches wherein the first side end portion extends further downward from the first main surface (the side surface of the first inorganic encapsulation layer 310 is shown extending pass the top surface of the substrate 100 in Park Fig. 10A). In regard to claim 17, Choung in view of Park teaches wherein the first side end portion is formed to cover the side surface in its entirety (the side surface of the first inorganic encapsulation layer 310 is on the shown side surface of the substrate 100 in Park Fig. 10A). In regard to claim 18, wherein the first side end portion covers an end portion of the first deposition film (the side surface of the first inorganic encapsulation layer 310 is shown on the side surface of the a display element layer DEL in a third groove Gv3 in Park Fig. 10A). (Fig. 10A and paragraph 150). In regard to claim 20, Choung teaches forming a third resist (a resist 416) on the third sealing layer, after forming the third sealing layer (the resist 416 is formed on the encapsulation layer 116 over a second sub-pixel 108b as shown in Fig. 4M) (Fig. 4M and paragraphs 51-52); removing parts of the third sealing layer and the third deposition film, which are exposed from the third resist by etching (as shown in FIGS. 4N and 4O, the encapsulation layer 116, the cathode 114, and the OLED material 112 exposed by the resist 416 are removed) ((Fig. 4N, Fig. 4O and paragraph 52); and removing the third resist (the resist 416 is shown removed in Fig. 4N). Claim Objections Claims 2, 7-9, 13-15 and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In regard to claim 2, Choung is considered a close prior art of record. However, Choung fails to teach the first sealing layer further includes a lower end portion connected to the first side end portion, which covers at least a part of the second main surface. Choung is silent regarding the placement of the first sealing layer on the bottom of the device. Claims 13-15 are objected to due to their dependency on claim 2. In regard to claim 7, Park is considered a close prior art of record. However, Park fails to teach forming a second sealing layer which covers the second deposition film, wherein the second sealing layer includes a second upper end portion which covers the second deposition film and a second side end portion which is connected to the second upper end portion and covers the side surface. Park is silent regarding the removal of the elements mapped as the sealing layer. Claims 8-9 are objected to due to their dependency on claim 7. In regard to claim 19, Choung is considered a close prior art of record. However, Choung fails to teach the first upper end portion is in contact with the cap layer. Choung fails to shown the element mapped as the first upper end portion in contact with any element mapped as a cap layer within the device. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEYON ALI-SIMAH PUNCHBEDDELL/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 31, 2023
Application Filed
Mar 02, 2026
Non-Final Rejection mailed — §103
May 07, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
83%
With Interview (+6.4%)
3y 6m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 76 resolved cases by this examiner. Grant probability derived from career allowance rate.

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