DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
This Office Action is in response to Applicant’s application 18/498,537 filed on March 17 2026 in which claims 1-18 and 22-23 are pending.
Drawings
The drawings submitted on September 2, 2021 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS), filed on October 31 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Priority
Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file.
Notation
References to patents will be in the form of (C:L) where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of (¶ XXXX).
Election/Restrictions
Applicant’s election without traverse of claims 1-18 and 22-23 in the reply filed on March 17 2026 is acknowledged. Claims 19-21 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 19-21 are canceled.
Claim 23 is a new added independent claim included in the response filed on March 17 2026. Claim 23 is treated as a linking claim since the applicant claims a method which is drawn to invention II, however the claim limitations are related to a device claim, as in invention I. The office will examine following claim since the limitations are related to device claim. However, if during prosecution Applicant’s amend the claim to have method steps or method of making then the claim will be withdrawn to a non-elected invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 22 and 23 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by Schaller (US 2021/0005539 A1; hereinafter “Schaller”).
Regarding claim 1, Schaller teaches in Figure 4 and related text e.g. a semiconductor device (Fig.4), comprising:
an electrically conductive carrier (4C, Fig.4; ¶ 0038);
a semiconductor chip (6B, Fig.4; ¶ 0038) arranged on the electrically conductive carrier (4C, Fig.4);
a layer stack arranged between the electrically carrier (4C) and the semiconductor chip (4C) and comprising a plurality of dielectric layers (8A and 8B; Fig.4; ¶ 0034),
wherein the layer stack galvanically (¶ 0018) isolates the semiconductor chip (6B) and the electrically conductive carrier (4C) form one another (8 can stack galvanically isolate between 6b and 4C through), and
wherein at least one of the plurality of dielectric layers (8A and 8B; Fig.4) is coated with an electrically conductive coating (10B and 10C; 10 can be electrically conductive or electrically insulating, ¶ 0019).
Regarding claim 2, Schaller teaches the electrically conductive coating is configured to reduce an electric field strength in a selected spatial region of the semiconductor device (10B-10C are made of electrically conductive coating can reduce an electrically filed strength; ¶ 0019).
Regarding claim 3, Schaller teaches the selected spatial region comprises a boundary region at which the semiconductor chip (6b), the layer stack (8a and 8b), and an encapsulation material (12; Fig.4) encapsulating the semiconductor chip adjoin adjoining one another (12 encapsulating all the structure as shown in Figure 4).
Regarding claim 4, Schaller teaches the electrically conductive coating (10B-10C; Fig. 4) is configured to form an electrode of a capacitor (10B and 10C can forms the electrodes of a capacitor), and the electric field strength is reduced based on a capacitance formed by the capacitor (the field of the capacitance is controlled by the thickness of 8B; Fig.4).
Regarding claim 5, Schaller teaches an adhesive layer (10A) comprising an electrically conductive filler and arranged between the electrically conductive carrier (4C) and the semiconductor chip (6b).
Regarding claim 22, Schaller teaches an apparatus (400, ¶ 0008) in Figure 4 and related text e.g. a semiconductor device (Fig.4), comprising:
an electrically conductive carrier (4C, Fig.4; ¶ 0038);
a semiconductor chip (6B, Fig.4; ¶ 0038) arranged on the electrically conductive carrier (4C, Fig.4);
a layer stack arranged between the electrically carrier (4C) and the semiconductor chip (4C) and comprising a plurality of dielectric layers (8A and 8B; Fig.4; ¶ 0034),
wherein the layer stack galvanically (¶ 0018) isolates the semiconductor chip (6B) and the electrically conductive carrier (4C) form one another (8 can stack galvanically isolate between 6b and 4C through), and
wherein at least one of the plurality of dielectric layers (8A and 8B; Fig.4) is coated with an electrically conductive coating (10B and 10C; 10 can be electrically conductive or electrically insulating, ¶ 0019).
Regarding claim 23, Schaller teaches a method (400, ¶ 0008) in Figure 4 and related text e.g. comprising:
providing electrical insulation (8B and 8A, Fig.4; ¶ 0034) within a device (400), comprising:
an electrically conductive carrier (4C, Fig.4; ¶ 0038);
a semiconductor chip (6B, Fig.4; ¶ 0038) arranged on the electrically conductive carrier (4C, Fig.4);
a layer stack arranged between the electrically carrier (4C) and the semiconductor chip (4C) and comprising a plurality of dielectric layers (8A and 8B; Fig.4; ¶ 0034),
wherein the layer stack galvanically (¶ 0018) isolates the semiconductor chip (6B) and the electrically conductive carrier (4C) form one another (8 can stack galvanically isolate between 6b and 4C through), and
wherein at least one of the plurality of dielectric layers (8A and 8B; Fig.4) is coated with an electrically conductive coating (10B and 10C; 10 can be electrically conductive or electrically insulating, ¶ 0019).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9-12 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hoegerl et al. (US 2021/0088600 A1; hereinafter “Hoegerl”) in view of Carpenter et al. (US 2021/0066217 A1; hereinafter “Carpenter”).
Regarding claim 9, Hoegerl teaches in Figure 4 and related text e.g. a semiconductor device (Fig.4), comprising:
an electrically conductive carrier (2, Fig.1; ¶ 0028);
a dielectric structure (6 and 8; Fig.1; ¶ 0026) arranged on the electrically conductive carrier (2); and
a semiconductor chip (10, Fig.1; ¶ 0026) arranged on a mounting surface of the dielectric structure (6 and 8; Fig.1),
wherein the dielectric structure (6 and 8) galvanically isolates the semiconductor chip (10) and the electrically conductive carrier (2) from one another (¶ 00029), and the dielectric structure (6 and 8) configured to enlarge a creepage path between the semiconductor chip and the electrically conductive carrier (Fig. 1; ¶ 0033: creepage path between the semiconductor chip (10) and carrier (2)).
Schaller does not teach wherein the dielectric structure comprises a plurality of elevations which project from the mounting surface and surround the semiconductor chip.
However, Carpenter teaches the dielectric structure (406, Fig.1; ¶0015) comprises a plurality of elevations (412, Fig.9; ¶ 0034) which project from the mounting surface (mounting surface of 406) and surround the semiconductor chip (416, Fig.9; 0034).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date, to have the dielectric structure comprises a plurality of elevations which project from the mounting surface and surround the semiconductor chip in the device of Schaller as taught by Carpenter for the purpose of improving the power transfer efficiency (¶ 0014).
Regarding claim 10, Schaller as modified by Carpenter teaches wherein the elevations comprise a plurality of chamfered shielding (Carpenter, 412 can be treated as chamfered shielding in Figure 9; ¶ 0048) or a plurality of rib structures.
Regarding claim 11, Schaller does not teach wherein a geometric shape of the elevations is directed oppositely to an electric field based on an electric potential difference between the semiconductor chip and the electrically conductive carrier.
However, Carpenter teaches the shape of the 412 and 410 can have different shapes and sizes (¶ 0048)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date, to have a geometric shape of the elevations is directed oppositely to an electric field based on an electric potential difference between the semiconductor chip and the electrically conductive carrier in the device of Schaller and Carpenter since such modification would have involved a mere change in size/shape of a component. A change in shape is generally recognized as being with the level of ordinary skill in the art MPEP § 2144.04 IV B.
Regarding claim 12, Schaller teaches a plurality of electrically conductive layers (14, Fig.1; ¶ 0034; Can be formed from conductive material) embedded in the dielectric structure (between 8 and 6 and on top of 6) and configured to form at least one capacitor (any two conductors and insulator can form a capacitor), wherein a capacitance formed by the at least one capacitor is configured to reduce an electric field strength in a selected spatial region of the semiconductor device (at least one capacitor can reduce an electrical field strength; ¶ Fig.1).
Regarding claim 14, Schaller teaches at least one electrically conductive layer of the plurality of electrically conductive layers is electrically connected to an electrical output (all the electrical layers are connected to 4, Fig.1; ¶ 0035), and the electrical output outputs a signal if a partial discharge occurs between the semiconductor chip and the at least one electrically conductive layer in the dielectric structure (the discharge can between the chip 10 and any conductive layer (14) formed in the device 100, Fig.1).
Regarding claim 15, Schaller teaches wherein the dielectric structure (6, Fig.1) is arranged directly on the electrically conductive carrier (2, Fig.1).
Regarding claim 16, Schaller teaches the dielectric structure is produced based on a 3D printing method (the process of forming a product claim is not patentable as the presence of process limitation on a product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product. In re Stephens 145 USPQ 656 (CCPA 1965)).
Regarding claim 17, Schaller teaches an electrically conductive coating (14, Fig.1) arranged between the mounting surface of the dielectric structure (6) and the semiconductor chip (10), wherein the electrically conductive coating is configured to reduce an electric field strength in a selected spatial region of the semiconductor device (the conductive coating can be configured to reduce an electric field strength in a selected spatial region of the semiconductor device).
Regarding claim 18, Schaller teaches furthermore comprising: at least one bond wire (16; ¶0026), wherein the elevations are configured to mechanically support the at least one bond wire in order to prevent a sagging or a bending of the at least one bond wire (elevation of the wire bond between the chip (10) and the lead (4, Fig1) can prevent sagging or bending of the at least one bond wire).
Allowable Subject Matter
Claims 6-8, 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 is objected to since the prior art reference does not teach the following limitations: “...a securing layer comprising an industrial carbon black and arranged between the electrically conductive carrier and the semiconductor chip” with the rest of each of the limitations of claim 5 and 1.
Claim 7 is objected to since the following claim is dependent on claim 5.
Claim 8 is objected to since the prior art reference does not teach the following limitations: “...a plurality of openings are formed in the electrically conductive coating, and are configured to prevent eddy currents from arising in the electrically conductive coating.”
Claim 13 is objected to since the prior art reference does not teach the following limitations: “a geometric shape and relative arrangement of the plurality of electrically conductive layers are configured to lengthen a discharge path extending from the semiconductor chip through the dielectric structure to the electrically conductive carrier” with each of the limitations of claims 12 and 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mounir S Amer whose telephone number is (571)270-3683. The examiner can normally be reached Monday-Friday 9:00-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mounir S Amer/Primary Examiner, Art Unit 2818
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