DETAILED ACTION
This office action is in response to the request for Continuation filed on January 2, 2026 in application 18/498,58.
Claims 1-20 are presented for examination. Claims 1, 11-12 are amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: Such claim limitation(s) is/are: “means for receiving raw debug data, means for generating a debug trace packet, and means for transmitting, via a trace interconnect bus” in claim 11.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof. The instant specification states “means” are implemented as processor-based device (para. 67-70).
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 U.S.C. § 101
35 U.S.C. § 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-10, 12-20 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to an abstract idea without significantly more.
As to claim 1: (claim 12 recited similar limitations)
Step 1 Analysis: Is the claim to a process, machine, manufacture or composition of matter? See MPEP § 2106.03.
Yes, the claim is to a device.
Step 2A Prong One Analysis: Does the claim recite an abstract idea, law of nature, or natural phenomenon? See MPEP § 2106.04(II)(A)(1).
Yes, the limitation “generate a debug trace packet comprising the raw debug data in lieu of formatted trace data” is the abstract idea of a mental process that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper (including an observation, evaluation, judgment, opinion). See MPEP § 2106.04(a)(2)(III).
Step 2A Prong Two Analysis: Does the claim recite additional elements that integrate the judicial exception into a practical application? See MPEP § 2106.04(d).
No, the limitation “A processor-based device, comprising: a trace interconnect bus; a subsystem circuit comprising a debug transmit circuit; and an input/output (I/O) endpoint circuit; the debug transmit circuit configured to: receive raw debug data from the subsystem circuit; and transmit the debug trace comprising the raw debug data to the I/O endpoint circuit via the trace interconnect bus during a period of trace interconnect bus inactivity” is an additional element that amounts to adding the words “apply it” (or an equivalent) with the judicial exception, or merely uses a computer in its ordinary capacity as a tool to perform an existing process. See MPEP §§ 2106.04(d), 2106.05(f)(2).
Step 2B Analysis: Does the claim recite additional elements that amount to significantly more than the judicial exception? See MPEP § 2106.05.
No, the limitation “a processor-based device, comprising: a trace interconnect bus; a subsystem circuit comprising a debug transmit circuit; and an input/output (I/O) endpoint circuit; the debug transmit circuit” is an additional element that amounts to adding the words “apply it” (or an equivalent) with the judicial exception, or merely uses a computer in its ordinary capacity as a tool to perform an existing process. See MPEP § 2106.05(f)(2).
No, the limitation “receive raw debug data from the subsystem circuit; and transmit the debug trace comprising the raw debug data to the I/O endpoint circuit via the trace interconnect bus during a period of trace interconnect bus inactivity” is an additional element that amounts to adding insignificant extra-solution activity to the judicial exception. See MPEP § 2106.05(g). Furthermore, the additional element is directed to receiving or transmitting data over a network / performing repetitive calculations / electronic recordkeeping / storing and retrieving information in memory / electronically scanning or extracting data from a physical document, which the courts have recognized as well-understood, routine, and conventional when they are claimed in a generic manner. See MPEP § 2106.05(d)(II).
As to claims 2-10: (claims 13-20 recited similar limitations)
Step 1 Analysis: Is the claim to a process, machine, manufacture or composition of matter? See MPEP § 2106.03. Yes, the claim is to a devices
Step 2A Prong One Analysis: Does the claim recite an abstract idea, law of nature, or natural phenomenon? See MPEP § 2106.04(II)(A)(1). The analysis of the parent claim is incorporated.
Step 2A Prong Two Analysis: Does the claim recite additional elements that integrate the judicial exception into a practical application? See MPEP § 2106.04(d). The analysis of the parent claim is incorporated.
Step 2B Analysis: Does the claim recite additional elements that amount to significantly more than the judicial exception? See MPEP § 2106.05. The analysis of the parent claim is incorporated.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-6, 11-13, 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Talvitie (US 2024/0044979) in further view of Mutschler et al. (US 2023/0089389) in further view of Aphale (US 2012/0079324).
In regard to claim 1, Talvitie teaches a processor-based device, comprising:
a trace interconnect bus (main system bus, fig. 2, 202, para. 82, 85);
a subsystem circuit comprising a debug transmit circuit (trace and debug logic, fig. 2, 203, para. 85); and
an input/output (I/O) endpoint circuit (external workstation can be connected to the external interface for receiving the trace data for analysis, para. 77);
the debug transmit circuit configured to:
receive debug data from the subsystem circuit (the trace and debug connections 214, 215 carry trace and debug data, para. 98, fig. 2);
generating a debug trace packet (generate trace, para. 4, 41); and
transmit the debug trace to the I/O endpoint circuit via the trace interconnect bus (outputting trace data through the external trace port, para. 46).
Talvitie does not explicitly teach receiving raw debug data, the raw debug data comprising data generated by the subsystem circuit in a raw state that does not conform with a trace format, generating and transmit the debug trace packet comprising raw debug data in lieu of formatted trace data.
Mutschler et al. teach of trace files can comprises composite log files, structured data files, raw data collections, or other various formats which are provided to users or user interfaces for further analysis and debug operations provided by analysis system 140 for host system 110, endpoint devices 120 and communication link 150 (para. 32).
It would have been obvious to modify the device of Talvitie by adding Mutschler et al. transaction analyzer. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would provide various formats in which the trace files can be provided (para. 32).
Talvitie and Mutschler et al. does not explicitly teach transmitting the debug trace during a period of trace interconnect bus inactivity.
Aphale teaches of the availability of the trace output may be determined based on a threshold percentage of intermediate trace buffer 806 and/or a threshold period of inactivity (para. 40).
It would have been obvious to modify the device of Talvitie and Mutschler et al. by adding Aphale firmware tracing data. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would provide multiple implementations of the trace buffer output (para. 40).
In regard to claim 2, Talvitie teaches the processor-based device of claim 1, wherein the trace interconnect bus comprises an Advanced Microcontroller Bus Architecture (AMBA) trace bus (ATB) interconnect bus (main system bus may be Advanced Microcontroller Bus Architecture (AMBA) bus, para. 32, any buses configured only to communicate debug or trace data such as any AMBA trace bus (ATB) or ARM CoreSight Debug Access Port Bus (DAP, para. 33) .
In regard to claim 4, Talvitie teaches the processor-based device of claim 1, wherein the debug transmit circuit is further configured to: receive a debug enable signal; and responsive to receiving the debug enable signal, selectively enable debug functionality of the debug transmit circuit (main system bus comprises multiplexers 216, 217, 218 and a bus arbiter which controls the multiplexers using control lines 227, para. 91-99, fig. 3).
In regard to claim 5, Talvitie teaches the processor-based device of claim 4, wherein: the debug transmit circuit comprises one of a plurality of debug transmit circuits of a corresponding plurality of subsystem circuits; and the debug transmit circuit is configured to selectively enable the debug functionality of the debug transmit circuit by being configured to selectively enable only the debug transmit circuit among the plurality of debug transmit circuits (main system bus comprises multiplexers 216, 217, 218 and a bus arbiter which controls the multiplexers using control lines 227, para. 91-99, fig. 3).
In regard to claim 6, Talvitie teaches the processor-based device of claim 4, wherein the debug transmit circuit is further configured to transmit a training pattern to the I/O endpoint circuit, responsive to receiving the debug enable signal (enabling the DWT and BPU of each processor to receive debug instructions from the trace and debug logic, para. 97).
In regard to claim 11, Talvitie teaches a processor-based device, comprising:
means for receiving debug data from a subsystem circuit of the processor-based device (the trace and debug connections 214, 215 carry trace and debug data, para. 98, fig. 2);
means for generating a debug trace packet comprising the debug data (generate trace, para. 4, 41); and
means for transmitting, via a trace interconnect bus of the processor-based device, the debug trace packet comprising the debug data to an I/O endpoint circuit of the processor-based device (outputting trace data through the external trace port, para. 46).
Talvitie does not explicitly teach receiving raw debug data, the raw debug data comprising data generated by the subsystem circuit in a raw state that does not conform with a trace format, generating and transmit the debug trace packet comprising raw debug data in lieu of formatted trace data.
Mutschler et al. teach of trace files can comprises composite log files, structured data files, raw data collections, or other various formats which are provided to users or user interfaces for further analysis and debug operations provided by analysis system 140 for host system 110, endpoint devices 120 and communication link 150 (para. 32).
Refer to claim 1 for motivational statement.
Talvitie and Mutschler et al. does not explicitly teach transmitting the debug trace packet during a period of trace interconnect bus inactivity.
Aphale teaches of the availability of the trace output may be determined based on a threshold percentage of intermediate trace buffer 806 and/or a threshold period of inactivity (para. 40).
Refer to claim 1 for motivational statement.
In regard to claim 12, Talvitie teaches a method for routing raw debug data using trace infrastructure, comprising:
receiving, by a debug transmit circuit of a subsystem circuit of a processor-based device, debug data from the subsystem circuit (the trace and debug connections 214, 215 carry trace and debug data, para. 98, fig. 2);
generating, by the debug transmit circuit, a debug trace packet comprising the debug data (generate trace, para. 4, 41); and
transmitting, by the debug transmit circuit via a trace interconnect bus of the processor-based device, the debug trace packet comprising the debug data to an input/output (I/O) endpoint circuit of the processor-based device (outputting trace data through the external trace port, para. 46).
Talvitie does not explicitly teach receiving raw debug data, the raw debug data comprising data generated by the subsystem circuit in a raw state that does not conform with a trace format, generating and transmit the debug trace packet comprising raw debug data in lieu of formatted trace data.
Mutschler et al. teach of trace files can comprises composite log files, structured data files, raw data collections, or other various formats which are provided to users or user interfaces for further analysis and debug operations provided by analysis system 140 for host system 110, endpoint devices 120 and communication link 150 (para. 32).
Refer to claim 1 for motivational statement.
Talvitie and Mutschler et al. does not explicitly teach transmitting the debug trace packet during a period of trace interconnect bus inactivity.
Aphale teaches of the availability of the trace output may be determined based on a threshold percentage of intermediate trace buffer 806 and/or a threshold period of inactivity (para. 40).
Refer to claim 1 for motivational statement.
In regard to claim 13, Talvitie teaches the method of claim 12, wherein the trace interconnect bus comprises an Advanced Microcontroller Bus Architecture (AMBA) trace bus (ATB) interconnect bus (main system bus may be Advanced Microcontroller Bus Architecture (AMBA) bus, para. 32, any buses configured only to communicate debug or trace data such as any AMBA trace bus (ATB) or ARM CoreSight Debug Access Port Bus (DAP, para. 33) .
In regard to claim 15, Talvitie teaches the method of claim 12, further comprising: receiving, by the debug transmit circuit, a debug enable signal; and responsive to receiving the debug enable signal, selectively enabling debug functionality of the debug transmit circuit (main system bus comprises multiplexers 216, 217, 218 and a bus arbiter which controls the multiplexers using control lines 227, para. 91-99, fig. 3).
In regard to claim 16, Talvitie teaches the method of claim 15, wherein: the debug transmit circuit comprises one of a plurality of debug transmit circuits of a corresponding plurality of subsystem circuits of the processor-based device; and selectively enabling debug functionality of the debug transmit circuit comprises selectively enabling only the debug transmit circuit among the plurality of debug transmit circuits (main system bus comprises multiplexers 216, 217, 218 and a bus arbiter which controls the multiplexers using control lines 227, para. 91-99, fig. 3).
In regard to claim 17, Talvitie teaches the method of claim 15, further comprising transmitting, by the debug transmit circuit, a training pattern to the I/O endpoint circuit, responsive to receiving the debug enable signal (enabling the DWT and BPU of each processor to receive debug instructions from the trace and debug logic, para. 97).
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Claims 3, 7-10, 14 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Talvitie (US 2024/0044979) in further view of Mutschler et al. (US 2023/0089389) in further view of Aphale (US 2012/0079324) in further view of Menon et al. (US 2017/0286254).
In regard to claim 3, Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach the processor-based device of claim 1, wherein the period of trace interconnect bus inactivity comprises a boot stage (early boot debug capture the traces, para. 48).
It would have been obvious to modify the device of Talvitie, Mutschler et al. and Aphale by adding Menon et al. debugger. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in debugging of boot data (para. 48)
In regard to claim 7, Talvitie teach the processor-based device of claim 1, wherein the I/O endpoint circuit comprises a debug receive circuit configured to: transmit the raw debug data to a trace sink (trace data output by the STM can be connected to the TPIU and/or other trace sinks, para. 85).
Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach receive the debug trace packet comprising the raw debug data from the debug transmit circuit; extract the raw debug data from the debug trace packet (crashDump and CrashLog are features to enable the collection and extraction of useful debug information, para. 31-32).
Refer to claim 3 for motivational statement.
In regard to claim 8, Talvitie teaches the processor-based device of claim 7, wherein the trace sink comprises one or more of a system memory, an embedded trace buffer, a Trace Port Interface Unit (TPIU), and one or more General Purpose I/O (GPIO) pins (trace data output can be connected to the TPIU and/or other trace sinks, para. 85).
In regard to claim 9, Talvitie teaches the processor-based device of claim 7, wherein: transmit the raw debug data to the trace sink based on the I/O configuration register (trace data output by the STM can be connected to the TPIU and/or other trace sinks, para. 85).
Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach the debug receive circuit is configured to extract the raw debug data and the debug receive circuit (crashDump and CrashLog are features to enable the collection and extraction of useful debug information, para. 31-32) comprises an I/O configuration register specifying one or more of a number of General Purpose I/O (GPIO) pins and an identification of one or more bits of the raw debug data (in open-chassis debug, the JTAG Test Access Port (TAP) interface as well as the Trace output provided by a trace aggregator are brought over general purpose input/output (GPIO) pins, para. 21).
Refer to claim 3 for motivational statement.
In regard to claim 10, Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach the processor-based device of claim 1, integrated into a device selected from the group consisting of: a set top box; an entertainment unit; navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter (target system comprises a smartphone, tablet, laptop IoT, SmartTV, car, server or any other portable device, para. 23).
Refer to claim 3 for motivational statement.
In regard to claim 14, Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach the method of claim 12, wherein the period of trace interconnect bus inactivity comprises a boot stage (early boot debug capture the traces, para. 48).
Refer to claim 3 for motivational statement.
In regard to claim 18, Talvitie teaches the method of claim 12, further comprising: transmitting, by the debug receive circuit, the raw debug data to a trace sink (trace data output by the STM can be connected to the TPIU and/or other trace sinks, para. 85).
Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach receiving, by a debug receive circuit of the I/O endpoint circuit, the debug trace packet comprising the raw debug data from the debug transmit circuit; extracting, by the debug receive circuit, the raw debug data from the debug trace packet (crashDump and CrashLog are features to enable the collection and extraction of useful debug information, para. 31-32).
Refer to claim 3 for motivational statement.
In regard to claim 19, Talvitie teaches the method of claim 18, wherein the trace sink comprises one or more of a system memory, an embedded trace buffer, a Trace Port Interface Unit (TPIU), and one or more General Purpose I/O (GPIO) pins (trace data output can be connected to the TPIU and/or other trace sinks, para. 85).
In regard to claim 20, Talvitie teaches the method of claim 18, wherein: transmitting the raw debug data to the trace sink comprises transmitting the raw debug data based on the I/O configuration register (trace data output by the STM can be connected to the TPIU and/or other trace sinks, para. 85).
Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach extracting the raw debug data comprises extracting the raw debug data based on the I/O configuration register (crashDump and CrashLog are features to enable the collection and extraction of useful debug information, para. 31-32); and the debug receive circuit comprises an I/O configuration register specifying one or more of a number of General Purpose I/O (GPIO) pins and an identification of one or more bits of the raw debug data (in open-chassis debug, the JTAG Test Access Port (TAP) interface as well as the Trace output provided by a trace aggregator are brought over general-purpose input/output (GPIO) pins, para. 21).
Refer to claim 3 for motivational statement.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Futaki et al. (US 2013/0171944) managing trace sessions
Ghamami (US 2007/0076632) transmit trace signal during idle steps
Ashfield et al. (US 8,001,428) trace data slaves connected via bus (AMBA bus)
Ivan et al. (US 2016/0105200) trace bus (ATB), bus architecture (AMBA)
Assouad et al. (US 6,119,254) hardware tracing/logging
Naaseh-Shahry et al. (US 5,812,830) debug with raw mode trigger
Bharti et al. (US 2023/0214311) debug by saving raw and processed transaction data
Ciubotariu (US 2022/0335013) raw event trace logs
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Mutschler et al. (US 11,882,038) trace file can be raw data collection
Andrade et al. (US 2011/0040734) traces from raw data sources
Cruickshank et al. (US 7,802,149) debug trace program having raw streaming data
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Mysore et al. (US 2024/0378062) trace boot and GPIO
Delson (US 2024/0235982) trace data packet record a node identifier in a header (para. 116, fig. 6)
Zhong (US 2021/0374090) trace and debug port
Ansari et al. (US 10,896,119) trace buffer, boot, GPIO
Deiderich, III et al. (US 10,866,881) boot sequence and debug trace
Hoffmann (US 10,866,922) debug trace during boot cycle
Tufvesson et al. (US 10,180,890) debug interface
Mou et al. (US 9,952,963) bus debug trace
Grafton et al. (US 2016/0349326) debug trigger interface
Balkan et al. (US 8,402,314) debug registers
Beebe (US 2011/0060948) trace packets
Henson (US 10,372646) trace bus
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/Loan L.T. Truong/Primary Examiner, Art Unit 2114 HYPERLINK "mailto:Loan.truong@uspto.gov" Loan.truong@uspto.gov