DETAILED ACTION
This office action is in response to applicant’s remarks filed on June 17, 2026, in application 18/498,58.
Claims 1-20 are presented for examination. No claims are amended or cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In response to the 35 USC 112f interpretation, examiner thanked applicant for stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. Applicant stated that claim 11 is “properly construed under 35 USC 112f with the debug transmit circuit (para. 23-24 and fig. 1) as the corresponding structure disclosed in the specification” to read on the claimed limitations of “means for receiving raw debug data, means for generating a debug trace packet, and means for transmitting, via a trace interconnect bus” in claim 11. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
In regard to the 35 USC 101, applicant has stated that the claims are directed to an improvement in trace infrastructure technology “to carry raw debug data during periods of bus inactivity” thereby improving the debugging capability of the processor-based device (see applicant’s specification, para. 7-8, 11-13. Conventional trace packets may incur additional expense in terms of overhead and monetary cost due to the need for industry-standard, infrastructure-compliance tools to decode the packetized trace data for analysis, thereby improving the need to decode the packet and reduce overhead and monetary cost.
Applicant arguments filed, with regard to the claim rejections under 35 USC 103, have been fully considered but they are not persuasive.
Applicant stated that Mutschler’s “raw data collections” as “output format of already-captured and processed trace files assembled by an external analysis system from monitored bus traffic”, see Mutschler para. 32, are fundamentally different from claim 1 “raw debug data” as “data generated by the subsystem circuit in a raw state that does not conform with a trace format”. Applicant further stated that Mutschler does not teach generating a debug trace packet comprising raw debug data in lieu of formatted trace data
Examiner disagreed. Mutschler et al. teach of “all the various information monitored, stored or replicated by operations 213-216 and contained within data structures 217-220 can be assembled, at least in part, into one or more trace files 230. These trace files can comprise … raw data collections, or other various formats which are provided to ... user interfaces for further analysis and debug operations provided by analysis system”, para. 32. It is noted that the claimed limitation received and generated raw debug data into a debug trace packet is equated to Mutschler et al. assembled into one or more trace files comprises raw data collection. The claimed debug trace packet is generated to comprise raw debug data similarly, Mutschler et al. assembled the various monitored information into trace files comprises raw data collection.
Applicant further stated that Aphale fails to disclose or suggest the “transmitting the debug trace packet comprising the raw debug data to the I/O endpoint circuit via the trace interconnect bus during a period of trace interconnection bus inactivity. Applicant stated that Aphale stated that “the availability of the trace output may be determined based on a threshold percentage of intermediate trace buffer 806 and/or a threshold period of inactivity”, para. 40, where the threshold period of inactivity, where the inactivity refers to the intermediate trace buffer 806 and not inactivity of a trace interconnection bus. Applicant further stated that Aphale does not disclose or suggest a trace interconnection bus, Aphale transmits trace data through a “SAS communication link” which is fundamentally different from the claimed trace interconnection bus.
Examiner disagreed. As Aphale describes in para. 40, “the availability of the trace output may be determined based on a threshold percentage of intermediate trace buffer 806 and/or a threshold period of inactivity” where the threshold percentage of the intermediate trace buffer and the threshold period of inactivity are two criteria that could be determine by itself or together to determine the availability of the trace output. The term and/or is considered where the availability of the trace output could be determined by “or a threshold period of inactivity” where the intermediate trace buffer is not taken into consideration. Applicant stated that the inactivity refers to a period during which no new trace data is being written to the buffer and not the inactivity of a trace interconnection bus. Aphale does not describe the inactivity as a period of no new trace data being written to the buffer but teaches the opposite where the output availability is determined only by the period of inactivity without considering the threshold of the buffer. For the remarks of Aphale transmits trace data through a SAS communication link and not a bus, Aphale teaches of “although fig. 1-8 are discussed with regard to a SAS link/SAS topology/SAS environment, the exemplary embodiments are not restricted to the SAS domain. In one or more embodiments, any form of serial links (e.g. serial SCSI bus), parallel SCSI bus) or other communication links is within the scope of the exemplary embodiments. At a basic level, as and when the trace data is generated, the trace data may be transmitted to the available links (e.g., serial link, parallel link) to an external means for buffering/analysis” (para. 51).
For the reasons mentioned above, the rejections are maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-6, 11-13, 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Talvitie (US 2024/0044979) in further view of Mutschler et al. (US 2023/0089389) in further view of Aphale (US 2012/0079324).
In regard to claim 1, Talvitie teaches a processor-based device, comprising:
a trace interconnect bus (main system bus, fig. 2, 202, para. 82, 85);
a subsystem circuit comprising a debug transmit circuit (trace and debug logic, fig. 2, 203, para. 85); and
an input/output (I/O) endpoint circuit (external workstation can be connected to the external interface for receiving the trace data for analysis, para. 77);
the debug transmit circuit configured to:
receive debug data from the subsystem circuit (the trace and debug connections 214, 215 carry trace and debug data, para. 98, fig. 2);
generating a debug trace packet (generate trace, para. 4, 41); and
transmit the debug trace to the I/O endpoint circuit via the trace interconnect bus (outputting trace data through the external trace port, para. 46).
Talvitie does not explicitly teach receiving raw debug data, the raw debug data comprising data generated by the subsystem circuit in a raw state that does not conform with a trace format, generating and transmit the debug trace packet comprising raw debug data in lieu of formatted trace data.
Mutschler et al. teach of trace files can comprises composite log files, structured data files, raw data collections, or other various formats which are provided to users or user interfaces for further analysis and debug operations provided by analysis system 140 for host system 110, endpoint devices 120 and communication link 150 (para. 32).
It would have been obvious to modify the device of Talvitie by adding Mutschler et al. transaction analyzer. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would provide various formats in which the trace files can be provided (para. 32).
Talvitie and Mutschler et al. does not explicitly teach transmitting the debug trace during a period of trace interconnect bus inactivity.
Aphale teaches of the availability of the trace output may be determined based on a threshold percentage of intermediate trace buffer 806 and/or a threshold period of inactivity (para. 40).
It would have been obvious to modify the device of Talvitie and Mutschler et al. by adding Aphale firmware tracing data. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would provide multiple implementations of the trace buffer output (para. 40).
In regard to claim 2, Talvitie teaches the processor-based device of claim 1, wherein the trace interconnect bus comprises an Advanced Microcontroller Bus Architecture (AMBA) trace bus (ATB) interconnect bus (main system bus may be Advanced Microcontroller Bus Architecture (AMBA) bus, para. 32, any buses configured only to communicate debug or trace data such as any AMBA trace bus (ATB) or ARM CoreSight Debug Access Port Bus (DAP, para. 33) .
In regard to claim 4, Talvitie teaches the processor-based device of claim 1, wherein the debug transmit circuit is further configured to: receive a debug enable signal; and responsive to receiving the debug enable signal, selectively enable debug functionality of the debug transmit circuit (main system bus comprises multiplexers 216, 217, 218 and a bus arbiter which controls the multiplexers using control lines 227, para. 91-99, fig. 3).
In regard to claim 5, Talvitie teaches the processor-based device of claim 4, wherein: the debug transmit circuit comprises one of a plurality of debug transmit circuits of a corresponding plurality of subsystem circuits; and the debug transmit circuit is configured to selectively enable the debug functionality of the debug transmit circuit by being configured to selectively enable only the debug transmit circuit among the plurality of debug transmit circuits (main system bus comprises multiplexers 216, 217, 218 and a bus arbiter which controls the multiplexers using control lines 227, para. 91-99, fig. 3).
In regard to claim 6, Talvitie teaches the processor-based device of claim 4, wherein the debug transmit circuit is further configured to transmit a training pattern to the I/O endpoint circuit, responsive to receiving the debug enable signal (enabling the DWT and BPU of each processor to receive debug instructions from the trace and debug logic, para. 97).
In regard to claim 11, Talvitie teaches a processor-based device, comprising:
means for receiving debug data from a subsystem circuit of the processor-based device (the trace and debug connections 214, 215 carry trace and debug data, para. 98, fig. 2);
means for generating a debug trace packet comprising the debug data (generate trace, para. 4, 41); and
means for transmitting, via a trace interconnect bus of the processor-based device, the debug trace packet comprising the debug data to an I/O endpoint circuit of the processor-based device (outputting trace data through the external trace port, para. 46).
Talvitie does not explicitly teach receiving raw debug data, the raw debug data comprising data generated by the subsystem circuit in a raw state that does not conform with a trace format, generating and transmit the debug trace packet comprising raw debug data in lieu of formatted trace data.
Mutschler et al. teach of trace files can comprises composite log files, structured data files, raw data collections, or other various formats which are provided to users or user interfaces for further analysis and debug operations provided by analysis system 140 for host system 110, endpoint devices 120 and communication link 150 (para. 32).
Refer to claim 1 for motivational statement.
Talvitie and Mutschler et al. does not explicitly teach transmitting the debug trace packet during a period of trace interconnect bus inactivity.
Aphale teaches of the availability of the trace output may be determined based on a threshold percentage of intermediate trace buffer 806 and/or a threshold period of inactivity (para. 40).
Refer to claim 1 for motivational statement.
In regard to claim 12, Talvitie teaches a method for routing raw debug data using trace infrastructure, comprising:
receiving, by a debug transmit circuit of a subsystem circuit of a processor-based device, debug data from the subsystem circuit (the trace and debug connections 214, 215 carry trace and debug data, para. 98, fig. 2);
generating, by the debug transmit circuit, a debug trace packet comprising the debug data (generate trace, para. 4, 41); and
transmitting, by the debug transmit circuit via a trace interconnect bus of the processor-based device, the debug trace packet comprising the debug data to an input/output (I/O) endpoint circuit of the processor-based device (outputting trace data through the external trace port, para. 46).
Talvitie does not explicitly teach receiving raw debug data, the raw debug data comprising data generated by the subsystem circuit in a raw state that does not conform with a trace format, generating and transmit the debug trace packet comprising raw debug data in lieu of formatted trace data.
Mutschler et al. teach of trace files can comprises composite log files, structured data files, raw data collections, or other various formats which are provided to users or user interfaces for further analysis and debug operations provided by analysis system 140 for host system 110, endpoint devices 120 and communication link 150 (para. 32).
Refer to claim 1 for motivational statement.
Talvitie and Mutschler et al. does not explicitly teach transmitting the debug trace packet during a period of trace interconnect bus inactivity.
Aphale teaches of the availability of the trace output may be determined based on a threshold percentage of intermediate trace buffer 806 and/or a threshold period of inactivity (para. 40).
Refer to claim 1 for motivational statement.
In regard to claim 13, Talvitie teaches the method of claim 12, wherein the trace interconnect bus comprises an Advanced Microcontroller Bus Architecture (AMBA) trace bus (ATB) interconnect bus (main system bus may be Advanced Microcontroller Bus Architecture (AMBA) bus, para. 32, any buses configured only to communicate debug or trace data such as any AMBA trace bus (ATB) or ARM CoreSight Debug Access Port Bus (DAP, para. 33) .
In regard to claim 15, Talvitie teaches the method of claim 12, further comprising: receiving, by the debug transmit circuit, a debug enable signal; and responsive to receiving the debug enable signal, selectively enabling debug functionality of the debug transmit circuit (main system bus comprises multiplexers 216, 217, 218 and a bus arbiter which controls the multiplexers using control lines 227, para. 91-99, fig. 3).
In regard to claim 16, Talvitie teaches the method of claim 15, wherein: the debug transmit circuit comprises one of a plurality of debug transmit circuits of a corresponding plurality of subsystem circuits of the processor-based device; and selectively enabling debug functionality of the debug transmit circuit comprises selectively enabling only the debug transmit circuit among the plurality of debug transmit circuits (main system bus comprises multiplexers 216, 217, 218 and a bus arbiter which controls the multiplexers using control lines 227, para. 91-99, fig. 3).
In regard to claim 17, Talvitie teaches the method of claim 15, further comprising transmitting, by the debug transmit circuit, a training pattern to the I/O endpoint circuit, responsive to receiving the debug enable signal (enabling the DWT and BPU of each processor to receive debug instructions from the trace and debug logic, para. 97).
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Claims 3, 7-10, 14 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Talvitie (US 2024/0044979) in further view of Mutschler et al. (US 2023/0089389) in further view of Aphale (US 2012/0079324) in further view of Menon et al. (US 2017/0286254).
In regard to claim 3, Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach the processor-based device of claim 1, wherein the period of trace interconnect bus inactivity comprises a boot stage (early boot debug capture the traces, para. 48).
It would have been obvious to modify the device of Talvitie, Mutschler et al. and Aphale by adding Menon et al. debugger. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in debugging of boot data (para. 48)
In regard to claim 7, Talvitie teach the processor-based device of claim 1, wherein the I/O endpoint circuit comprises a debug receive circuit configured to: transmit the raw debug data to a trace sink (trace data output by the STM can be connected to the TPIU and/or other trace sinks, para. 85).
Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach receive the debug trace packet comprising the raw debug data from the debug transmit circuit; extract the raw debug data from the debug trace packet (crashDump and CrashLog are features to enable the collection and extraction of useful debug information, para. 31-32).
Refer to claim 3 for motivational statement.
In regard to claim 8, Talvitie teaches the processor-based device of claim 7, wherein the trace sink comprises one or more of a system memory, an embedded trace buffer, a Trace Port Interface Unit (TPIU), and one or more General Purpose I/O (GPIO) pins (trace data output can be connected to the TPIU and/or other trace sinks, para. 85).
In regard to claim 9, Talvitie teaches the processor-based device of claim 7, wherein: transmit the raw debug data to the trace sink based on the I/O configuration register (trace data output by the STM can be connected to the TPIU and/or other trace sinks, para. 85).
Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach the debug receive circuit is configured to extract the raw debug data and the debug receive circuit (crashDump and CrashLog are features to enable the collection and extraction of useful debug information, para. 31-32) comprises an I/O configuration register specifying one or more of a number of General Purpose I/O (GPIO) pins and an identification of one or more bits of the raw debug data (in open-chassis debug, the JTAG Test Access Port (TAP) interface as well as the Trace output provided by a trace aggregator are brought over general purpose input/output (GPIO) pins, para. 21).
Refer to claim 3 for motivational statement.
In regard to claim 10, Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach the processor-based device of claim 1, integrated into a device selected from the group consisting of: a set top box; an entertainment unit; navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter (target system comprises a smartphone, tablet, laptop IoT, SmartTV, car, server or any other portable device, para. 23).
Refer to claim 3 for motivational statement.
In regard to claim 14, Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach the method of claim 12, wherein the period of trace interconnect bus inactivity comprises a boot stage (early boot debug capture the traces, para. 48).
Refer to claim 3 for motivational statement.
In regard to claim 18, Talvitie teaches the method of claim 12, further comprising: transmitting, by the debug receive circuit, the raw debug data to a trace sink (trace data output by the STM can be connected to the TPIU and/or other trace sinks, para. 85).
Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach receiving, by a debug receive circuit of the I/O endpoint circuit, the debug trace packet comprising the raw debug data from the debug transmit circuit; extracting, by the debug receive circuit, the raw debug data from the debug trace packet (crashDump and CrashLog are features to enable the collection and extraction of useful debug information, para. 31-32).
Refer to claim 3 for motivational statement.
In regard to claim 19, Talvitie teaches the method of claim 18, wherein the trace sink comprises one or more of a system memory, an embedded trace buffer, a Trace Port Interface Unit (TPIU), and one or more General Purpose I/O (GPIO) pins (trace data output can be connected to the TPIU and/or other trace sinks, para. 85).
In regard to claim 20, Talvitie teaches the method of claim 18, wherein: transmitting the raw debug data to the trace sink comprises transmitting the raw debug data based on the I/O configuration register (trace data output by the STM can be connected to the TPIU and/or other trace sinks, para. 85).
Talvitie, Mutschler et al. and Aphale does not explicitly teach but Menon et al. teach extracting the raw debug data comprises extracting the raw debug data based on the I/O configuration register (crashDump and CrashLog are features to enable the collection and extraction of useful debug information, para. 31-32); and the debug receive circuit comprises an I/O configuration register specifying one or more of a number of General Purpose I/O (GPIO) pins and an identification of one or more bits of the raw debug data (in open-chassis debug, the JTAG Test Access Port (TAP) interface as well as the Trace output provided by a trace aggregator are brought over general-purpose input/output (GPIO) pins, para. 21).
Refer to claim 3 for motivational statement.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Centanni, JR. et al. (US 2003/0093714) dump of raw trace data from logic analyzer to stored computer file
Tang et al. (US 2003/0217130) raw network packet traffic stored in the network trace
Jain et al. (US 2007/0025239) monitor data may comprise raw packet transmission
Malomsoky et al. (US 2007/0070969) capturing raw traffic traces over standardized interfaces
Nolan et al. (US 2007/0113218) combine raw debug data into larger packets or bundles before transmission
Krishnan (US 7,249,286) trace file that contains raw data packets that have been captured by a trace capture utility
SOHM et al. (US 2006/0259827) navigating trace data by viewing just the raw trace data
Trobough et al. (US 2015/0127983) captured information may be placed in its raw form
Chen et al. (US 2019/0042745) receives the raw execution trace from execution trace collector
Froehlick et al. (US 2021/0250831) using AI and machine learning to process raw trace-port feed
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Futaki et al. (US 2013/0171944) managing trace sessions
Ghamami (US 2007/0076632) transmit trace signal during idle steps
Ashfield et al. (US 8,001,428) trace data slaves connected via bus (AMBA bus)
Ivan et al. (US 2016/0105200) trace bus (ATB), bus architecture (AMBA)
Assouad et al. (US 6,119,254) hardware tracing/logging
Naaseh-Shahry et al. (US 5,812,830) debug with raw mode trigger
Bharti et al. (US 2023/0214311) debug by saving raw and processed transaction data
Ciubotariu (US 2022/0335013) raw event trace logs
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Mutschler et al. (US 11,882,038) trace file can be raw data collection
Andrade et al. (US 2011/0040734) traces from raw data sources
Cruickshank et al. (US 7,802,149) debug trace program having raw streaming data
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Mysore et al. (US 2024/0378062) trace boot and GPIO
Delson (US 2024/0235982) trace data packet record a node identifier in a header (para. 116, fig. 6)
Zhong (US 2021/0374090) trace and debug port
Ansari et al. (US 10,896,119) trace buffer, boot, GPIO
Deiderich, III et al. (US 10,866,881) boot sequence and debug trace
Hoffmann (US 10,866,922) debug trace during boot cycle
Tufvesson et al. (US 10,180,890) debug interface
Mou et al. (US 9,952,963) bus debug trace
Grafton et al. (US 2016/0349326) debug trigger interface
Balkan et al. (US 8,402,314) debug registers
Beebe (US 2011/0060948) trace packets
Henson (US 10,372646) trace bus
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LOAN TRUONG whose telephone number is 408-918-7552. The examiner can normally be reached on 10AM-6PM PST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Ashish can be reached on 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Loan L.T. Truong/Primary Examiner, Art Unit 2114 Loan.truong@uspto.gov
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