DETAILED ACTION
This Office Action is in response to the application filed on 31 October 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 7-10, 13-15, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hasegawa et al. (US 2020/0321298 A1; hereinafter Hasegawa).
In regards to claim 1, Hasegawa teaches, e.g. in figs. 2, 4, and 5, an integrated circuit, comprising:
a semiconductor chip (200) [0023] comprising a first edge (408) oriented in a first planar direction (406) (fig. 4A: (408) is oriented in relations to (406));
a first bump row (Column B) comprising a plurality of first bumps (410a) aligned in the first planar direction along the first edge ((Column B) is aligned in relations to (406) along, i.e. parallel to, (408)); and
a second bump row (Column A) comprising a plurality of second bumps (410b) aligned in the first planar direction ((Column A) is aligned in relations to (406)), the second bump row being located farther from the first edge of the semiconductor chip than the first bump row (fig. 4A: (Column B) is closer to (408) compared to (Column A)),
wherein a first width (W4) of the first bumps in the first planar direction is narrower than a second width (W3) of the second bumps in the first planar direction [0038].
In regards to claim 4, Hasegawa teaches the limitations discussed above in addressing claim 1. Hasegawa further teaches, e.g. in figs. 2, 4, and 5, the limitations wherein each of the second bumps is positioned offset from a corresponding one of the first bumps in the first planar direction (fig. 4A: elements (410a) are offset in direction (406)).
In regards to claim 7, Hasegawa teaches the limitations discussed above in addressing claim 1. Hasegawa further teaches, e.g. in figs. 2, 4, and 5, the limitations wherein the integrated circuit is a display driver integrated circuit (IC) configured to drive a display panel ([0022], [0045-0046]: display update signals).
In regards to claim 8, Hasegawa teaches the limitations discussed above in addressing claim 7. Hasegawa further teaches, e.g. in figs. 2, 4, and 5, the limitations wherein the display driver IC is configured to:
generate data voltages with which pixels of the display panel are driven ([0022], [0045-0046]: display update signals); and
provide the data voltages to the display panel via the first bumps and the second bumps ([0022], [0045-0046]: display update signals).
In regards to claim 9, Hasegawa teaches the limitations discussed above in addressing claim 7. Hasegawa further teaches, e.g. in figs. 2, 4, and 5, the limitations wherein the semiconductor chip further comprises a second edge oriented in a second planar direction perpendicular to the first planar direction, and wherein the second edge is shorter than the first edge (fig. 5: e.g. (500) has longer edges and shorter edges).
In regards to claim 10, Hasegawa teaches, e.g. in figs. 2, 4, and 5, a display device, comprising:
a display panel ([0022], [0045-0046]: implied by display update signals); and
a display driver integrated circuit (IC) [0022] bonded on the display panel, the display driver IC comprising:
a semiconductor chip (200) [0023] comprising a first edge (408) oriented in a first planar direction (406) (fig. 4A: (408) is oriented in relations to (406));
a first bump row (Column B) comprising a plurality of first bumps (410a) aligned in the first planar direction along the first edge ((Column B) is aligned in relations to (406) along, i.e. parallel to, (408)); and
a second bump row (Column A) comprising a plurality of second bumps (410b) aligned in the first planar direction ((Column A) is aligned in relations to (406)), the second bump row being located farther from the first edge of the semiconductor chip than the first bump row (fig. 4A: (Column B) is closer to (408) compared to (Column A)),
wherein a first width (W4) of the first bumps in the first planar direction is narrower than a second width (W3) of the second bumps in the first planar direction [0038].
In regards to claim 13, Hasegawa teaches the limitations discussed above in addressing claim 10. Hasegawa further teaches, e.g. in figs. 2, 4, and 5, the limitations wherein each of the second bumps is positioned shifted from a corresponding one of the first bumps in the first planar direction (fig. 4A: elements (410a) are offset in direction (406)).
In regards to claim 14, Hasegawa teaches the limitations discussed above in addressing claim 10. Hasegawa further teaches, e.g. in figs. 2, 4, and 5, the limitations wherein the display panel comprises:
an active area that comprises pixels [0043];
a plurality of first bond pads bonded to the plurality of first bumps of the first bump row, respectively [0033-0034];
a plurality of second bond pads bonded to the plurality of second bumps of the second bump row, respectively [0033-0034];
a plurality of first routing traces that electrically couple the first bond pads to the active area [0043]; and
a plurality of second routing traces that electrically couple the first bond pads to the active area [0043].
In regards to claim 15, Hasegawa teaches the limitations discussed above in addressing claim 14. Hasegawa further teaches, e.g. in figs. 2, 4, and 5, the limitations wherein the plurality of first and second routing traces comprises routing trace portions that extend in a second planar direction perpendicular to the first planar direction to pass under the first edge of the display driver IC (fig. 5; [0022], [0045-0046]: display update signals).
In regards to claim 18, Hasegawa teaches, e.g. in figs. 2, 4, and 5, a method, comprising:
generating data voltages by a display driver IC [0022] comprising:
a semiconductor chip (200) [0023] comprising a first edge (408) oriented in a first planar direction (406) (fig. 4A: (408) is oriented in relations to (406));
a first bump row (Column B) comprising a plurality of first bumps (410a) aligned in the first planar direction along the first edge ((Column B) is aligned in relations to (406) along, i.e. parallel to, (408)); and
a second bump row (Column A) comprising a plurality of second bumps (410b) aligned in the first planar direction ((Column A) is aligned in relations to (406)), the second bump row being located farther from the first edge of the semiconductor chip than the first bump row (fig. 4A: (Column B) is closer to (408) compared to (Column A)),
wherein a first width (W4) of the first bumps in the first planar direction is narrower than a second width (W3) of the second bumps in the first planar direction [0038]; and
providing the data voltages to a display panel via the plurality of first bumps and the plurality of second bumps ([0022], [0045-0046]: display update signals).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, 5, 6, 11, 12, 16, 17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa as respectively applied to claims 1, 10, and 18 above, in view of Rossi et al. (US 2018/0157782 A1; hereinafter Rossi).
In regards to claim 2, Hasegawa teaches the limitations discussed above in addressing claim 1. Hasegawa appears to be silent as to, but does not preclude, the limitations of sets of bumps having multiple respective heights. Rossi teaches the limitations of multiple bumps varying in size, shape, and relative orientations (fig. 5). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Hasegawa with the aforementioned limitations taught by Rossi such that the bumps taught by Hasegawa were had various sizes, shapes, and relative orientations to optimize device density and align offset contacts (Rossi [0089]).
The combination of Hasegawa and Rossi appears to be silent as to the limitations wherein a first height of the first bumps in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bumps in the second planar direction; however Rossi teaches the limitation of having rows of bumps with different respective sizes (fig. 5; [0089]). Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitation wherein a first height of the first bumps in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bumps in the second planar direction, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (1950).
In regards to claim 3, the combination of Hasegawa and Rossi teaches the limitations discussed above in addressing claim 2. The combination of Hasegawa and Rossi appears to be silent as to the limitations wherein a first area of one of the plurality of first bumps is substantially equal to a second area of one of the plurality of second bumps; however Rossi teaches the limitations of multiple bumps varying in size, shape, and relative orientations (fig. 5) to optimize device density and align offset contacts (Rossi [0089]). Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966).
In regards to claim 5, Hasegawa teaches the limitations discussed above in addressing claim 1. Hasegawa appears to be silent as to, but does not preclude, the limitations of sets of bumps having multiple respective heights. Rossi teaches the limitations of multiple bumps varying in size, shape, and relative orientations (fig. 5). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Hasegawa with the aforementioned limitations taught by Rossi such that the bumps taught by Hasegawa were had various sizes, shapes, and relative orientations to optimize device density and align offset contacts (Rossi [0089]).
The combination of Hasegawa and Rossi appears to be silent as to the limitations further comprising a third bump row comprising a plurality of third bumps aligned in the first planar direction, wherein the third bump row is located farther from the first edge of the semiconductor chip than the second bump row, and wherein the second width of the second bumps in the first planar direction is narrower than a third width of the third bumps in the first planar direction; however Rossi teaches the limitations of multiple bumps varying in size, shape, and relative orientations (fig. 5) to optimize device density and align offset contacts (Rossi [0089]). Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitations further comprising a third bump row comprising a plurality of third bumps aligned in the first planar direction, wherein the third bump row is located farther from the first edge of the semiconductor chip than the second bump row, and wherein the second width of the second bumps in the first planar direction is narrower than a third width of the third bumps in the first planar direction, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (1950).
In regards to claim 6, the combination of Hasegawa and Rossi teaches the limitations discussed above in addressing claim 5. The combination of Hasegawa and Rossi appears to be silent as to the limitations wherein a first height of the first bumps in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bumps in the second planar direction, wherein the second height of the second bumps is greater than a third height of the third bumps in the second planar direction, and wherein one of the plurality of first bumps, one of the plurality of second bumps and one of the plurality of third bumps, respectively, have a substantially equal area; however Rossi teaches the limitations of multiple bumps varying in size, shape, and relative orientations (fig. 5) to optimize device density and align offset contacts (Rossi [0089]). Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitations wherein a first height of the first bumps in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bumps in the second planar direction, wherein the second height of the second bumps is greater than a third height of the third bumps in the second planar direction, and wherein one of the plurality of first bumps, one of the plurality of second bumps and one of the plurality of third bumps, respectively, have a substantially equal area, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (1950).
In regards to claim 11, Hasegawa teaches the limitations discussed above in addressing claim 10. Hasegawa appears to be silent as to, but does not preclude, the limitations of sets of bumps having multiple respective heights. Rossi teaches the limitations of multiple bumps varying in size, shape, and relative orientations (fig. 5). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Hasegawa with the aforementioned limitations taught by Rossi such that the bumps taught by Hasegawa were had various sizes, shapes, and relative orientations to optimize device density and align offset contacts (Rossi [0089]).
The combination of Hasegawa and Rossi appears to be silent as to the limitations wherein a first height of the first bumps in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bumps in the second planar direction; however Rossi teaches the limitation of having rows of bumps with different respective sizes (fig. 5; [0089]). Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitations wherein a first height of the first bumps in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bumps in the second planar direction, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (1950).
In regards to claim 12, the combination of Hasegawa and Rossi teaches the limitations discussed above in addressing claim 11. The combination of Hasegawa and Rossi appears to be silent as to the limitations wherein a first area of one of the plurality of first bumps is substantially equal to a second area of one of the plurality of second bumps; however Rossi teaches the limitations of multiple bumps varying in size, shape, and relative orientations (fig. 5) to optimize device density and align offset contacts (Rossi [0089]). Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966).
In regards to claim 16, Hasegawa teaches the limitations discussed above in addressing claim 10. Hasegawa appears to be silent as to, but does not preclude, the limitations of sets of bumps having multiple respective heights. Rossi teaches the limitations of multiple bumps varying in size, shape, and relative orientations (fig. 5). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Hasegawa with the aforementioned limitations taught by Rossi such that the bumps taught by Hasegawa were had various sizes, shapes, and relative orientations to optimize device density and align offset contacts (Rossi [0089]).
The combination of Hasegawa and Rossi appears to be silent as to the limitations further comprising a third bump row comprising a plurality of third bumps aligned in the first planar direction, wherein the third bump row is located farther from the first edge of the semiconductor chip than the second bump row, wherein each of the third bumps is positioned shifted from a corresponding one of the second bumps in the first planar direction, and wherein the second width of the second bumps in the first planar direction is narrower than a third width of the third bumps in the first planar direction; however Rossi teaches the limitation of having rows of bumps with different respective sizes (fig. 5; [0089]). Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitations further comprising a third bump row comprising a plurality of third bumps aligned in the first planar direction, wherein the third bump row is located farther from the first edge of the semiconductor chip than the second bump row, wherein each of the third bumps is positioned shifted from a corresponding one of the second bumps in the first planar direction, and wherein the second width of the second bumps in the first planar direction is narrower than a third width of the third bumps in the first planar direction, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (1950).
In regards to claim 17, the combination of Hasegawa and Rossi teaches the limitations discussed above in addressing claim 16. The combination of Hasegawa and Rossi appears to be silent as to the limitations wherein a first height of the first bumps in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bumps in the second planar direction, wherein the second height of the second bumps is greater than a third height of the third bumps in the second planar direction, and wherein one of the plurality of first bumps, one of the plurality of second bumps and one of the plurality of third bumps, respectively, have a substantially equal area; however Rossi teaches the limitations of multiple bumps varying in size, shape, and relative orientations (fig. 5) to optimize device density and align offset contacts (Rossi [0089]) Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitations wherein a first height of the first bumps in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bumps in the second planar direction, wherein the second height of the second bumps is greater than a third height of the third bumps in the second planar direction, and wherein one of the plurality of first bumps, one of the plurality of second bumps and one of the plurality of third bumps, respectively, have a substantially equal area, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (1950).
In regards to claim 19, the combination of Hasegawa and Rossi teaches the limitations discussed above in addressing claim 18. The combination of Hasegawa and Rossi appears to be silent as to the limitations wherein a first height of the first bumps in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bumps in the second planar direction; however Rossi teaches the limitations of multiple bumps varying in size, shape, and relative orientations (fig. 5) to optimize device density and align offset contacts (Rossi [0089]). Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitations wherein a first height of the first bumps in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bumps in the second planar direction, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (1950).
In regards to claim 20, Hasegawa teaches the limitations discussed above in addressing claim 19. The combination of Hasegawa and Rossi appears to be silent as to the limitations wherein a first area of one of the plurality of first bumps is substantially equal to a second area of one of the plurality of second bumps; however Rossi teaches the limitations of multiple bumps varying in size, shape, and relative orientations (fig. 5) to optimize device density and align offset contacts (Rossi [0089]). Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitations wherein a first area of one of the plurality of first bumps is substantially equal to a second area of one of the plurality of second bumps, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (1950).
Conclusion
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812