Office Action Predictor
Last updated: April 15, 2026
Application No. 18/498,773

SYSTEMS FOR AND METHODS FOR WIDEBAND ISOLATED OUTPUTS

Non-Final OA §102§103
Filed
Oct 31, 2023
Examiner
AKINYEMI, AJIBOLA A
Art Unit
2649
Tech Center
2600 — Communications
Assignee
Avago Technologies International Sales Pte. Limited
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
97%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
746 granted / 931 resolved
+18.1% vs TC avg
Strong +17% interview lift
Without
With
+16.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
25 currently pending
Career history
956
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
66.0%
+26.0% vs TC avg
§102
20.2%
-19.8% vs TC avg
§112
2.2%
-37.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 931 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6, 11-13, 16, 19, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Youssef (Pub. No.: US 2014/0240048A1). With respect to claim 1: Youssef discloses a device comprising a first output for a first radio frequency (RF) signal (fig. 6, RFout1); a second output for a second RF signal (fig. 6, RFout2); a first transistor having a first source/drain (fig. 6, item 536); and a second transistor having a first source/drain (fig. 6, item 546), wherein the first source/drain of the first transistor is coupled to the first source/drain of the second transistor (fig. 6, source/drain of 536 is coupled to source/drain of 546) and wherein the first and second transistors are disposed between the first output and the second output (fig. 6, item 536 and 546 are dispose in-between RFout 1 and RFout 2). With respect to claim 2: Youssef discloses the device of claim 1, comprising an input coupled to: a gate of a third transistor, a first source/drain of the third transistor coupled with the first source/drain of the first transistor and the first source/drain of the second transistor (fig. 6 with RFin 1 coupled to transistor 534 gate and source/drain of third transistor coupled to source/drain of first transistor). With respect to claim 3: Youssef discloses the device of claim 2, wherein: the second source/drain of the first transistor is coupled with a first terminal of a first inductor, a second terminal of the first inductor coupled with a first voltage node; and the second source/drain of the second transistor is coupled with a first terminal of a second inductor, the second terminal of the second inductor coupled with the first voltage node (fig. 5B with transistor 536 coupled to inductor 584 and second terminal of inductor coupled to VDD and same for the other transistor 538). With respect to claim 4: Youssef discloses the device of claim 1, wherein: the first source/drain of the first transistor and the first source/drain of the second transistor is coupled with a first source/drain of a third transistor; a first gate of the first transistor is coupled with a first voltage node; a second gate of the second transistor is coupled with a second voltage node; and the second source/drain of the third transistor is coupled with a third voltage node (fig. 6 with transistor 536, 546 having their gate coupled to the voltage and third transistor 534 source/drain to voltage as well). With respect to claim 5: Youssef discloses the device of claim 4, wherein: a voltage of the first voltage node differs from a voltage of the second voltage node and a voltage of the third voltage node (Ven1, Ven3 etc are different). With respect to claims 6: Youssef discloses the device of claim 4, wherein: a voltage of the second voltage node does not differ from a voltage of the third voltage node (parag. 0049 and 0056 discloses voltage off and ON switch). With respect to claims 11, 16: Youssef discloses the device of claim 1, wherein: the first RF signal and the second RF signal are derived from a same antenna (fig.3, with antenna 310 for devices 330 and 360). With respect to claim 12: Youssef discloses the device of claim 1, wherein: the first output and the second output are outputs of a power divider (fig. 5B, with VDDs). With respect to claim 13: Youssef discloses a system, comprising: an amplifier (parag. 0011) comprising: a first output for a first radio frequency (RF) signal (fig. 6, RFout1); and a second output for a second RF signal (fig. 6, RFout2); and a cascade circuit comprising: a first source/drain of a first transistor coupled with the first output (fig. 6, item 536 coupled to RFout1); and a first source/drain of a second transistor coupled with the second output (fig. 6, item 546 coupled to RFout2); and a first source/drain of a third transistor coupled with a second source/drain of the first transistor and a second source/drain of the second transistor (fig. 6, item 534 with source/drain coupled to 536 and 546). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Youssef (Pub. No.: US 2014/0240048A1) and further in view of Zhenbiao (Pub. No.: US 2005/0248402 A1). With respect to claim 19: Youssef discloses a method comprising: receiving, at a gate of a first transistor, a first signal comprising: first content centered about a first frequency (fig. 6, item 536 is a transistor having with Ven1 having a first frequency); and second content centered about a second frequency; receiving, at a first source/drain of a second transistor (fig. 6, item 546 having source/drain for second frequency), the first content; receiving, at a first source/drain of a third transistor (fig. 6, item 534 having source/drain for first frequency); Youssef does not explicitly disclose, wherein the first content and the second content comprise radio frequency content; and the first frequency exceeds the second frequency by 1.5 GHz. Zhenbiao discloses the first content and the second content comprise radio frequency content and the first frequency exceeds the second frequency by 1.5 GHz (parag. 0029 discloses first and second frequency band with 2.4GHZ and 5.15GHZ). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of Zhenbiao into the teaching of Youssef in order to provide gain select, for operation in either the first or second frequency bands. With respect to claim 20: Youssef discloses the method of claim 19, comprising: receiving, at a second gate of the second transistor and a third gate of the third transistor, a non-zero DC voltage (parag. 0049 and 0056 discloses high and low voltages which are non zero). Allowable Subject Matter Claims 7-10, 14, 15, 17, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AJIBOLA A AKINYEMI whose telephone number is (571)270-1846. The examiner can normally be reached Monday-Friday 8:00am-5:00pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YUWEN PAN can be reached at (571)-272-7855. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AJIBOLA A AKINYEMI/Primary Examiner, Art Unit 2649
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Prosecution Timeline

Oct 31, 2023
Application Filed
Nov 08, 2025
Non-Final Rejection — §102, §103
Mar 24, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
97%
With Interview (+16.7%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 931 resolved cases by this examiner. Grant probability derived from career allow rate.

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