DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-4, and 6-24 are pending.
Claims 1-4, 6-8, 11-13, 15-18, 20, and 23 have been amended.
This action is Non-Final.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 20-23 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,443,216 in view of Thorson et al. (hereinafter as Thorson) USPAT 10,824,188.
As per claim 20, USPAT 12,443,216 teaches a digital circuit for clock waveform synthesis for each individual instruction or operational cycle of a processor [claim 1], comprising:
an instruction control unit (ICU) that supplies a sequence of instructions to control a generation of clock signals [claim 1];
a clock pulse synthesis (CPS) controller, connected to the ICU, that decodes the instructions supplied by the ICU, and generates clock waveform parameter signals respective to a particular instruction of the sequence of instructions [claim 1];
a shift register clocked by a high frequency clock that operates at a frequency higher than that of a nominal processor clock frequency, wherein the high frequency clock is driven by a phase-locked loop circuit; and wherein the shift register is comprised of one or more toggle flip-flop registers that are initialized by using the clock waveform parameter signals supplied by the CPS controller [claim 1]; and
a bypass multiplexer that supplies either a clock signal that is output from the shift registers, or from the phase locked loop that provides the nominal processor clock signal, wherein an output of the multiplexer is connected to a clock driver on the processor chip [claim 1].
USPAT 12,443,216 does not explicitly teach a plurality of processor chips; wherein the plurality of processor chips are configured as a spanning tree such that a first CPS circuit of a root processor chip of the plurality of processor chips provided at the root of the spanning tree generates a plurality of beacon pulses to one or more downstream processor chips provided in the spanning tree through a plurality of communication links.
Thorson teaches processor chips having system circuitry components. Thorson is thus similar to USPAT 12,443,216 because they pertain to processor chip components. Thorson further teaches a plurality of processor chips [FIG. 1 and FIG. 8: (chip 1 is coupled to chip 2 through chip N and are a plurality of processor chips)], wherein the plurality of processor chips are configured as a spanning tree such that a first CPS circuit of a root processor chip of the plurality of processor chips provided at the root of the spanning tree [FIG. 8: (chip 1 is viewed as the root processor chip and chips 2 through chip N is viewed as downstream chips of a tree configuration; it is considered a spanning tree because the processors are all connected together without any cycles (e.g. alternative paths from chips such as chip 2 to other chips such as chip N)] generates a plurality of beacon pulses to one or more downstream processor chips provided in the spanning tree through a plurality of communication links [col. 4 lines 57-61: (hardware counter on master system/Chip 1 sends timing reference that is embedded with data (beacon pulses) to downstream slave processors/Chip 2-N)].
The combination of USPAT 12,443,216 with Thorson leads to the clock circuitry of USPAT 12,443,216 being inside the system circuitry components 120 and 121 of chip 1 and chip 2-N in Thorson. In other words, USPAT 12,443,216 teaches the clock circuitry components in system circuitry 120,121 of each processor chip in Thorson. The combination also implements Thorson’s synchronization mechanism in USPAT 12,443,216 and Thorson in which the plurality of chips are then synchronized through a timing reference provided from the master processor chip to slave processor chips.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Thorson’s teachings of a plurality of processor chips coupled to each other via communication links as the processor chips that implement USPAT 12,443,216’s instruction-based clock circuitry. In other words, Thorson teaches the processor chips in which USPAT 12,443,216’s teachings are applied. It would also have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Thorson’s teachings of synchronizing the plurality of processor chips through a timing reference/beacon from master to slave chips in USPAT 12,443,216 and Thorson. One of ordinary skill in the art would have been motivated to apply USPAT 12,443,216’s teachings in processor chips such as in Thorson because it allows for different systems to work together [col. 1 lines 11-13] for overall processing improvement, while individually saving power by altering clock signals based on the instruction it is executing. One of ordinary skill in the art would have been motivated to use Thorson’s synchronization mechanism of timing reference between master and slave chips in USPAT 12,443,216 and Thorson because it allows the processor chips to be synchronized so that they can work together and thus improve performance.
All features of instant dependent claims 21-23 are covered by claims 1 and 4 of USPAT 12,443,216 and are therefore rejected accordingly.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4, and 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim PGPUB 2002/0026596, and further in view of Eaton et al. (hereinafter as Eaton) PGPUB 2008/0284474, Thorson et al. (hereinafter as Thorson) USPAT 10,824,188, and Dean et al. (hereinafter as Dean) USPAT 6,477,654.
As per claim 1, Kim teaches each processor chip comprising generating a high frequency clock signal which is input to a clock pulse synthesis (CPS) circuit [FIG. 2 and 0014: (MUX 160 (CPS circuit) receives a high frequency clock signal CLOCK1)], which generates a chip clock signal [FIG. 2 and 0018: (MUX 160 generates P_CLOCK)], the chip clock signal specifying a variance in clock period [FIG. 4: (the P_CLOCK signal (chip clock signal) shows/specifies a variance in clock period; the period of the P_CLOCK signal changes, and thus a variance in clock period is specified)] respective to a particular instruction of a sequence of instructions
[0016-0019: (P_CLOCK signal is selected from either CLOCK1 or CLOCK2 based on/respective to a power-up instruction or to a power-down instruction (particular instruction) of a sequence/series of power-up and power-down instructions)] to save power executing the sequence of instructions from during a first period of instruction execution or reduce latency during a second period of instruction execution [0016-0017: (instruction decoder evaluates the instruction to determine if it is a power up or down instruction in a period of instruction execution, which is then used to produce a clock signal for the processor)].
Kim does not teach teaches a plurality of processor chips coupled together via communication links; a reference clock to drive a Phase-Locked Loop (PLL) for generating the high frequency clock signal; a sequence of instructions from a compiled program; wherein the plurality of processor chips are configured as a spanning tree such that a first CPS circuit of a root processor chip of the plurality of processor chips provided at the root of the spanning tree generates a plurality of beacon pulses to one or more downstream processor chips provided in the spanning tree through a plurality of communication links. Kim utilizes a clock oscillator rather than receiving a reference clock.
Eaton teaches a clock generator system that provides clock signal to a processor based on power management information. Eaton is thus similar to Kim because they teach generating clock signals to processor. Eaton further teaches a reference clock to drive a Phase-Locked Loop (PLL) for generating a high frequency clock signal which is input to a CPS [FIG. 3: (reference clock is provided to PLL 302 and 306, which is then provided to other circuit 312 (CPS))].
The combination of Kim with Eaton teaches using a reference clock that is provided to a PLL which then outputs CLOCK1 to the MUX 160 (CPS). In other words, it allows substituting the oscillator in the clock generator of Kim with a reference clock provided to a PLL instead.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Eaton’s teachings of a reference clock provided to a PLL to provide an output clock CLOCK1 in Kim instead of using the clock oscillator. One of ordinary skill in the art would be motivated to use a reference clock with a PLL instead of a clock oscillator because PLL uses less crystals and provides more flexibility and lower cost than a crystal oscillator.
The combination of Kim with Eaton do not explicitly teach a plurality of processor chips coupled together via communication links; a sequence of instructions from a compiled program; wherein the plurality of processor chips are configured as a spanning tree such that a first CPS circuit of a root processor chip of the plurality of processor chips provided at the root of the spanning tree generates a plurality of beacon pulses to one or more downstream processor chips provided in the spanning tree through a plurality of communication links.
Thorson teaches processor chips having system circuitry components. Thorson is thus similar to Kim and Eaton because they pertain to processor chip components. Thorson further teaches a plurality of processor chips coupled together via communication links [FIG. 1 and FIG. 8: (chip 1 is coupled to chip 2 through chip N over communication links between C2C interfaces)], wherein the plurality of processor chips are configured as a spanning tree such that a first CPS circuit of a root processor chip of the plurality of processor chips provided at the root of the spanning tree [FIG. 8: (chip 1 is viewed as the root processor chip and chips 2 through chip N is viewed as downstream chips of a tree configuration; it is considered a spanning tree because the processors are all connected together without any cycles (e.g. alternative paths from chips such as chip 2 to other chips such as chip N)] generates a plurality of beacon pulses to one or more downstream processor chips provided in the spanning tree through a plurality of communication links [col. 4 lines 57-61: (hardware counter on master system/Chip 1 sends timing reference that is embedded with data (beacon pulses) to downstream slave processors/Chip 2-N)].
The combination of Kim and Eaton with Thorson leads to the clock circuitry of Kim and Eaton being inside the system circuitry components 120 and 121 of chip 1 and chip 2 in Thorson. In other words, Kim and Eaton teaches the clock circuitry components in system circuitry 120,121 of each processor chip in Thorson. The combination also implements Thorson’s synchronization mechanism in Kim, Eaton, and Thorson in which the plurality of chips are then synchronized through a timing reference provided from the master processor chip to slave processor chips.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Thorson’s teachings of a plurality of processor chips coupled to each other via communication links as the processor chips that implement Kim and Eaton’s instruction-based clock circuitry. In other words, Thorson teaches the processor chips in which Kim and Eaton’s teachings are applied. It would also have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Thorson’s teachings of synchronizing the plurality of processor chips through a timing reference/beacon from master to slave chips in Kim, Eaton, and Thorson. One of ordinary skill in the art would have been motivated to apply Kim and Eaton’s teachings in processor chips such as in Thorson because it allows for different systems to work together [col. 1 lines 11-13] for overall processing improvement, while individually saving power by altering clock signals based on the instruction it is executing. One of ordinary skill in the art would have been motivated to use Thorson’s synchronization mechanism of timing reference between master and slave chips in Kim, Eaton, and Thorson because it allows the processor chips to be synchronized so that they can work together and thus improve performance.
The combination of Kim, Eaton, and Thorson do not explicitly teach a sequence of instructions from a compiled program. Although Thorson shows a compiler providing programs to the different processor chips, Thorson does not specify what kind of instructions the compiler is providing, and whether they are equivalent to the power-up or power-down instructions in Kim.
Dean teaches a computing device that decodes instructions. Dean is thus similar to Kim, Eaton, and Thorson. Dean further teaches a sequence of instructions from a compiled program [claim 19]. Dean teaches a compiler inserting power-up and power-down instructions in the sequence of instructions of an application to be executed.
The combination of Kim, Eaton, and Thorson with Dean leads to the compiler adding the power-up and power-down instructions to an application, and the instruction decoder in Kim decoding these power-up or power-down instructions to change the clock frequency and clock period.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Dean’s teachings of the compiler providing the power-up and power-down instructions in Kim, Eaton, and Thorson. One of ordinary skill in the art would have been motivated to have the compiler provide the power-up and power-down instructions in Kim because it allows for more efficient power usage since the compiler is aware of what functions or features will be executed or will be used next when it compiles the program application.
As per claim 2, Kim, Eaton, Thorson, and Dean teach the plurality of processor chips of claim 1, wherein the high frequency clock signal is a faster multiple of the chip clock signal [Eaton 0028].
As per claim 3, Kim, Eaton, Thorson, and Dean teach the plurality of processor chips of claim 1, wherein a compiler compiles the sequence of instructions, and wherein at least one first processor chip has a first CPS set to run at a first clock rate and at least one second processor chip has a second CPS to run at a second clock rate [Dean claim 19: (compiler compiles sequence of instructions for an application and inserts power-up or power-down instructions) with Kim, Eaton, and Thorson: (system circuitry in each processor chip has the clock circuitry that can vary based on decoded power-up or power-down instruction; first processor chip would run at a first clock rate while second processor chip would run at a second clock rate; first clock rate and second clock rate may or may not be the same)].
As per claim 4, Kim, Eaton, Thorson, and Dean teach the plurality of processor chips of claim 3, wherein the compiler accounts for differences between the first clock rate and the second clock rate and schedules data transfers between the at least one first chip and the at least one second chip using common wall-clock time [Thorson col. 4 lines 38-43 and col. 3 lines 26-49].
As per claim 6, Kim, Eaton, Thorson, and Dean teach the plurality of processor chips of claim 1, wherein the plurality of beacon pulses are sent at a constant rate [Thorson col. 2 lines 58-60 and lines 33-34: (chips are synchronized periodically, and thus the timing reference is provided at a constant rate)]
As per claim 7, Kim, Eaton, Thorson, and Dean teach the plurality of processor chips of claim 6, wherein each downstream processor chip of the one or more downstream processor chips adjusts a respective chip clock that is generated by the downstream processor chip up and down accordingly every time a beacon is received to continuously compensate for any difference between the root processor chip and the downstream processor chip [Thorson col. 2 line 63 – col. 3 line 3 and col. 4 lines 57-67].
Claim(s) 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim PGPUB 2002/0026596, and further in view of Eaton et al. (hereinafter as Eaton) PGPUB 2008/0284474, Thorson et al. (hereinafter as Thorson) USPAT 10,824,188, Dean et al. (hereinafter as Dean) USPAT 6,477,654, and Om et al. (hereinafter as Om) PGPUB 2005/0212571.
Claim 8 is similar in scope to claim 20 as addressed below and is thus rejected under the same rationale.
Claim 9 is similar in scope to claim 21 as addressed below and is thus rejected under the same rationale.
Claim 10 is similar in scope to claim 22 as addressed below and is thus rejected under the same rationale.
Claim 11 is similar in scope to claim 23 as addressed below and is thus rejected under the same rationale.
As per claim 12, Kim, Eaton, Thorson, and Dean teach the digital circuit of claim 11, wherein the processor chip is linked to the plurality of processor chips [Thorson FIG. 8: (processor chip 1 are linked/connected to the plurality of processor chips 2-N, and each chip have other circuits 815); and Eaton FIG. 3: (processor have PLL circuit)].
Claim(s) 13-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim PGPUB 2002/0026596, and further in view of Thorson et al. (hereinafter as Thorson) USPAT 10,824,188.
As per claim 13, Kim teaches a processor [0012: processor] for processing a functional instruction sequence [0012 and 0016: (externally inputted instruction) and FIG.3A and 0020: (there is a sequence of power-down/power-up instructions that are provided, and are thus a functional instruction sequence)] and a plurality of clock period synthesis (CPS) instructions determined respective to instructions of the functional instruction sequence [0016-0017 and 0019: (clock selection unit 140 and instruction decoder 150 outputs signals such as signal 4 and signal 2 (CPS instructions) to the first clock controller 130 to change clock operations responsive to the respective decoded instruction in the sequence of instructions (e.g. response to a power-down instruction in the sequence of power-down and power-up instructions))].
Kim does not teach a plurality of processor chips, wherein the plurality of processor chips are configured as a spanning tree such that a first CPS circuit of a root processor chip of the plurality of processor chips provided at the root of the spanning tree generates a plurality of beacon pulses to one or more downstream processor chips provided in the spanning tree through a plurality of communication links.
Thorson teaches processor chips having system circuitry components. Thorson is thus similar to Kim because they pertain to processor chip components. Thorson further teaches a plurality of processor chips [FIG. 1 and FIG. 8: (chip 1 is coupled to chip 2 through chip N and are a plurality of processor chips)], wherein the plurality of processor chips are configured as a spanning tree such that a first CPS circuit of a root processor chip of the plurality of processor chips provided at the root of the spanning tree [FIG. 8: (chip 1 is viewed as the root processor chip and chips 2 through chip N is viewed as downstream chips of a tree configuration; it is considered a spanning tree because the processors are all connected together without any cycles (e.g. alternative paths from chips such as chip 2 to other chips such as chip N)] generates a plurality of beacon pulses to one or more downstream processor chips provided in the spanning tree through a plurality of communication links [col. 4 lines 57-61: (hardware counter on master system/Chip 1 sends timing reference that is embedded with data (beacon pulses) to downstream slave processors/Chip 2-N)].
The combination of Kim with Thorson leads to the clock circuitry of Kim being inside the system circuitry components 120 and 121 of chip 1 and chip 2-N in Thorson. In other words, Kim teaches the clock circuitry components in system circuitry 120,121 of each processor chip in Thorson. The combination also implements Thorson’s synchronization mechanism in Kim and Thorson in which the plurality of chips are then synchronized through a timing reference provided from the master processor chip to slave processor chips.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Thorson’s teachings of a plurality of processor chips coupled to each other via communication links as the processor chips that implement Kim’s instruction-based clock circuitry. In other words, Thorson teaches the processor chips in which Kim’s teachings are applied. It would also have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Thorson’s teachings of synchronizing the plurality of processor chips through a timing reference/beacon from master to slave chips in Kim and Thorson. One of ordinary skill in the art would have been motivated to apply Kim’s teachings in processor chips such as in Thorson because it allows for different systems to work together [col. 1 lines 11-13] for overall processing improvement, while individually saving power by altering clock signals based on the instruction it is executing. One of ordinary skill in the art would have been motivated to use Thorson’s synchronization mechanism of timing reference between master and slave chips in Kim and Thorson because it allows the processor chips to be synchronized so that they can work together and thus improve performance.
As per claim 14, Kim and Thorson teach the processor of claim 13, further comprising, in the absence of any CPS instructions, generating a default value for a chip clock period at boot time [Kim FIG. 2, 0016-0018: (instruction is decoded and analyzed; if it is not a particular instruction, there is no instruction signal provided to first clock controller 130 and the default second clock is used for the processor)].
As per claim 15, Kim and Thorson teach the processor of claim 14, further comprising a configuration register for overwriting a hardware default value for the chip clock period on each processor chip [Kim 0017 and 0023].
As per claim 16, Kim and Thorson teach the processor of claim 15, wherein a compiler schedules the functional instruction sequence without consideration of CPS instructions [Thorson col. 2 lines 13-17].
As per claim 17, Kim and Thorson teach the processor of claim 16, wherein the compiler keeps a tally of the real-time duration of the instructions executed on each processor chip and the real-time values are deterministically aligned at data transfer times [Thorson col. 2 line 21 – col. 4 line 6].
As per claim 18, Kim and Thorson teach the processor of claim 17, wherein the compiler optimizes the clock period durations on each processor chip of the plurality of processor chips [Thorson col. 6 line 48 – col. 7 line 6].
As per claim 19, Kim and Thorson teach the processor of claim 16, wherein the compiler schedules the plurality of CPS instructions [Thorson col. 2 lines 13-20].
Claim(s) 20-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim PGPUB 2002/0026596, and further in view of Eaton et al. (hereinafter as Eaton) PGPUB 2008/0284474, Om et al. (hereinafter as Om) PGPUB 2005/0212571, and Thorson et al. (hereinafter as Thorson) USPAT 10,824,188.
As per claim 20, Kim teaches a digital circuit for clock waveform synthesis for each individual instruction or operational cycle of a processor [abstract, 0007, and 0012: (circuitry for providing clock to a processor)], comprising:
an instruction control unit (ICU) that supplies a sequence instructions to control a generation of clock signals [FIG. 2 and 0017: (instruction decoder 150 (ICU) provides signals to control generation of clock signals based on the decoded instructions; FIG. 3A and 0020: (there is a sequence of power-down/power-up instructions that are provided, and are thus a sequence of instructions)];
a clock pulse synthesis (CPS) controller, connected to the ICU, that decodes the instructions supplied by the ICU, and generates clock waveform parameter signals respective to a particular instruction of the sequence of instructions [FIG. 2 and 0019: (first clock controller 130 is connected to instruction decoder and based on/respective to the particular instructions, clock controller generates control signals (clock waveform parameter signals) to first clock generator 110 (e.g. clock control signals are provided in response to a power-down instruction in the sequence of power-down and power-up instructions))];and
a bypass multiplexer that supplies either a clock signal that is output [0015 and FIG. 2: (MUX is supplied with high frequency clock from unit 110)], or from the phase locked loop that provides the nominal processor clock signal [0015 and FIG. 2: (MUX is also supplied with clock signal from second clock generator 120 that has a lower frequency)], wherein an output of the multiplexer is connected to a clock driver on the processor chip [FIG. 2, 0023-0026, and 0018: (output of MUX is a processor clock signal P_Clock which is provided to a clock component (such as a clock driver) in the processor)].
Kim does not teach a plurality of processor chips; shift register clocked by a high frequency clock that operates at a frequency higher than that of a nominal processor clock frequency, wherein the high frequency clock is driven by a phase-locked loop circuit; and wherein the shift register is comprised of one or more toggle flip-flop registers that are initialized by using the clock waveform parameter signals supplied by the CPS controller; the bypass multiplexer that supplies a clock signal that is output from the shift registers; and wherein the plurality of processor chips are configured as a spanning tree such that a first CPS circuit of a root processor chip of the plurality of processor chips provided at the root of the spanning tree generates a plurality of beacon pulses to one or more downstream processor chips provided in the spanning tree through a plurality of communication links. Kim teaches the clock controller providing control signals to first clock generator 110, but there is no mention about a shift register.
Eaton teaches a clock generator system that provides clock signal to a processor based on power management information. Eaton is thus similar to Kim because they teach generating clock signals to processor. Eaton further teaches a shift register clocked by a high frequency clock that operates at a frequency higher than that of a nominal processor clock frequency [0028: (a conventional shift register may function as a clock generator; conventional shift register has required a reference clock having a frequency that is four times (high frequency) a particular clock signal frequency (nominal processor clock frequency))], wherein the high frequency clock is driven by a phase-locked loop circuit [FIG. 1-3: (in conventional art, a PLL is used for circuitry components)]; and a clock signal that is output from the shift registers [0028: (shift register function as a clock generator to generator to generate arbitrary clock signal waveforms)].
The combination of Kim with Eaton teaches substituting Kim’s first clock generator 110 with a shift register that generates arbitrary clock signal waveforms, where the shift register is clocked at a high frequency. Thus the combination of Kim with Eaton would teach the limitation of a bypass multiplexer that supplies either a clock signal that is output from the shift registers [Kim’s MUX would become connected to output of shift registers], or for the phase locked loop that provides the nominal processor clock signal [Kim’s MUX also connected to the slower/nominal second clock generator].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Eaton’s teachings of a conventional shift register to generate arbitrary clock signal waveforms in Kim, instead of using Kim’s first clock generator circuitry. One of ordinary skill in the art would have been motivated to use Eaton’s teachings of a conventional shift register to generate arbitrary clock signals in Kim because it is a simpler conventional design that can generate clock custom or arbitrary clock signals using lower cost elements.
Kim and Eaton do not explicitly teach a plurality of processor chips; wherein the shift register is comprised of one or more toggle flip-flop registers that are initialized by using the clock waveform parameter signals supplied by the CPS controller; wherein the plurality of processor chips are configured as a spanning tree such that a first CPS circuit of a root processor chip of the plurality of processor chips provided at the root of the spanning tree generates a plurality of beacon pulses to one or more downstream processor chips provided in the spanning tree through a plurality of communication links. Kim and Eaton do not appear to mention a toggle flip flop connected to the shift register.
Om teaches a shift register [0016: (FF-Delay is a resettable shift register)] that is connected to a MUX that causes a clock signal to be provided to a processor. Om is thus similar to Kim and Eaton. Om further teach wherein the shift register is comprised of one or more toggle flip-flop registers that are initialized by using the clock waveform parameter signals [0019: (external clock (clock waveform parameter signals) may be applied to toggle type flip flop, whose output is then fed to the rest of the shift register)]. Om teaches a toggle type flip flop being connected to shift register, and where the toggle type flip flop receives an external clock signal.
The combination of Kim and Eaton with Om leads to the control signals from the first clock controller in Kim being external clock signals to a toggle flip flop that is connected to a shift register for the generation of the first clock.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Om’s teachings of using a toggle flip flop that is connected to the shift register in Kim and Eaton. One of ordinary skill in the art would have been motivated to use a toggle flip flop with the shift register in Kim and Eaton because it allows a glitch to corrupt only the first flop but reduce the effect of this anomaly significantly at the output of the shift register [Om 0019], thus reducing effects of corruption thus improving accuracy and reliability.
Kim, Eaton, and Om do not appear to teach a plurality of processor chips; wherein the plurality of processor chips are configured as a spanning tree such that a first CPS circuit of a root processor chip of the plurality of processor chips provided at the root of the spanning tree generates a plurality of beacon pulses to one or more downstream processor chips provided in the spanning tree through a plurality of communication links
Thorson teaches processor chips having system circuitry components. Thorson is thus similar to Kim, Eaton, and Om because they pertain to processor chip components. Thorson further teaches a plurality of processor chips [FIG. 1 and FIG. 8: (chip 1 is coupled to chip 2 through chip N and are a plurality of processor chips)], wherein the plurality of processor chips are configured as a spanning tree such that a first CPS circuit of a root processor chip of the plurality of processor chips provided at the root of the spanning tree [FIG. 8: (chip 1 is viewed as the root processor chip and chips 2 through chip N is viewed as downstream chips of a tree configuration; it is considered a spanning tree because the processors are all connected together without any cycles (e.g. alternative paths from chips such as chip 2 to other chips such as chip N)] generates a plurality of beacon pulses to one or more downstream processor chips provided in the spanning tree through a plurality of communication links [col. 4 lines 57-61: (hardware counter on master system/Chip 1 sends timing reference that is embedded with data (beacon pulses) to downstream slave processors/Chip 2-N)].
The combination of Kim, Eaton, and Om with Thorson leads to the clock circuitry of Kim, Eaton, and Om being inside the system circuitry components 120 and 121 of chip 1 and chip 2-N in Thorson. In other words, Kim, Eaton, and Om teaches the clock circuitry components in system circuitry 120,121 of each processor chip in Thorson. The combination also implements Thorson’s synchronization mechanism in Kim, Eaton, Om and Thorson in which the plurality of chips are then synchronized through a timing reference provided from the master processor chip to slave processor chips. Together, the combination leads to each processor chip containing circuitry including a bypass multiplexer, where an output of the multiplexer goes to the clock driver on the respective processor chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Thorson’s teachings of a plurality of processor chips coupled to each other via communication links as the processor chips that implement Kim, Eaton, and Om’s instruction-based clock circuitry. In other words, Thorson teaches the processor chips in which Kim’s teachings are applied. It would also have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Thorson’s teachings of synchronizing the plurality of processor chips through a timing reference/beacon from master to slave chips in Kim, Eaton, Om, and Thorson. One of ordinary skill in the art would have been motivated to apply Kim, Eaton, Om’s teachings in processor chips such as in Thorson because it allows for different systems to work together [col. 1 lines 11-13] for overall processing improvement, while individually saving power by altering clock signals based on the instruction it is executing. One of ordinary skill in the art would have been motivated to use Thorson’s synchronization mechanism of timing reference between master and slave chips in Kim, Eaton, Om, and Thorson because it allows the processor chips to be synchronized so that they can work together and thus improve performance.
As per claim 21, Kim, Eaton, Om, and Thorson teach the digital circuit of claim 20, wherein the shift register is used to determine the clock high time and the clock low time [Eaton 0028: (shift register generate arbitrary clock signal waveforms and thus determines/decides the clock high time and the clock low time)].
As per claim 22, Kim, Eaton, Om, and Thorson teach the digital circuit of claim 21, wherein the shift register generates half-cycle resolution of the high frequency clock period [Eaton 0028].
As per claim 23, Kim, Eaton, Om, and Thorson teach the digital circuit of claim 21, wherein the phase-locked loop circuit is located on the processor chip [Eaton FIG. 3: (PLL part of processor 300)].
As per claim 24, Kim, Eaton, Om, and Thorson teach the digital circuit of claim 21, wherein the CPS controller reuses a same shift register element for clock signal edges that start or end on the rising or falling edge of the high frequency clock [Om FIG. 1 and 0019: (a single flip flop may be used as the shift register; thus the shift register would be reused for clock signal edges that start or end on the rising or falling edge of the high frequency clock)].
Response to Arguments
Applicant's arguments filed 7/31/2026 have been fully considered but they are not persuasive. Applicant argues that claim 1, 13, and 20 have been amended to incorporate the subject matter of indicated allowable claim 5. Examiner respectfully disagrees.
Claims 1, 13, and 20 have been amended to include only a portion of the limitations of previous claim 5 (without claims 2-4). Thus for claim 1, it is a different scope that what was previously examined, and for claims 13 and 20, it is a different scope altogether.
In addition, upon further review of the amended limitation and the specification, it appears there is no specific definition provided for the term spanning tree. The general definition for the term spanning tree appears to be a loop-free subgraph that connects all vertices using the fewest possible links. In other words, it is a tree structure without loops or cycles. With that definition in mind, it appears the previously applied prior art Thorson actually does teach such a spanning tree structure in FIG. 8 in which chip 1 is the master/root processor chip and chips 2-N are just downstream nodes connected to chip 1. Furthermore, Thorson teaches that Chip 1 provides a timing reference/beacon to the downstream chips through a plurality of links for synchronization. Therefore, Thorson actually does teach the amended limitation.
For the reasons described above, the previously applied prior art is still applicable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Garg et al. (PGPUB 2022/0100247) teaches a plurality of dies arranged in a tree configuration.
Kurian et al. (PGPUB 2018/0249432) teaches a spanning tree structure, and beacons for synchronization with peers.
Douskey et al. (PGPUB 2010/0231281) teaches integrated circuits connected into a tree structure with a root node connected to leaf nodes.
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/DANNY CHAN/Primary Examiner, Art Unit 2175
