DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-24 are pending.
Claims 1, 8, 13-15, 20-21, and 24 have been amended.
This action is Final.
Specification
The disclosure is objected to because of the following informalities:
Applicant’s specification does not provide any description about FIG. 5C and the purpose of such figure. There is no discussion regarding FIG. 5C, and the only paragraphs that mentions FIG. 5C in paragraphs [0020] and [0061] of Applicant’s specification merely refers to a group of drawings of FIG. 5A, FIG. 5B, and FIG. 5C. There is no discussion on what FIG. 5C is meant to convey. The only difference between FIG. 5B and FIG. 5C are the two arrows and the two question marks at the bottom of the figure, but it is uncertain what these arrows and question marks mean.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 20-23 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8, and 17 of USPAT 12,443,216. Although the claims at issue are not identical, they are not patentably distinct from each other because they are simple changes of a statutory category. Claim 1 of USPAT 12,443,216 include all the limitations of the instant claim 20 and therefore anticipates the instant claim.
Comparisons of selected claims are shown in the following table.
Instant Application (18/498,810)
USPAT 12,443,216
20. A digital circuit for clock waveform synthesis for each individual instruction or operational cycle of a processor, comprising: an instruction control unit (ICU) that supplies a sequence of instructions to control a generation of clock signals; a clock pulse synthesis (CPS) controller, connected to the ICU, that decodes the instructions supplied by the ICU, and generates clock waveform parameter signals respective to a particular instruction of the sequence of instructions; a shift register clocked by a high frequency clock that operates at a frequency higher than that of a nominal processor clock frequency, wherein the high frequency clock is driven by a phase-locked loop circuit; and wherein the shift register is comprised of one or more toggle flip-flop registers that are initialized by using the clock waveform parameter signals supplied by the CPS controller; and a bypass multiplexer that supplies either a clock signal that is output from the shift registers, or from the phase locked loop that provides the nominal processor clock signal, wherein an output of the multiplexer is connected to a clock driver on the processor chip.
1. A digital circuit for clock waveform synthesis for each individual instruction or operational cycle of a processor, comprising: an instruction control unit (ICU) that supplies instructions to control the generation of clock signals; a clock pulse synthesis (CPS) controller connected to the ICU, the CPS controller decodes the instructions supplied from the ICU, and generates clock waveform parameter signals; wherein a CPS circuit comprises the CPS controller and a waveform generator that produces waveforms based on the clock waveform parameter signals: a duration logic block that uses the clock waveform parameter signals supplied by the CPS controller and preloads values for the waveform generator: a shift register that is clocked by a high frequency clock that operates at a frequency that is higher than a nominal processor clock frequency, wherein the high frequency clock is generated by a phase-locked loop circuit on the processor; wherein the shift register is comprised of one or more toggle flip-flop registers that are initialized by using the duration logic block and the clock waveform parameter signals supplied by the CPS controller; and a bypass multiplexer that is connected, via an output of the bypass multiplexer, to the processor, the bypass multiplexer is supplied with either a clock signal that is output from the shift register, or from a phase locked loop that provides the high frequency clock.
21. The digital circuit of claim 20, wherein the shift register is used to determine the clock high time and the clock low time
1. …first clock signal that is output from the shift register
22. The digital circuit of claim 21, wherein the shift register generates half-cycle resolution of the high frequency clock period.
4. The digital circuit of claim 1, wherein the processor further comprises a main clock, and wherein a first waveform resolution of the main clock is half of a second waveform resolution of the high frequency clock.
23. The digital circuit of claim 21, wherein the high frequency clock is driven by a phase-locked loop circuit on the processor chip.
1. …wherein the high frequency clock is generated by a phase-locked loop circuit on the processor;
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim1 PGPUB 2002/0026596, and further in view of Eaton et al. (hereinafter as Eaton)1 PGPUB 2008/0284474, Thorson et al. (hereinafter as Thorson)2 USPAT 10,824,188, and Dean et al. (hereinafter as Dean) USPAT 6,477,654.
As per claim 1, Kim teaches each processor chip comprising generating a high frequency clock signal which is input to a clock pulse synthesis (CPS) circuit [FIG. 2 and 0014: (MUX 160 (CPS circuit) receives a high frequency clock signal CLOCK1)], which generates a chip clock signal [FIG. 2 and 0018: (MUX 160 generates P_CLOCK)], the chip clock signal specifying a variance in clock period [FIG. 4: (the P_CLOCK signal (chip clock signal) shows/specifies a variance in clock period; the period of the P_CLOCK signal changes, and thus a variance in clock period is specified)] respective to a particular instruction of a sequence of instructions
[0016-0019: (P_CLOCK signal is selected from either CLOCK1 or CLOCK2 based on/respective to a power-up instruction or to a power-down instruction (particular instruction) of a sequence/series of power-up and power-down instructions)] to save power executing the sequence of instructions from during a first period of instruction execution or reduce latency during a second period of instruction execution [0016-0017: (instruction decoder evaluates the instruction to determine if it is a power up or down instruction in a period of instruction execution, which is then used to produce a clock signal for the processor)].
Kim does not teach teaches a plurality of processor chips coupled together via communication links; a reference clock to drive a Phase-Locked Loop (PLL) for generating the high frequency clock signal; a sequence of instructions from a compiled program. Kim utilizes a clock oscillator rather than receiving a reference clock.
Eaton teaches a clock generator system that provides clock signal to a processor based on power management information. Eaton is thus similar to Kim because they teach generating clock signals to processor. Eaton further teaches a reference clock to drive a Phase-Locked Loop (PLL) for generating a high frequency clock signal which is input to a CPS [FIG. 3: (reference clock is provided to PLL 302 and 306, which is then provided to other circuit 312 (CPS))].
The combination of Kim with Eaton teaches using a reference clock that is provided to a PLL which then outputs CLOCK1 to the MUX 160 (CPS). In other words, it allows substituting the oscillator in the clock generator of Kim with a reference clock provided to a PLL instead.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Eaton’s teachings of a reference clock provided to a PLL to provide an output clock CLOCK1 in Kim instead of using the clock oscillator. One of ordinary skill in the art would be motivated to use a reference clock with a PLL instead of a clock oscillator because PLL uses less crystals and provides more flexibility and lower cost than a crystal oscillator.
The combination of Kim with Eaton do not explicitly teach a plurality of processor chips coupled together via communication links; a sequence of instructions from a compiled program.
Thorson teaches processor chips having system circuitry components. Thorson is thus similar to Kim and Eaton because they pertain to processor chip components. Thorson further teaches a plurality of processor chips coupled together via communication links [FIG. 1 and FIG. 8: (chip 1 is coupled to chip 2 through chip N over communication links between C2C interfaces)].
The combination of Kim and Eaton with Thorson leads to the clock circuitry of Kim and Eaton being inside the system circuitry components 120 and 121 of chip 1 and chip 2 in Thorson. In other words, Kim and Eaton teaches the clock circuitry components in system circuitry 120,121 of each processor chip in Thorson.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Thorson’s teachings of processor chips coupled to each other via communication links as the processor chips to implement Kim and Eaton’s instruction-based clock circuitry on. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use implement Kim and Eaton’s teachings in processor chips such as in Thorson because it allows for different systems to work together [claim 1 lines 11-13] for overall processing improvement, while individually saving power by altering clock signals based on the instruction it is executing.
The combination of Kim, Eaton, and Thorson do not explicitly teach a sequence of instructions from a compiled program. Although Thorson shows a compiler providing programs to the different processor chips, Thorson does not specify what kind of instructions the compiler is providing, and whether they are equivalent to the power-up or power-down instructions in Kim.
Dean teaches a computing device that decodes instructions. Dean is thus similar to Kim, Eaton, and Thorson. Dean further teaches a sequence of instructions from a compiled program [claim 19]. Dean teaches a compiler inserting power-up and power-down instructions in the sequence of instructions of an application to be executed.
The combination of Kim, Eaton, and Thorson with Dean leads to the compiler adding the power-up and power-down instructions to an application, and the instruction decoder in Kim decoding these power-up or power-down instructions to change the clock frequency and clock period.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Dean’s teachings of the compiler providing the power-up and power-down instructions in Kim, Eaton, and Thorson. One of ordinary skill in the art would have been motivated to have the compiler provide the power-up and power-down instructions in Kim because it allows for more efficient power usage since the compiler is aware of what functions or features will be executed or will be used next when it compiles the program application.
As per claim 2, Kim, Eaton, Thorson, and Dean teach the plurality of processor chips of claim 1, wherein the high frequency clock signal is a faster multiple of a chip clock signal [Eaton 0028].
As per claim 3, Kim, Eaton, Thorson, and Dean teach the plurality of processor chips of claim 1, wherein a compiler compiles the sequence of instructions, and wherein at least one processor chip (first chips) has a CPS set to run at a first clock rate and at least one other processor chip (second chips) has a CPS to run at second clock rate [Dean claim 19: (compiler compiles sequence of instructions for an application and inserts power-up or power-down instructions) with Kim and Eaton: (system circuitry in each processor chip has the clock circuitry that can vary based on decoded power-up or power-down instruction; first processor chip would run at a first clock rate while second processor chip would run at a second clock rate; first clock rate and second clock rate may or may not be the same)].
As per claim 4, Kim, Eaton, and Thorson teach the plurality of processor chips of claim 3, wherein the compiler accounts for the pre-planned frequency differences and schedules data transfers between the first chips and the second chips using common wall-clock time [Thorson col. 4 lines 38-43 and col. 3 lines 26-49].
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim PGPUB 2002/0026596, and further in view of Thorson et al. (hereinafter as Thorson) USPAT 10,824,188.
As per claim 13, Kim teaches a processor [0012: processor] for processing a functional instruction sequence [0012 and 0016: (externally inputted instruction) and FIG.3A and 0020: (there is a sequence of power-down/power-up instructions that are provided, and are thus a functional instruction sequence)] and a plurality of clock period synthesis (CPS) instructions determined respective to instructions of the functional instruction sequence [0016-0017 and 0019: (clock selection unit 140 and instruction decoder 150 outputs signals such as signal 4 and signal 2 (CPS instructions) to the first clock controller 130 to change clock operations responsive to the respective decoded instruction in the sequence of instructions (e.g. response to a power-down instruction in the sequence of power-down and power-up instructions))].
Kim does not teach a plurality of processing chips.
Thorson teaches processor chips having system circuitry components. Thorson is thus similar to Kim because they pertain to processor chip components. Thorson further teaches a plurality of processor chips [FIG. 1 and FIG. 8: (chip 1 is coupled to chip 2 through chip N)].
The combination of Kim and Eaton with Thorson leads to the clock circuitry of Kim being inside the system circuitry components 120 and 121 of chip 1 and chip 2 in Thorson. In other words, Kim teaches the clock circuitry components in system circuitry 120,121 of each processor chip in Thorson.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Thorson’s teachings of processor chips coupled to each other via communication links as the processor chips to implement Kim’s instruction-based clock circuitry on. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use implement Kim’s teachings in processor chips such as in Thorson because it allows for different systems to work together [claim 1 lines 11-13] for overall processing improvement, while individually saving power by altering clock signals based on the instruction it is executing.
As per claim 14, Kim and Thorson teach the processor of claim 13, further comprising, in the absence of any CPS instructions, generating a default value for a chip clock period at boot time [Kim FIG. 2, 0016-0018: (instruction is decoded and analyzed; if it is not a particular instruction, there is no instruction signal provided to first clock controller 130 and the default second clock is used for the processor)].
As per claim 15, Kim and Thorson teach the processor of claim 14, further comprising a configuration register for overwriting a hardware default value for the chip clock period on each processing chip [Kim 0017 and 0023].
As per claim 16, Kim and Thorson teach the processor of claim 15, wherein a compiler schedules the functional instructions sequence without consideration of CPS instructions [Thorson col. 2 lines 13-17].
As per claim 17, Kim and Thorson teach the processor of claim 16, wherein the compiler keeps a tally of the real-time duration of the instructions executed on each processing chip in a multi-chip processor and the real-time values are deterministically aligned at data transfer times [Thorson col. 2 line 21 – col. 4 line 6].
As per claim 18, Kim and Thorson teach the processor of claim 17, wherein the compiler optimizes the clock period durations on each individual processor chip [Thorson col. 6 line 48 – col. 7 line 6].
As per claim 19, Kim and Thorson teach the processor of claim 16, wherein the compiler schedules the plurality of CPS instructions [Thorson col. 2 lines 13-20].
Claim(s) 20-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim PGPUB 2002/0026596, and further in view of Eaton et al. (hereinafter as Eaton) PGPUB 2008/0284474 and Om et al. (hereinafter as Om)1 PGPUB 2005/0212571.
As per claim 20, Kim teaches a digital circuit for clock waveform synthesis for each individual instruction or operational cycle of a processor [abstract, 0007, and 0012: (circuitry for providing clock to a processor)], comprising:
an instruction control unit (ICU) that supplies a sequence instructions to control a generation of clock signals [FIG. 2 and 0017: (instruction decoder 150 (ICU) provides signals to control generation of clock signals based on the decoded instructions; FIG. 3A and 0020: (there is a sequence of power-down/power-up instructions that are provided, and are thus a sequence of instructions)];
a clock pulse synthesis (CPS) controller, connected to the ICU, that decodes the instructions supplied by the ICU, and generates clock waveform parameter signals respective to a particular instruction of the sequence of instructions [FIG. 2 and 0019: (first clock controller 130 is connected to instruction decoder and based on/respective to the particular instructions, clock controller generates control signals (clock waveform parameter signals) to first clock generator 110 (e.g. clock control signals are provided in response to a power-down instruction in the sequence of power-down and power-up instructions))];and
a bypass multiplexer that supplies either a clock signal that is output [0015 and FIG. 2: (MUX is supplied with high frequency clock from unit 110)], or from the phase locked loop that provides the nominal processor clock signal [0015 and FIG. 2: (MUX is also supplied with clock signal from second clock generator 120 that has a lower frequency)], wherein an output of the multiplexer is connected to a clock driver on the processor chip [FIG. 2, 0023-0026, and 0018: (output of MUX is a processor clock signal P_Clock which is provided to a clock component (such as a clock driver) in the processor)].
Kim does not teach a shift register clocked by a high frequency clock that operates at a frequency higher than that of a nominal processor clock frequency, wherein the high frequency clock is driven by a phase-locked loop circuit; and wherein the shift register is comprised of one or more toggle flip-flop registers that are initialized by using the clock waveform parameter signals supplied by the CPS controller; and the bypass multiplexer that supplies a clock signal that is output from the shift registers. Kim teaches the clock controller providing control signals to first clock generator 110, but there is no mention about a shift register.
Eaton teaches a clock generator system that provides clock signal to a processor based on power management information. Eaton is thus similar to Kim because they teach generating clock signals to processor. Eaton further teaches a shift register clocked by a high frequency clock that operates at a frequency higher than that of a nominal processor clock frequency [0028: (a conventional shift register may function as a clock generator; conventional shift register has required a reference clock having a frequency that is four times (high frequency) a particular clock signal frequency (nominal processor clock frequency))], wherein the high frequency clock is driven by a phase-locked loop circuit [FIG. 1-3: (in conventional art, a PLL is used for circuitry components)]; and a clock signal that is output from the shift registers [0028: (shift register function as a clock generator to generator to generate arbitrary clock signal waveforms)].
The combination of Kim with Eaton teaches substituting Kim’s first clock generator 110 with a shift register that generates arbitrary clock signal waveforms, where the shift register is clocked at a high frequency. Thus the combination of Kim with Eaton would teach the limitation of a bypass multiplexer that supplies either a clock signal that is output from the shift registers [Kim’s MUX would become connected to output of shift registers], or for the phase locked loop that provides the nominal processor clock signal [Kim’s MUX also connected to the slower/nominal second clock generator].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Eaton’s teachings of a conventional shift register to generate arbitrary clock signal waveforms in Kim, instead of using Kim’s first clock generator circuitry. One of ordinary skill in the art would have been motivated to use Eaton’s teachings of a conventional shift register to generate arbitrary clock signals in Kim because it is a simpler conventional design that can generate clock custom or arbitrary clock signals using lower cost elements.
Kim and Eaton do not explicitly teach wherein the shift register is comprised of one or more toggle flip-flop registers that are initialized by using the clock waveform parameter signals supplied by the CPS controller. Kim and Eaton do not appear to mention a toggle flip flop connected to the shift register.
Om teaches a shift register [0016: (FF-Delay is a resettable shift register)] that is connected to a MUX that causes a clock signal to be provided to a processor. Om is thus similar to Kim and Eaton. Om further teach wherein the shift register is comprised of one or more toggle flip-flop registers that are initialized by using the clock waveform parameter signals [0019: (external clock (clock waveform parameter signals) may be applied to toggle type flip flop, whose output is then fed to the rest of the shift register)]. Om teaches a toggle type flip flop being connected to shift register, and where the toggle type flip flop receives an external clock signal.
The combination of Kim and Eaton with Om leads to the control signals from the first clock controller in Kim being external clock signals to a toggle flip flop that is connected to a shift register for the generation of the first clock.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Om’s teachings of using a toggle flip flop that is connected to the shift register in Kim and Eaton. One of ordinary skill in the art would have been motivated to use a toggle flip flop with the shift register in Kim and Eaton because it allows a glitch to corrupt only the first flop but reduce the effect of this anomaly significantly at the output of the shift register [Om 0019], thus reducing effects of corruption thus improving accuracy and reliability.
As per claim 21, Kim, Eaton, and Om teach the digital circuit of claim 20, wherein the shift register is used to determine the clock high time and the clock low time [Eaton 0028: (shift register generate arbitrary clock signal waveforms and thus determines/decides the clock high time and the clock low time)].
As per claim 22, Kim, Eaton, and Om teach the digital circuit of claim 21, wherein the shift register generates half-cycle resolution of the high frequency clock period [Eaton 0028].
As per claim 23, Kim, Eaton, and Om teach the digital circuit of claim 21, wherein the high frequency clock is driven by a phase-locked loop circuit on the processor chip [Eaton FIG. 3: (PLL part of processor 300)].
As per claim 24, Kim, Eaton, and Om teach the digital circuit of claim 21, wherein the CPS controller reuses a same shift register element for clock signal edges that start or end on the rising or falling edge of the high frequency clock [Om FIG. 1 and 0019: (a single flip flop may be used as the shift register; thus the shift register would be reused for clock signal edges that start or end on the rising or falling edge of the high frequency clock)].
Allowable Subject Matter
Claims 5-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (i.e. claims 2-4).
Response to Arguments
Applicant's arguments filed 2/11/2026 have been fully considered but they are not persuasive. Applicant appears to provide similar arguments on page 11-12 for claims 1, 13, and 20 that Kim merely discloses decoding an externally inputted instruction, and that these externally inputted power-up/power-down instructions are not determined respective to instructions of the functional instruction sequence as claimed. Examiner respectfully disagree.
Regarding Applicant’s argument for claims 1, 13, and 20 that Kim merely discloses decoding an externally inputted instruction, and that these externally inputted power-up/power-down instructions are not determined respective to instructions of the functional instruction sequence as claimed, Examiner first notes that the claim does not exclude externally inputted instructions. Examiner then notes that Applicant’s specification does not provide a specific definition for the term “functional instruction sequence”, and thus Examiner interprets the term to mean a plurality of instructions over a period of time (i.e. a series of instructions provided over a period of time) under the broadest reasonable interpretation of the claim in light of the specification. Examiner then notes that Kim does teach a series or sequence of instructions because Kim’s instruction decoder 150 [FIG. 2] may receive power up or power down instructions at different times [FIG. 3A – FIG. 3B], and thus the instruction decoder 150 does indeed receive a sequence of instructions. Examiner further notes that upon the instruction decoder 150 receiving an instruction from the sequence of instructions, it causes signals (such as signal 2 and signal 4) to be selectively provided to the first clock controller 130 to change operations of the first clock [FIG. 2 and 0016-0017]. These signals provided to the first clock controller 130 based on/respective to the received instructions of the instruction sequence are thus equivalent to the claimed plurality of clock period synthesis (CPS) instructions determined respective to instructions of the functional instruction sequence. In summary, Kim teaches generating signals/instructions to change clock operations based on/respective to instructions in a series of instructions, which is similar to Applicant’s claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Muthukumar et al. (PGPUB 2007/0106914) teaches a compiler inserting power up and power down instructions [0005 and 0019].
Terechko et al. (PGPUB 2006/0179329) teaches compiler inserting power down instructions [0008].
Seth et al. (PGPUB 2003/0014742) teaches energy aware compilers including power-down instructions [0029].
Bartley (USPAT 6,219,796) teaches allowing a compiler to insert power-down instructions.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY CHAN whose telephone number is (571)270-5134. The examiner can normally be reached Monday - Friday 10-7 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 5712703779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANNY CHAN/Primary Examiner, Art Unit 2175
1 Cited in IDS on 11/7/2024.
2 Cited in IDS on 8/8/2024.
Prosecution Insights