DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 and 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the previous data save indicator" in the last lines of the claim. However, there is insufficient antecedent basis for this limitation in the claim. For the purpose of compact prosecution, the examiner will interpret the claim limitation as “a data save indicator”.
Claim 16 recites the limitation "the previous permitted save indicator" in the last lines of the claim. However, there is insufficient antecedent basis for this limitation in the claim. For the purpose of compact prosecution, the examiner will interpret the claim limitation as “a permitted save indicator”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 12-14, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Underwood et al. Pub. No. US 2020/0050478 A1 (hereafter Underwood) in view of Ashkar et al. Pub. No. US 10,558,489 B2 (hereafter Ashkar).
With regard to claim 1, Underwood teaches a method of operating a data processing system that comprises: a host processor; a main memory resource associated with the host processor (Another embodiment of the technology described herein comprises a method of processing data using a data processing system comprising: a host processor that executes applications using an operating system in at least paragraphs [0021] - [0022] and that the host processor 2 communicates with the MCU 25 of the GPU 5 via a shared interface memory (which may be main memory, or another suitable memory cache, depending on the configuration) in at least paragraph [0151]);
a processing resource operable to perform data processing operations for applications executing on the host processor (A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by the accelerator in at least the abstract);
a working memory resource associated with the processing resource (The technology described herein also extends to a computer software carrier comprising such software which when used to operate a graphics processor, renderer or microprocessor system comprising a data processor causes in conjunction with the data processor the processor, renderer or system to carry out the steps of the methods of the technology described herein. Such a computer software carrier could be a physical storage medium such as a ROM chip, CD ROM, RAM, flash memory, or disk, or could be a signal such as an electronic signal over wires, an optical signal or a radio signal such as to a satellite or the like in at least paragraph [0136]);
providing, by the host processor, in response to a request for processing to be performed by the processing resource from an application executing on the host processor, a command stream to the processing resource to cause the processing resource to perform a processing task comprising one or more processing operations (wherein the host processor comprises command stream generating circuitry operable to prepare, in response to a request for processing to be performed by the accelerator from an application being executed on the host processor, one or more command stream(s) for causing the accelerator to perform processing tasks for the application, each command stream including a sequence of commands for implementation by the accelerator; and wherein the command stream generating circuitry is operable to include within a command for a command stream an indication that a subsequent sequence of one or more command(s) within that command stream is to be implemented by the accelerator in a protected mode of operation so that when that command is executed the accelerator is operable to initiate or request a switch into the protected mode of operation for processing the subsequent sequence of one or more command(s) in at least paragraph [0020]);
the command stream comprising: a sequence of commands for execution by the processing resource to cause the processing resource to perform the processing operations for the processing task (Thus, the technology described herein generally relates to data processing systems comprising an accelerator that is operable to execute a sequence of commands in a command stream provided by a host processor in order to perform processing work for applications executing on the operating system of the host processor. For instance, when a request for processing work by the accelerator is made by an application on the host processor, the host processor can then prepare one or more command stream(s) including a plurality of commands (instructions) specifying the processing work to be performed by the accelerator. The commands (instructions) are then implemented on the accelerator, e.g. using a suitable command stream execution unit under the control of a supervising controller, with the commands being executed in turn in order to perform the desired (requested) processing work in at least paragraph [0030]);
executing, by the processing resource, the commands in the command stream to perform the processing operations for the processing task (Once all the required command sequences for the command stream have been built, then the command stream is in an embodiment made visible to the corresponding command stream interface (e.g. by appropriately “flushing” the work), so that the command stream interface can then start to execute the commands in the command stream (e.g. either immediately or after any still-executing previous command streams have been completed) in at least paragraph [0066]);
in response to the processing resource receiving a request to suspend processing of the processing task being performed (In another embodiment, the status reports may be limited to OK/FAIL (i.e. where there is no INCOMPLETE status). In this case, in the event that the host processor issues a suspend or interrupt request for a command stream while the accelerator is operating in the protected mode, the status of the protected mode execution will be indicated as FAIL, and the controller (firmware) may be capable of tracking that a suspend request was issued during protected mode execution and to then set the protected mode required flags again at the appropriate time in at least paragraph [0119]).
While Underwood teaches context switching, saving and suspending command streams, they do not teach the one or more save indicators in a command stream. They also do not teach storing in the main memory data indicated by the one or more data save indicators in response to the processing resource receiving a request to suspend processing.
However, in analogous art, Ashkar teaches one or more data save indicators that indicate data that is to be saved (When operations are suspended on GPU 200, status information associated with the in-flight work-items is saved to memory by save/restore machine 212. Data associated with the in-flight work items is streamed from different units of GPU 200 to save/restore machine 212, and restore information identifying where the data came from is embedded alongside the data. For example, each piece of data sent to save/restore machine 212 is tagged to indicate which unit generated the piece of data. In one embodiment, data is streamed over a common bus to save/restore machine 212, and save/restore machine 212 uses the embedded tags to determine which unit(s) generated each piece of data. Save/restore machine 212 saves the status information and embedded tags to memory, and this stored data will be used later if a restore operation is requested in at least paragraph (21), Examiner notes that the embedded information/tags in the streamed data taught by Ashkar can be the one or more data save indicators);
storing in the main memory resource data indicated by one of the one or more data save indicators in the command stream (When operations are suspended on GPU 200, status information associated with the in-flight work-items is saved to memory by save/restore machine 212. Data associated with the in-flight work items is streamed from different units of GPU 200 to save/restore machine 212, and restore information identifying where the data came from is embedded alongside the data. For example, each piece of data sent to save/restore machine 212 is tagged to indicate which unit generated the piece of data. In one embodiment, data is streamed over a common bus to save/restore machine 212, and save/restore machine 212 uses the embedded tags to determine which unit(s) generated each piece of data. Save/restore machine 212 saves the status information and embedded tags to memory, and this stored data will be used later if a restore operation is requested in at least paragraph (21)).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the data save indicators and them being stored in the memory resource taught by Ashkar with the method of operating a data processing system taught by Underwood. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of having “improved techniques for implementing suspend and restore operations on a processor” especially because “determining how to suspend operations on the GPU to enable a seamless restoration can be challenging” (See Ashkar paragraph (3)).
With regard to claim 7, Underwood teaches a data processing system comprising: a host processor; a main memory resource associated with the host processor (An embodiment of the technology described herein comprises a data processing system, the data processing system comprising: a host processor that executes applications using an operating system; an accelerator operable to process data for applications executing on the host processor; and memory for storing data for use by the accelerator, the memory having both protected memory and non-protected memory in at least paragraphs [0015] – [0018]);
a processing resource operable to perform data processing operations for applications executing on the host processor (A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by the accelerator in at least the abstract);
a working memory resource associated with the processing resource (The technology described herein also extends to a computer software carrier comprising such software which when used to operate a graphics processor, renderer or microprocessor system comprising a data processor causes in conjunction with the data processor the processor, renderer or system to carry out the steps of the methods of the technology described herein. Such a computer software carrier could be a physical storage medium such as a ROM chip, CD ROM, RAM, flash memory, or disk, or could be a signal such as an electronic signal over wires, an optical signal or a radio signal such as to a satellite or the like in at least paragraph [0136]);
the host processor comprising: a circuit configured to provide, in response to a request for processing to be performed by the processing resource from an application executing on the host processor, a command stream to the processing resource to cause the processing resource to perform a processing task comprising one or more processing operations (wherein the host processor comprises command stream generating circuitry operable to prepare, in response to a request for processing to be performed by the accelerator from an application being executed on the host processor, one or more command stream(s) for causing the accelerator to perform processing tasks for the application, each command stream including a sequence of commands for implementation by the accelerator; and wherein the command stream generating circuitry is operable to include within a command for a command stream an indication that a subsequent sequence of one or more command(s) within that command stream is to be implemented by the accelerator in a protected mode of operation so that when that command is executed the accelerator is operable to initiate or request a switch into the protected mode of operation for processing the subsequent sequence of one or more command(s) in at least paragraph [0020]);
the command stream comprising: a sequence of commands for execution by the processing resource to cause the processing resource to perform the processing operations for the processing task (Thus, the technology described herein generally relates to data processing systems comprising an accelerator that is operable to execute a sequence of commands in a command stream provided by a host processor in order to perform processing work for applications executing on the operating system of the host processor. For instance, when a request for processing work by the accelerator is made by an application on the host processor, the host processor can then prepare one or more command stream(s) including a plurality of commands (instructions) specifying the processing work to be performed by the accelerator. The commands (instructions) are then implemented on the accelerator, e.g. using a suitable command stream execution unit under the control of a supervising controller, with the commands being executed in turn in order to perform the desired (requested) processing work in at least paragraph [0030]);
the processing resource comprising: a circuit configured to execute commands in a command stream received by the processing resource to perform processing operations for a processing task (wherein the host processor comprises command stream generating circuitry operable to prepare, in response to a request for processing to be performed by the accelerator from an application being executed on the host processor, one or more command stream(s) for causing the accelerator to perform processing tasks for the application, each command stream including a sequence of commands for implementation by the accelerator in at least paragraph [0020], and once all the required command sequences for the command stream have been built, then the command stream is in an embodiment made visible to the corresponding command stream interface (e.g. by appropriately “flushing” the work), so that the command stream interface can then start to execute the commands in the command stream (e.g. either immediately or after any still-executing previous command streams have been completed) in at least paragraph [0066]);
a circuit configured to: in response to the processing resource receiving a request to suspend processing of a processing task being performed (wherein the host processor comprises command stream generating circuitry in at least paragraph [0020] and, in another embodiment, the status reports may be limited to OK/FAIL (i.e. where there is no INCOMPLETE status). In this case, in the event that the host processor issues a suspend or interrupt request for a command stream while the accelerator is operating in the protected mode, the status of the protected mode execution will be indicated as FAIL, and the controller (firmware) may be capable of tracking that a suspend request was issued during protected mode execution and to then set the protected mode required flags again at the appropriate time. in at least paragraph [0119]).
While Underwood teaches context switching, saving and suspending command streams, they do not teach the one or more save indicators in a command stream. They also do not teach storing in the main memory data indicated by the one or more data save indicators in response to the processing resource receiving a request to suspend processing.
However, in analogous art, Ashkar teaches one or more data save indicators that indicate data that is to be saved (For example, each piece of data sent to save/restore machine 212 is tagged to indicate which unit generated the piece of data. In one embodiment, data is streamed over a common bus to save/restore machine 212, and save/restore machine 212 uses the embedded tags to determine which unit(s) generated each piece of data. Save/restore machine 212 saves the status information and embedded tags to memory, and this stored data will be used later if a restore operation is requested in at least paragraph (21));
store in the main memory resource data indicated by a data save indicator in a command stream being executed (When operations are suspended on GPU 200, status information associated with the in-flight work-items is saved to memory by save/restore machine 212. Data associated with the in-flight work items is streamed from different units of GPU 200 to save/restore machine 212, and restore information identifying where the data came from is embedded alongside the data. For example, each piece of data sent to save/restore machine 212 is tagged to indicate which unit generated the piece of data. In one embodiment, data is streamed over a common bus to save/restore machine 212, and save/restore machine 212 uses the embedded tags to determine which unit(s) generated each piece of data. Save/restore machine 212 saves the status information and embedded tags to memory, and this stored data will be used later if a restore operation is requested in at least paragraph (21)).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the data save indicators and them being stored in the memory resource taught by Ashkar with the method of operating a data processing system taught by Underwood. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of having “improved techniques for implementing suspend and restore operations on a processor” especially because “determining how to suspend operations on the GPU to enable a seamless restoration can be challenging” (See Ashkar paragraph (3)).
With regard to claim 12, Underwood and Ashkar teach the system of claim 11. Underwood does not teach that the data retrieved when the processing task which is to be resumed is resumed comprises some but not all of the data which was saved to the main memory resource when the processing task which is to be resumed was suspended.
However, in analogous art, Ashkar teaches wherein the data retrieved when the processing task which is to be resumed is resumed comprises some but not all of the data which was saved to the main memory resource when the processing task which is to be resumed was suspended (At a later point of time, suspend/restore control unit 345 detects a request to restore one of the stored states 360A-B. In response to detecting the request to restore one of the stored states 360A-B, suspend/restore control unit 345 retrieves the work-item information from memory 355 and uses this information to restore work-items to queues 320A-N in at least paragraph (28), Examiner notes Ashkar teaches that there are stored states 360A and 360B and only one stored state is retrieved which can be interpreted to mean that some but not all of the data is being restored.)
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the partial data retrieval taught by Ashkar with the method of operating a data processing system taught by Underwood. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of having “improved techniques for implementing suspend and restore operations on a processor” especially because “determining how to suspend operations on the GPU to enable a seamless restoration can be challenging” (See Ashkar paragraph (3)).
With regard to claim 13, Underwood teaches a method of generating a command stream for causing a processing resource operable to perform data processing operations for applications executing on a host processor to perform a processing task comprising one or more processing operations (wherein the host processor comprises command stream generating circuitry operable to prepare, in response to a request for processing to be performed by the accelerator from an application being executed on the host processor, one or more command stream(s) for causing the accelerator to perform processing tasks for the application in at least paragraph [0020]);
the method comprising including in the command stream: a sequence of commands for execution by the processing resource to cause the processing resource to perform the processing operations for the processing task (Once all the required command sequences for the command stream have been built, then the command stream is in an embodiment made visible to the corresponding command stream interface (e.g. by appropriately “flushing” the work), so that the command stream interface can then start to execute the commands in the command stream (e.g. either immediately or after any still-executing previous command streams have been completed) in at least paragraph [0066]);
While Underwood teaches context switching, saving and suspending command streams, they do not teach the one or more save indicators.
However, in analogous art, Ashkar teaches one or more data save indicators indicative of data that should be saved in the event of processing of the processing task being suspended (For example, each piece of data sent to save/restore machine 212 is tagged to indicate which unit generated the piece of data. In one embodiment, data is streamed over a common bus to save/restore machine 212, and save/restore machine 212 uses the embedded tags to determine which unit(s) generated each piece of data. Save/restore machine 212 saves the status information and embedded tags to memory, and this stored data will be used later if a restore operation is requested in at least paragraph (21)).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the data save indicators taught by Ashkar with the method of generating a command stream taught by Underwood. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of having “improved techniques for implementing suspend and restore operations on a processor” especially because “determining how to suspend operations on the GPU to enable a seamless restoration can be challenging” (See Ashkar paragraph (3)).
With regard to claim 14, Underwood and Ashkar teach the method of claim 13, Ashkar teaches including a data save indicator in the command stream based on one or more of: the execution duration of commands in the command stream (In one embodiment, control unit 132 of GPU 130 is configured to initiate a suspend operation in response to receiving a request to suspend an application executing on GPU 130. In one embodiment, control unit 132 causes the work creation units (e.g., queues 135) to stop launching new work-items prior to initiating the suspend operation. In one embodiment, control unit 132 starts a timer prior to initiating the suspend operation and sets a grace period for work creation units to become idle based on a number of clock cycles of the timer. In another embodiment, control unit 132 waits to receive acknowledgements from all work creation units that these units have stopped creating new work. Once all work creation units have been idled, control unit 132 initiates the suspend operation to determine and record information about the in-flight work-items, the work creation units that launched the in-flight work-items, the execution units which have been allocated for the in-flight work-items, and additional status information. In one embodiment, control unit 132 stores the information as stored state 155 in memory 150. In other embodiments, control unit 132 can allocate stored state 155 in another location in at least paragraph (15) and in one embodiment, the command processor 205 also includes a save/restore machine 212. In one embodiment, the save/restore machine 212 is (or effectively implements) a finite state machine which is triggered and managed by firmware and/or microcode. When operations are suspended on GPU 200, status information associated with the in-flight work-items is saved to memory by save/restore machine 212. Data associated with the in-flight work items is streamed from different units of GPU 200 to save/restore machine 212, and restore information identifying where the data came from is embedded alongside the data in at least paragraph (21)).
With regard to claim 17, Underwood and Ashkar teach the method of claim 13, Underwood does not teach that the data retrieved when the processing task which is to be resumed is resumed comprises some but not all of the data which was saved to the main memory resource when the processing task which is to be resumed was suspended.
However, in analogous art, Ashkar teaches including one or more data retrieval indicators in the command stream, the one or more data retrieval indicators configured to indicate data which should be retrieved from the main memory resource when the processing task is resumed after having been previously suspended (In one embodiment, suspend/restore control unit 345 will receive streamed data from various parts of the processor that manage work-items, and restore information will be embedded with the streamed data indicating where the work-items came from in the processor. Suspend/restore control unit 345 will save this data to memory, and this saved data will be used later if a restore operation is requested in at least paragraph (25), Examiner notes that the embedded restore information with the streamed data taught by Ashkar can be a data retrieval indicator in the command stream).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the partial data retrieval taught by Ashkar with the method of operating a data processing system taught by Underwood. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the as “improved techniques for implementing suspend and restore operations on a processor are desired” especially because “determining how to suspend operations on the GPU to enable a seamless restoration can be challenging” (See Ashkar paragraph (3)).
With regard to claim 18, Underwood and Askar teach the method of claim 17 and its data retrieval indicators. Underwood does not specifically teach that the one or more data retrieval indicators are based on the location of the one or more save indicators and whether data that will be generated or changed on execution of a preceding command or commands in the command stream will be required in the further execution of the command stream.
However, in analogous art, Ashkar teaches that including a data retrieval indicator in the command stream based on one or more of: the location of one of the one or more data save indicators in the command stream (In one embodiment, the command processor 205 also includes a save/restore machine 212. In one embodiment, the save/restore machine 212 is (or effectively implements) a finite state machine which is triggered and managed by firmware and/or microcode. When operations are suspended on GPU 200, status information associated with the in-flight work-items is saved to memory by save/restore machine 212. Data associated with the in-flight work items is streamed from different units of GPU 200 to save/restore machine 212, and restore information identifying where the data came from is embedded alongside the data. For example, each piece of data sent to save/restore machine 212 is tagged to indicate which unit generated the piece of data. In one embodiment, data is streamed over a common bus to save/restore machine 212, and save/restore machine 212 uses the embedded tags to determine which unit(s) generated each piece of data. Save/restore machine 212 saves the status information and embedded tags to memory, and this stored data will be used later if a restore operation is requested. This restore information will be used by the save/restore machine 212 to redirect the saved data in memory back to the original source in response to a restore operation being launched in at least paragraph (33), Examiner notes that the data retrieval happens on the basis of the location of the tags i.e. the embedded tags used to determine which unit(s) generated each piece of data in the command stream);
whether data that will be generated or changed on execution of a preceding command or commands in the command stream will be required in the further execution of the command stream (The control unit also retrieves stored information, corresponding to the previously suspended state, about in-flight work items and corresponding work creation units and execution units. Also, prior to restoring in-flight work-items to each work creation unit, the control unit prevents the plurality of work creation units from launching new work-items. Then, the control unit restores in-flight work items to each work creation unit and corresponding execution units in at least paragraph (11)).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the data retrieval indicators and their basis taught by Ashkar with generating a command stream for causing a processing resource operable to perform data processing operations taught by Underwood and Ashkar. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, as “improved techniques for implementing suspend and restore operations on a processor are desired” especially because “determining how to suspend operations on the GPU to enable a seamless restoration can be challenging” (See Ashkar paragraph (3)).
With regard to claim 19, Underwood teaches a non-transitory computer readable storage medium storing computer software code (The technology described herein may accordingly suitably be embodied as a computer program product for use with a computer system. Such an implementation may comprise a series of computer readable instructions either fixed on a tangible, non-transitory medium, such as a computer readable medium, for example, diskette, CD-ROM, ROM, RAM, flash memory, or hard disk in at least paragraph [0138]);
when executing on at least one processor (The methods in accordance with the technology described herein may be implemented at least partially using software e.g. computer programs. It will thus be seen that when viewed from further embodiments the technology described herein comprises computer software specifically adapted to carry out the methods herein described when installed on a data processor, a computer program comprising computer software code for performing the methods herein described when the program is run on a data processor, and a computer program comprising software code portions for performing all the steps of a method or of the methods herein described when the program is run on a data processor. The data processor may be a microprocessor system, a programmable FPGA (field programmable gate array), etc. in at least paragraph [0135]);
the method comprising including in the command stream: a sequence of commands for execution by the processing resource to cause the processing resource to perform the processing operations for the processing task (Thus, the technology described herein generally relates to data processing systems comprising an accelerator that is operable to execute a sequence of commands in a command stream provided by a host processor in order to perform processing work for applications executing on the operating system of the host processor. For instance, when a request for processing work by the accelerator is made by an application on the host processor, the host processor can then prepare one or more command stream(s) including a plurality of commands (instructions) specifying the processing work to be performed by the accelerator. The commands (instructions) are then implemented on the accelerator, e.g. using a suitable command stream execution unit under the control of a supervising controller, with the commands being executed in turn in order to perform the desired (requested) processing work in at least paragraph [0030]);
Underwood does not teach performing a method of generating a command stream and the one or more data save indicators indicative of data that should be saved in the event of processing of the processing task being suspended.
However, in analogous art, Ashkar teaches performs a method of generating a command stream for causing a processing resource operable to perform data processing operations for applications executing on a host processor to perform a processing task comprising one or more processing operations (wherein the host processor comprises command stream generating circuitry operable to prepare, in response to a request for processing to be performed by the accelerator from an application being executed on the host processor, one or more command stream(s) for causing the accelerator to perform processing tasks for the application in at least paragraph [0020]);
one or more data save indicators indicative of data that should be saved in the event of processing of the processing task being suspended (When operations are suspended on GPU 200, status information associated with the in-flight work-items is saved to memory by save/restore machine 212. Data associated with the in-flight work items is streamed from different units of GPU 200 to save/restore machine 212, and restore information identifying where the data came from is embedded alongside the data. For example, each piece of data sent to save/restore machine 212 is tagged to indicate which unit generated the piece of data. In one embodiment, data is streamed over a common bus to save/restore machine 212, and save/restore machine 212 uses the embedded tags to determine which unit(s) generated each piece of data. Save/restore machine 212 saves the status information and embedded tags to memory, and this stored data will be used later if a restore operation is requested in at least paragraph (21).
Claims 2, 3, 8, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Underwood et al. Pub. No. US 2020/0050478 A1 (hereafter Underwood) in view of Ashkar et al. Pub. No. US 10,558,489 B2 (hereafter Ashkar) as applied to claim 1 above and in further view of STEPHENS et al. Pub No. US 2021/0042115 A1 (hereafter Stephens).
With regard to claim 2, Underwood and Ashkar teach the method of claim 1. They do not teach that the processing task is a neural networking task.
However, in analogous art, Stephens teaches that the processing task is a task that performs neural network processing (Some data processing applications may involve processing of individual data values, where a data value is loaded from a specific address, and processed by some instructions executed by the processing circuitry 14 to generate results which are written to the registers 16, and then once the results can no longer be held within the registers 16 then they are written back to the cache 18 or memory 8. However, other processing algorithms may operate on larger data structures which comprise a number of separate data values forming elements of the data structure. For example the data structure could be a stream of data of one-dimensional extent of considerable size, such as a block of data to be compressed for example. Alternatively, the data structure could be a matrix or table of two or more dimensions, for which a processing operation is to be applied to the matrix/table as a whole. As shown in FIG. 2, one example of such a data structure may be a matrix (in this example a 2-dimensional matrix). Matrix processing can be useful for certain processing algorithms such as some signal processing applications or machine learning applications in at least paragraphs [0062] - [0064], Examiner notes that the data processing taught by Stephens can also process data structure instructions such as matrices and those count as neural network processing tasks).
It would have been prima facie obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute the processing task in Underwood and Ashkar in the context of the method of the data processing system with “a 2-dimensional matrix” which is a part of “neural network based processing” (See at least Stephens [0064]), for a similar purpose. All the combinations Underwood, Ashkar, and Stephens teach a method of a data processing system that deal operate on processing tasks (See at least Stephens [004]).
While Underwood and Ashkar disclose a processing task, they do not disclose operating on a neural network based processing task and it being a simple substitution for any use case. Stephens fills this gap by teaching that “the data structure could be a stream of data of one-dimensional extent of considerable size, such as a block of data to be compressed for example. Alternatively, the data structure could be a matrix or table of two or more dimensions, for which a processing operation is to be applied to the matrix/table as a whole” and that working on matrices/neural network based processing being an alternate use case as “matrix processing can be useful for certain processing algorithms such as some signal processing applications or machine learning applications” (See Stephens [0063] and [0064]) in a method that is substantially similar and capable of substitution to that of Underwood and Ashkar.
The use of neural network processing task in place of the processing task in Underwood and Ashkar, is a predictable use of prior art elements according to their established functions, leading to the predictable result of performing matrix/neural network processing for machine learning applications.
With regard to claim 3, Underwood and Askar teach the method of claim 1. They do not teach that at least one of the one or more data save indicators is in the form of a table which associates respective ones of a plurality of different blocks of working memory in the working memory resource with indications of whether the contents of each block of working memory should be saved to the main memory resource.
However, in analogous art, Stephens teaches at least one of the one or more data save indicators is in the form of a table which associates respective ones of a plurality of different blocks of working memory in the working memory resource with indications of whether the contents of each block of working memory should be saved to the main memory resource (For data structures which correspond to a number of discontiguous blocks of memory addresses, the address-indicating metadata can comprise a number of pieces of information and may take a number of forms. For example the address indicating metadata may comprise at least one of: start address information indicative of a start address of at least one of the plurality of discontiguous blocks of memory addresses; offset information indicative of a separation between start addresses of the plurality of discontiguous blocks of memory addresses; first size information indicative of a size of each discontiguous block of memory addresses; and second size information indicative of how many of the discontiguous blocks of memory addresses form the data structure. Alternatively, rather than indicating the start address information, offset information, or first and second size information directly, other examples may provide address indicating metadata which identifies this indirectly, for example through one or more register identifiers identifying general purpose registers holding at least one of these parameters, and/or an instruction address indication which identifies an address of an instruction specifying registers holding one or more of these parameters. As mentioned above, the register identifiers or the instruction address indication (e.g. a program counter) may be enough for software or circuitry which needs to restore a data structure to the storage circuitry of the processing circuitry to identify where the data structure can be found in memory. In some cases the data structure could be a 3-dimensional or multi-dimensional data structure of order greater than 3, so it is not essential that the data structure is a 2-dimensional data structure. In general the data structure can be some ordered arrangement of data elements. [0056] Alternatively, another example of the data structure can simply be a 1-dimensional stream of data elements, without a 2 or more dimensional arrangement such as in a table or matrix. Examiner notes that the metadata in the data structure taught by Stephens in its broadest reasonable interpretation could be a data save indicator in at least paragraphs [0052], [0054], and [0055]. Examiner notes that the metadata in the data structure taught by Stephens in its broadest reasonable interpretation could be a data save indicator).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the table formatted one or more data save indicators which are associated with the plurality of the different blocks of the working memory in the working memory resource with indications of whether the contents of each block of working memory should be saved to the main memory resource taught by Stephens with the method of the data processing system taught by Underwood and Ashkar. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, such that the method “can then be used to ensure that any data structure processing instruction is applied only to the portion of the discontiguous blocks of memory addresses which represent the part of the overall larger data structure which should be processed by an individual data structure processing instruction (See Stephens paragraph [0052]).
With regard to claim 8, Underwood and Ashkar teach the system of claim 7. They do not teach that the processing task is a neural networking task.
However, in analogous art, Stephens teaches that the processing task is a task that performs neural network processing (Some data processing applications may involve processing of individual data values, where a data value is loaded from a specific address, and processed by some instructions executed by the processing circuitry 14 to generate results which are written to the registers 16, and then once the results can no longer be held within the registers 16 then they are written back to the cache 18 or memory 8. However, other processing algorithms may operate on larger data structures which comprise a number of separate data values forming elements of the data structure. For example the data structure could be a stream of data of one-dimensional extent of considerable size, such as a block of data to be compressed for example. Alternatively, the data structure could be a matrix or table of two or more dimensions, for which a processing operation is to be applied to the matrix/table as a whole. As shown in FIG. 2, one example of such a data structure may be a matrix (in this example a 2-dimensional matrix). Matrix processing can be useful for certain processing algorithms such as some signal processing applications or machine learning applications in at least paragraphs [0062] - [0064], Examiner notes that the data processing taught by Stephens can also process data structure instructions such as matrices and those count as neural network processing tasks).
It would have been prima facie obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute the processing task in Underwood and Ashkar in the context of the method of the data processing system with “a 2-dimensional matrix” which is a part of “neural network based processing” (See at least Stephens [0064]), for a similar purpose. All the combinations Underwood, Ashkar, and Stephens teach a method of a data processing system that deal operate on processing tasks (See at least Stephens [004]).
While Underwood and Ashkar disclose a processing task, they do not disclose operating on a neural network based processing task and it being a simple substitution for any use case. Stephens fills this gap by teaching that “the data structure could be a stream of data of one-dimensional extent of considerable size, such as a block of data to be compressed for example. Alternatively, the data structure could be a matrix or table of two or more dimensions, for which a processing operation is to be applied to the matrix/table as a whole” and that working on matrices/neural network based processing being an alternate use case as “matrix processing can be useful for certain processing algorithms such as some signal processing applications or machine learning applications” (See Stephens [0063] and [0064]) in a method that is substantially similar and capable of substitution to that of Underwood and Ashkar.
The use of neural network processing task in place of the processing task in Underwood and Ashkar, is a predictable use of prior art elements according to their established functions, leading to the predictable result of performing matrix/neural network processing for machine learning applications.
With regard to claim 9, Underwood and Askar teach the system of claim 7. They do not teach that at least one of the one or more data save indicators is in the form of a table which associates respective ones of a plurality of different blocks of working memory in the working memory resource with indications of whether the contents of each block of working memory should be saved to the main memory resource.
However, in analogous art, Stephens teaches at least one of the one or more data save indicators is in the form of a table which associates respective ones of a plurality of different blocks of working memory in the working memory resource with indications of whether the contents of each block of working memory should be saved to the main memory resource (For data structures which correspond to a number of discontiguous blocks of memory addresses, the address-indicating metadata can comprise a number of pieces of information and may take a number of forms. For example the address indicating metadata may comprise at least one of: start address information indicative of a start address of at least one of the plurality of discontiguous blocks of memory addresses; offset information indicative of a separation between start addresses of the plurality of discontiguous blocks of memory addresses; first size information indicative of a size of each discontiguous block of memory addresses; and second size information indicative of how many of the discontiguous blocks of memory addresses form the data structure. Alternatively, rather than indicating the start address information, offset information, or first and second size information directly, other examples may provide address indicating metadata which identifies this indirectly, for example through one or more register identifiers identifying general purpose registers holding at least one of these parameters, and/or an instruction address indication which identifies an address of an instruction specifying registers holding one or more of these parameters. As mentioned above, the register identifiers or the instruction address indication (e.g. a program counter) may be enough for software or circuitry which needs to restore a data structure to the storage circuitry of the processing circuitry to identify where the data structure can be found in memory. In some cases the data structure could be a 3-dimensional or multi-dimensional data structure of order greater than 3, so it is not essential that the data structure is a 2-dimensional data structure. In general the data structure can be some ordered arrangement of data elements. [0056] Alternatively, another example of the data structure can simply be a 1-dimensional stream of data elements, without a 2 or more dimensional arrangement such as in a table or matrix. Examiner notes that the metadata in the data structure taught by Stephens in its broadest reasonable interpretation could be a data save indicator in at least paragraphs [0052], [0054], and [0055]. Examiner notes that the metadata in the data structure taught by Stephens in its broadest reasonable interpretation could be a data save indicator).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the table formatted one or more data save indicators which are associated with the plurality of the different blocks of the working memory in the working memory resource with indications of whether the contents of each block of working memory should be saved to the main memory resource taught by Stephens with the method of the data processing system taught by Underwood and Ashkar. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, such that the method “can then be used to ensure that any data structure processing instruction is applied only to the portion of the discontiguous blocks of memory addresses which represent the part of the overall larger data structure which should be processed by an individual data structure processing instruction (See Stephens paragraph [0052]).
Claims 4-6, 10, 11, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Underwood et al. Pub. No. US 2020/0050478 A1 (hereafter Underwood) in view of Ashkar et al. Pub. No. US 10,558,489 B2 (hereafter Ashkar) as applied to claims 1 and 7 above and in further view of LUIZ et al. Pub No. US 2017/0010914 A1 (hereafter Luiz).
With regard to claim 4, Underwood and Ashkar teach the method of claim 1. Underwood does not teach that the command stream additionally comprises one or more permitted suspend indicators which indicate where in the command stream the processing task is permitted to be suspended.
However, in analogous art, Luiz teaches that the command stream additionally comprises one or more permitted suspend indicators which indicate where in the command stream the processing task is permitted to be suspended (A sequence of per-thread instructions may include at least one instruction that defines a cooperative behavior between the representative thread and one or more other threads of the thread array. For example, the sequence of per-thread instructions could include an instruction to suspend execution of operations for the representative thread at a particular point in the sequence until such time as one or more of the other threads reach that particular point, an instruction for the representative thread to store data in a shared memory to which one or more of the other threads have access, an instruction for the representative thread to atomically read and update data stored in a shared memory to which one or more of the other threads have access based on their thread IDs, or the like in at least paragraph [0046]).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the permitted suspend indicators taught by Luiz with the method of operating a data processing system taught by Underwood. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “restoring threads within a processing core” as part of a trap handling routine that operates efficiently in parallel processors (See the Abstract and Summary of the Invention of Luiz).
With regard to claim 5, Underwood, Ashkar, and Luiz teach the method of claim 4. Underwood does not teach that in response to a request to resume a previously suspended processing task, the processing resource retrieves from the main memory resource some or all of the data previously saved to the main memory resource when processing of the task which is to be resumed was suspended.
However, in analogous art, Ashkar teaches in response to a request to resume a previously suspended processing task (In one embodiment, control unit 132 of GPU 130 is configured to initiate a restore operation in response to receiving a request to restore a previously suspended application. After restoring all of the previously in-flight work-items, control unit 132 allows the work creation units to start launching new work-items. It is noted that a “restore operation” can also be referred to as a “resume operation” in at least paragraph (16));
the processing resource retrieves from the main memory resource some or all of the data previously saved to the main memory resource when processing of the task which is to be resumed was suspended (In response to receiving the request, control unit 132 retrieves status information (e.g., stored state 155) corresponding to the previously suspended application in at least paragraph (16)).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the retrieval of the data previously saved to the main memory resource in response to a request to resume a previously suspended processing task taught by Ashkar with the method of operating a data processing system taught by Underwood. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of having “improved techniques for implementing suspend and restore operations on a processor” especially because “determining how to suspend operations on the GPU to enable a seamless restoration can be challenging” (See Ashkar paragraph (3)).
With regard to claim 6, Underwood, Ashkar, and Luiz teach the method of claim 5. Underwood does not teach that the data retrieved when the processing task which is to be resumed is resumed comprises some but not all of the data which was saved to the main memory resource when the processing task which is to be resumed was suspended.
However, in analogous art, Ashkar teaches wherein the data retrieved when the processing task which is to be resumed is resumed comprises some but not all of the data which was saved to the main memory resource when the processing task which is to be resumed was suspended (At a later point of time, suspend/restore control unit 345 detects a request to restore one of the stored states 360A-B. In response to detecting the request to restore one of the stored states 360A-B, suspend/restore control unit 345 retrieves the work-item information from memory 355 and uses this information to restore work-items to queues 320A-N in at least paragraph (28), Examiner notes Ashkar teaches that there are stored states 360A and 360B and only one stored state is retrieved which can be interpreted to mean that some but not all of the data is being restored.)
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the partial data retrieval taught by Ashkar with the method of operating a data processing system taught by Underwood. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of having “improved techniques for implementing suspend and restore operations on a processor” especially because “determining how to suspend operations on the GPU to enable a seamless restoration can be challenging” (See Ashkar paragraph (3)).
With regard to claim 10, Underwood and Ashkar teach the system of claim 7. Underwood does not teach that the command stream additionally comprises one or more permitted suspend indicators which indicate where in the command stream the processing task is permitted to be suspended.
However, in analogous art, Luiz teaches that the command stream comprises one or more permitted suspend indicators which indicate where in the command stream a processing task is permitted to be suspended (A sequence of per-thread instructions may include at least one instruction that defines a cooperative behavior between the representative thread and one or more other threads of the thread array. For example, the sequence of per-thread instructions could include an instruction to suspend execution of operations for the representative thread at a particular point in the sequence until such time as one or more of the other threads reach that particular point, an instruction for the representative thread to store data in a shared memory to which one or more of the other threads have access, an instruction for the representative thread to atomically read and update data stored in a shared memory to which one or more of the other threads have access based on their thread IDs, or the like in at least paragraph [0046]).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the permitted suspend indicators taught by Luiz with the method of operating a data processing system taught by Underwood. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “restoring threads within a processing core” as part of a trap handling routine that operates efficiently in parallel processors (See the Abstract and Summary of the Invention of Luiz).
With regard to claim 11, Underwood, Ashkar, and Luiz teach the system of claim 10. Underwood does not teach that in response to a request to resume a previously suspended processing task, the processing resource retrieves from the main memory resource some or all of the data previously saved to the main memory resource when processing of the task which is to be resumed was suspended.
However, in analogous art, Ashkar teaches in response to a request to resume a previously suspended processing task (In one embodiment, control unit 132 of GPU 130 is configured to initiate a restore operation in response to receiving a request to restore a previously suspended application. After restoring all of the previously in-flight work-items, control unit 132 allows the work creation units to start launching new work-items. It is noted that a “restore operation” can also be referred to as a “resume operation” in at least paragraph (16));
retrieve from the main memory resource some or all of the data previously saved to the main memory resource when processing of the task which is to be resumed was suspended (In response to receiving the request, control unit 132 retrieves status information (e.g., stored state 155) corresponding to the previously suspended application in at least paragraph (16)).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the retrieval of the data previously saved to the main memory resource in response to a request to resume a previously suspended processing task taught by Ashkar with the method of operating a data processing system taught by Underwood. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of having “improved techniques for implementing suspend and restore operations on a processor” especially because “determining how to suspend operations on the GPU to enable a seamless restoration can be challenging” (See Ashkar paragraph (3)).
With regard to claim 15, Underwood and Ashkar teach the method of claim 13. Underwood does not teach that the command stream additionally comprises one or more permitted suspend indicators which indicate where in the command stream the processing task is permitted to be suspended.
However, in analogous art, Luiz teaches including one or more permitted suspend indicators in the command stream, the one or more permitted suspend indicators configured to indicate where in the command stream the processing of the processing task may be suspended (A sequence of per-thread instructions may include at least one instruction that defines a cooperative behavior between the representative thread and one or more other threads of the thread array. For example, the sequence of per-thread instructions could include an instruction to suspend execution of operations for the representative thread at a particular point in the sequence until such time as one or more of the other threads reach that particular point, an instruction for the representative thread to store data in a shared memory to which one or more of the other threads have access, an instruction for the representative thread to atomically read and update data stored in a shared memory to which one or more of the other threads have access based on their thread IDs, or the like in at least paragraph [0046]).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the permitted suspend indicators taught by Luiz with the method of operating a data processing system taught by Underwood. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “restoring threads within a processing core” as part of a trap handling routine that operates efficiently in parallel processors (See the Abstract and Summary of the Invention of Luiz).
With regard to claim 16, Underwood, Ashkar, and Luiz teach the method of claim 15, Ashkar teaches including a permitted suspend indicator in the command stream based on one or more of: the execution duration of commands in the command stream (In one embodiment, control unit 132 of GPU 130 is configured to initiate a suspend operation in response to receiving a request to suspend an application executing on GPU 130. In one embodiment, control unit 132 causes the work creation units (e.g., queues 135) to stop launching new work-items prior to initiating the suspend operation. In one embodiment, control unit 132 starts a timer prior to initiating the suspend operation and sets a grace period for work creation units to become idle based on a number of clock cycles of the timer. In another embodiment, control unit 132 waits to receive acknowledgements from all work creation units that these units have stopped creating new work. Once all work creation units have been idled, control unit 132 initiates the suspend operation to determine and record information about the in-flight work-items, the work creation units that launched the in-flight work-items, the execution units which have been allocated for the in-flight work-items, and additional status information. In one embodiment, control unit 132 stores the information as stored state 155 in memory 150. In other embodiments, control unit 132 can allocate stored state 155 in another location in at least paragraph (15)).
Conclusion
The prior art made of record and not relied upon for the following teachings is considered pertinent to applicant’s disclosure.
US 2017/0010914 A1
teaches
save indicators based on or more of: whether a command or commands in the command stream will generate new data or change existing data when executed, whether the command stream includes a particular type of command, and the number of commands in the command stream since a data save indicator in the command stream
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
When responding to this Office Action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 CFR 1.111(c).
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/S.E./Examiner, Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197
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