Prosecution Insights
Last updated: August 18, 2026
Application No. 18/499,660

THERMAL APPARATUS FOR AN INTEGRATED CIRCUIT AND METHODS OF OPERATION

Non-Final OA §103§112
Filed
Nov 01, 2023
Priority
Sep 12, 2023 — IN 202341061226
Examiner
MOORE, DEVON TYLEN
Art Unit
3763
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
NXP Semiconductors N.V.
OA Round
3 (Non-Final)
47%
Grant Probability
Moderate
3-4
OA Rounds
4m
Est. Remaining
80%
With Interview

Examiner Intelligence

Grants 47% of resolved cases
47%
Career Allowance Rate
80 granted / 169 resolved
-22.7% vs TC avg
Strong +33% interview lift
Without
With
+32.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
65 currently pending
Career history
253
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
56.2%
+16.2% vs TC avg
§102
11.0%
-29.0% vs TC avg
§112
31.8%
-8.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 169 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 13th, 2026 has been entered. Claim Objections Claims 1-11 are objected to because of the following informalities: Claim 1, lines 7-8: “an integrated circuit” should read “the integrated circuit” Claim 3, lines 6-7: “one a voltage level” should read “one of a voltage level” Claims 2-3, 5, 8, and 11 are also objected to by virtue of their dependency on claim 1. Claim 4 is also objected to by virtue of its dependency on claim 3. Claim 6 is also objected to by virtue of its dependency on claim 5. Claim 7 is also objected to by virtue of its dependency on claim 6. Claim 9 is also objected to by virtue of its dependency on claim 8. Claim 10 is also objected to by virtue of its dependency on claim 9. Appropriate correction is required. Claim Rejections - 35 USC § 112(a) The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 3, lines 1-5 recite, “wherein a first general purpose input output (GPIO) pin of a processor of the controller is directly connected to a first voltage shifter and a second GPIO pin of the processor of the controller is directly connected to a second voltage shifter, the first terminal of the Peltier element is directly connected to an output of the first voltage shifter and a second terminal of the Peltier element is directly connected to an output of the second voltage shifter”, which is not supported by the disclosure. Although, Figures 3-6 depict GPIOm and GPIOn of MCU 302 to be connected to voltage shifter 304 and voltage shifter 306 via inputs 310 and voltage shifter 304 and voltage shifter 306 to be connected to terminals 126 and 128 of Peltier element 114 via outputs 312, the drawings are not detailed schematics showing all of the electrical connections between components of the controller 136 and cannot be solely relied upon to support direct connections of the electrical components of the system. The closest support for this in the specification is as follows, “Based on the junction temperature indicated by the sensor 308, the controller 136 may output the first signal to the voltage shifter 304 and the second signal to the voltage shifter 306 or vice versa. If the controller 136 outputs the first signal to the voltage shifter 304 and the second signal to the voltage shifter 306, a first and second voltage may be applied to the terminals 126, 128 respectively to produce a first polarity across the terminals and cause a heating of the ceramic substrate 122 and a cooling of the ceramic substate 124. If the controller 136 outputs the first signal to the voltage shifter 306 and the second signal to the voltage shifter 304, the first and second voltage may be applied to the terminals 126, 128 respectively to produce a second polarity across the terminals and cause a heating of the ceramic substrate 124 and a cooling of the ceramic substate 122 where the first and second polarities are opposite such as positive and negative polarities (Pg. 8, paragraph 18).” However, this is only support for the first voltage shifter 304 and the second voltage shifter 306 being in communication with both the controller 136 and the terminals 126, 128 of the Peltier element 114, this is not support for any direct connections. Further, the communications between the GPIOm and GPIOn of MCU 302 and between voltage shifter 304 and voltage shifter 306 and terminals 126 and 128, identified as items 310 and 312, are only referred to as inputs and outputs and are not described by the specification to be any kind of physical connection for electrical communication between the components, “The voltage shifters may have a respective input 310 and output 312. The volage that is output by a voltage shifter at the output 312 may depend on a signal applied to the input 310 of the voltage shifter (Pg. 8, paragraph 18)”. Claim 4 is also rejected by virtue of its dependency on claim 3. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 5-6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20220104387), hereinafter Yang in view of Chou et al. (US Patent No. 9,625,186), hereinafter Chou. Regarding claim 1, Yang discloses a system (Fig. 1) comprising: an integrated circuit (Fig. 1, electronic component 101; Pg. 2, paragraph 37, The electronic component 101 may include, but not being limited to, an electronic chip, a memory package, capacitor, resistor, inductor, transistor, or any type of electronic component, etc.); a heatsink which is in contact with packaging of the integrated circuit (Fig. 1, heat sink 105, package lid 103; Pg. 3, paragraph 39, In one embodiment, the thermoelectric element 102 may be disposed inside the heat sink or cold plate 105); a Peltier element comprising a first surface and a second surface and positioned in a cavity of the heatsink (Fig. 1, thermoelectric element 102; Pg. 3, paragraph 39, In one embodiment, the thermoelectric element 102 may be disposed inside the heat sink or cold plate 105; Pg. 3, paragraph 40, The thermoelectric element (TEE) 102 may operate based on a peltier effect. When a current is flowing in the TEE 102 in a positive direction, the TEE 102 may be used for a cooling purpose, where heat is transferred from a side A to a side B of the TEE 102. When the current is flowing in the TEE 102 in a negative direction, the TEE 102 may be used for a heating purpose, where the heat is transferred from the side B to the side A of the TEE. However, there is a limitation on a maximum temperature difference between the two sides); and a controller (Fig. 1, controller 106); wherein based on a first indication from a sensor, the sensor located on the integrated circuit, the controller applies a first polarity to the Peltier element to reduce a temperature of the second surface to cool the integrated circuit and based on a second indication from the sensor, the controller applies a second polarity to the Peltier element to increase the temperature of the second surface to heat the integrated circuit (Fig. 1, electrical circuit 104; Pg. 3, paragraph 39, The thermoelectric element 102 itself may be connected to the external electrical circuit 104 for a current control purpose; Pg. 4, paragraph 51, The controller may control the switches' duty cycles based on the temperature data obtained from one or more temperature sensors coupled to the electronic components (e.g., processor) or coupled to different sides of TEE element 102. Based on the temperature, the control may turn on or off some of the switches to control the current flow direction of a current flowing through TEE 102, which enables the TEE 102 to operate in a cooling mode or a heating mode; Pg. 3, paragraph 40, The thermoelectric element (TEE) 102 may operate based on a peltier effect. When a current is flowing in the TEE 102 in a positive direction, the TEE 102 may be used for a cooling purpose, where heat is transferred from a side A to a side B of the TEE 102. When the current is flowing in the TEE 102 in a negative direction, the TEE 102 may be used for a heating purpose, where the heat is transferred from the side B to the side A of the TEE. However, there is a limitation on a maximum temperature difference between the two sides; Pg. 4, paragraph 61, As illustrated in FIG. 5, the self-regulated controller 106 may have at least two inputs 501, 502 and two outputs 503, 504. The two temperature inputs 501, 502 may be sensed from temperature sensors. For example, a first input 501 may receive the temperature of the first side (side A) of the TEE from a first sensor, and a second input 502 may receive the temperature of the second side (side B) of the TEE from a second sensor. Based on the temperatures of the first side (side A) and the second side (side B), the controller 106 may decide the current flow direction of the bidirectional current based on a logic shown in FIG. 6, which will be described below. This self-regulated controller may be embedded into a core controller); wherein the first polarity and the second polarity are applied to control the temperature measured by the sensor to be within an optimal temperature range which spans an upper temperature and a lower temperature, the optimal temperature range being within an operating range of the integrated circuit defined by a minimum operating temperature and a maximum operating temperature of the integrated circuit (Fig. 6, steps 601-608; Pg. 5, paragraph 65-68, At block 602, the temperature of the first side (side A) of the TEE and the temperature of the second side (side B) of the TEE may be read in, by the controller. At block 603, whether the T_A, the temperature of the first side (side A) of the TEE, is lower than the minimum allowable temperature may be determined by the controller. At block 604, the controller may determine that the T_A is below the minimum allowable temperature and output a command for a direction of a bidirectional current to heat up the electronic component, for example, a negative current direction. The self-regulated heat transfer controller may be configured to determine a current flow direction of a bidirectional current in the TEE is to be in a direction to heat up the electronic component in response to determining that the temperature of the first side of the thermoelectric element is lower than the minimum temperature allowable for the electronic component. In one embodiment, the direction to heat up the electronic component may be the negative current direction. When the T_A is below the minimum allowable temperature, the current flow may be negative such that TEM is acting as a heat pump, to transfer heat from the ambient environment to the electronic component to heat up the electronic component. In this way, high temperature external heating source is not required to transfer heat to the component to heat up the component, thus, eliminating the need of the external heating source. At block 605, the controller may determine whether T_A, the temperature of the first side (side A) of the TEE, is lower than T_target, the target temperature; Pg. 5, paragraph 70-71, At block 607, in response to determining that T_A, the temperature of the first side (side A) of the TEE, is not lower than T_target, the target temperature, the controller may further determine whether T_A, the temperature of the first side (side A) of the TEE, is higher than T_B, the temperature of the second side (side B) of the TEE. At block 608, the controller may output a command for a direction of the bidirectional current to cool the electronic component, for example, a positive current direction, in response to determining that T A, the temperature of the first side (side A) of the TEE, is higher than T_B, the temperature of the second side (side B) of the TEE. In one embodiment, the self-regulated heat transfer controller may be configured to determine the current flow direction of the bidirectional current in the TEE is to be in a direction to cool the electronic component in response to determining that the temperature of the first side of the thermoelectric element is higher than the temperature of the second side of the thermoelectric element; Further, the teachings of Yang as least imply an optimal temperature range which spans an upper temperature and a lower temperature, the optimal temperature range being within an operating range of the integrated circuit defined by a minimum operating temperature and a maximum operating temperature of the integrated circuit it has been held in considering the disclosure of a reference, it is proper to take into account not only specific teachings of the reference but also the inferences which one skilled in the art would reasonably be expected to draw therefrom (MPEP 2144.01)); and wherein the controller is configured to apply neither the first polarity nor the second polarity to the Peltier element when the junction temperature of the integrated circuit, as measured by the sensor, is within the optimal temperature range (Fig 6, block 606; Pg. 5, paragraph 69, At block 606, when the T_Ais above the minimum allowable temperature, but is below T_target, the target temperature, there is no need to initiate action for heat transfer). However, Yang does not disclose the sensor to measure a junction temperature of the integrated circuit and the upper temperature and lower temperature selected to define a predetermined reliability of the integrated circuit during operation in a first temperature environment and a second temperature environment, the upper temperature being a temperature in the first temperature environment, and the lower temperature being a temperature in the second temperature environment. Chou teaches the sensor to measure a junction temperature of the integrated circuit and the upper temperature and lower temperature selected to define a predetermined reliability of the integrated circuit during operation in a first temperature environment and a second temperature environment, the upper temperature being a temperature in the first temperature environment, and the lower temperature being a temperature in the second temperature environment (Fig. 5A, 3D IC 314, thermoelectric coolers 202 and 204, controller 212, temperature monitor 510; Fig. 6, first predetermined setpoint 602, second predetermined setpoint 604, desired temperature threshold 606; Col. 8, lines 15-37, FIG. 5A is a simplified block diagram of a stacked cell 3D IC 314 with temperature monitor 510 and controller 212 in accordance with some embodiments of the present disclosure. In the illustrated embodiment, temperature monitor 510 is disposed adjacent to hot spot 430. Hot spot 430 and temperature monitor 510 are disposed between first ILV 502 and second ILV 504. First ILV 502 and second ILV 504 are connected to first thermoelectric cooler 202 and second thermoelectric cooler 204 by local vias 326 or microbumps. In some embodiments, first ILV 502 is connected only to one of thermoelectric cooler 202 and second thermoelectric cooler 204. In some embodiments, second ILV 504 is connected only to one of thermoelectric cooler 202 and second thermoelectric cooler 204. Temperature monitor 510 can be disposed in any location within the stacked cell 3D IC 314. Disposing temperature monitor 510 adjacent to or in the vicinity of hot spot 430 allows for monitoring the area of the stacked cell 3D IC 314 most likely to exceed temperature design thresholds. In some embodiments, temperature monitor 510 is implemented as a thermal detector 700 as described below in relation to FIG. 7; Also see Fig. 9, method 900). Yang fails to teach the sensor to measure a junction temperature of the integrated circuit and the upper temperature and lower temperature selected to define a predetermined reliability of the integrated circuit during operation in a first temperature environment and a second temperature environment, the upper temperature being a temperature in the first temperature environment, and the lower temperature being a temperature in the second temperature environment, however Chou teaches that it is a known method in the art of Peltier temperature control of integrated circuits to include the sensor to measure a junction temperature of the integrated circuit and the upper temperature and lower temperature selected to define a predetermined reliability of the integrated circuit during operation in a first temperature environment and a second temperature environment, the upper temperature being a temperature in the first temperature environment, and the lower temperature being a temperature in the second temperature environment. This is strong evidence that modifying Yang as claimed would produce predictable results (i.e. maintaining the integrated circuit within an optimal temperature range to improve overall system efficiencies). Accordingly, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yang by Chou and arrive at the claimed invention since all claimed elements were known in the art and one having ordinary skill in the art could have combined the elements as claimed by known methods with no changes in their respective functions and the combination would have yielded the predictable result of maintaining the integrated circuit within an optimal temperature range to improve overall system efficiencies. Regarding claim 5, Yang as modified discloses the system of claim 1 (see the combination of references used in the rejection of claim 1 above), wherein the controller is arranged to apply the first polarity based on the first indication being greater than a high end of an optimal temperature range (Yang, Fig. 6; Pg. 5, paragraph 71, At block 608, the controller may output a command for a direction of the bidirectional current to cool the electronic component, for example, a positive current direction, in response to determining that T_A, the temperature of the first side (side A) of the TEE, is higher than T_B, the temperature of the second side (side B) of the TEE. In one embodiment, the self-regulated heat transfer controller may be configured to determine the current flow direction of the bidirectional current in the TEE is to be in a direction to cool the electronic component in response to determining that the temperature of the first side of the thermoelectric element is higher than the temperature of the second side of the thermoelectric element). Regarding claim 6, Yang as modified discloses the system of claim 5 (see the combination of references used in the rejection of claim 5 above), wherein the first polarity causes the first surface of the Peltier element to heat and the second surface of the Peltier element to cool (Yang, Fig. 6; Pg. 5, paragraph 71, At block 608, the controller may output a command for a direction of the bidirectional current to cool the electronic component, for example, a positive current direction, in response to determining that T_A, the temperature of the first side (side A) of the TEE, is higher than T_B, the temperature of the second side (side B) of the TEE. In one embodiment, the self-regulated heat transfer controller may be configured to determine the current flow direction of the bidirectional current in the TEE is to be in a direction to cool the electronic component in response to determining that the temperature of the first side of the thermoelectric element is higher than the temperature of the second side of the thermoelectric element). Regarding claim 8, Yang as modified discloses the system of claim 1 (see the combination of references used in the rejection of claim 1 above), wherein the controller is arranged to apply the second polarity based on the second indication being less than the lower temperature of the optimal temperature range (Yang, Fig. 6; Pg. 5, paragraph 67, At block 604, the controller may determine that the T_A is below the minimum allowable temperature and output a command for a direction of a bidirectional current to heat up the electronic component, for example, a negative current direction. The self-regulated heat transfer controller may be configured to determine a current flow direction of a bidirectional current in the TEE is to be in a direction to heat up the electronic component in response to determining that the temperature of the first side of the thermoelectric element is lower than the minimum temperature allowable for the electronic component. In one embodiment, the direction to heat up the electronic component may be the negative current direction. When the T_A is below the minimum allowable temperature, the current flow may be negative such that TEM is acting as a heat pump, to transfer heat from the ambient environment to the electronic component to heat up the electronic component. In this way, high temperature external heating source is not required to transfer heat to the component to heat up the component, thus, eliminating the need of the external heating source). Regarding claim 9, Yang as modified discloses the system of claim 8 (see the combination of references used in the rejection of claim 8 above), wherein the second polarity causes the first surface of the Peltier element to cool and the second surface of the Peltier element to heat (Yang, Fig. 6; Pg. 5, paragraph 67, At block 604, the controller may determine that the T_A is below the minimum allowable temperature and output a command for a direction of a bidirectional current to heat up the electronic component, for example, a negative current direction. The self-regulated heat transfer controller may be configured to determine a current flow direction of a bidirectional current in the TEE is to be in a direction to heat up the electronic component in response to determining that the temperature of the first side of the thermoelectric element is lower than the minimum temperature allowable for the electronic component. In one embodiment, the direction to heat up the electronic component may be the negative current direction. When the T_A is below the minimum allowable temperature, the current flow may be negative such that TEM is acting as a heat pump, to transfer heat from the ambient environment to the electronic component to heat up the electronic component. In this way, high temperature external heating source is not required to transfer heat to the component to heat up the component, thus, eliminating the need of the external heating source). Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yang as modified by Chou as applied to claim 1 above, and further in view of VanHoudt (US 20020121094), hereinafter VanHoudt. Regarding claim 2, Yang as modified discloses the system of claim 1 (see the combination of references used in the rejection of claim 1 above), wherein the Peltier element comprises a first terminal and a second terminal, the first polarity or the second polarity applied across the first terminal and the second terminal (Yang, Fig. 1, electrical circuit 104; Pg. 3, paragraph 39, The thermoelectric element 102 itself may be connected to the external electrical circuit 104 for a current control purpose; Pg. 4, paragraph 51, When the first switch and the third switch are turned on while the second switch and fourth switch are turned off, the current flow direction in a first direction, and wherein when the second switch and the fourth switch are turned on while the first switch and the third switch are turned off, the current flow direction is in a second direction opposite to the first direction). However, Yang as modified does not disclose the first terminal and the second terminal are coupled to the first surface and the second surface of the Peltier element respectively. VanHoudt teaches the first terminal and the second terminal are coupled to the first surface and the second surface of the Peltier element respectively (Fig. 1, thermoelectric device 104, first electrical junction contact 106, second electrical junction contact 108, electrical line 120, electrical line 122; Pg. 3, paragraph 33, System 100 further comprises a switch-mode DC power supply 112 and a polarity controller 114 for controlling the direction of electrical current flow through Peltier junction 110. DC power supply 112 is electrically connected to first junction contact 106 and to second junction contact 108 so that it may provide pulse-modulated DC current through Peltier junction 110). Yang as modified fails to teach the first terminal and the second terminal are coupled to the first surface and the second surface of the Peltier element respectively, however VanHoudt teaches that it is a known method in the art of thermoelectric temperature control to include the first terminal and the second terminal are coupled to the first surface and the second surface of the Peltier element. This is strong evidence that modifying Yang as modified as claimed would produce predictable results (i.e. providing electrical flow through the Peltier element). Accordingly, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yang as modified by VanHoudt and arrive at the claimed invention since all claimed elements were known in the art and one having ordinary skill in the art could have combined the elements as claimed by known methods with no changes in their respective functions and the combination would have yielded the predictable result of providing electrical flow through the Peltier element. Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yang as modified by Ramirez as applied to claim 1 above, and further in view of Barnard et al. (WO 207080418), hereinafter Barnard. Regarding claim 3, Yang as modified discloses the system of claim 1 (see the combination of references used in the rejection of claim 1 above), wherein the controller comprises a processor and is coupled to a first voltage shifter and a second voltage shifter, a first terminal is coupled to the first voltage shifter and a second terminal is coupled to the second voltage shifter (Yang, Fig. 1, electrical circuit 104; Fig. 3, polarity change circuit 302, transistors Q3 303, Q4 304, Q5 305, and Q6 30; Pg. 3, paragraph 39, The thermoelectric element 102 itself may be connected to the external electrical circuit 104 for a current control purpose; Pg. 3, paragraph 43, The circuit 104 may include a buck-boost converter 301 and a polarity change circuit 302 (also referred to as polarity switching circuit); Pg. 3, paragraph 48, Referring to FIG. 3, the polarity change circuit 302 is configured to change a current flow direction of the bidirectional current 110 in the TEE 102. A set of transistors Q3 303, Q4 304, Q5 305 and Q6 305 may come in as a group of switches to form the polarity change circuit 302; Pg. 4, paragraph 51, The controller may control the switches' duty cycles based on the temperature data obtained from one or more temperature sensors coupled to the electronic components (e.g., processor) or coupled to different sides of TEE element 102. Based on the temperature, the control may turn on or off some of the switches to control the current flow direction of a current flowing through TEE 102, which enables the TEE 102 to operate in a cooling mode or a heating mode; Pg. 4, paragraph 51, When the first switch and the third switch are turned on while the second switch and fourth switch are turned off, the current flow direction in a first direction, and wherein when the second switch and the fourth switch are turned on while the first switch and the third switch are turned off, the current flow direction is in a second direction opposite to the first direction). However, Yang as modified does not disclose wherein a first general purpose input output (GPIO) pin of a processor of the controller is directly connected to a first voltage shifter and a second GPIO pin of the processor of the controller is directly connected to a second voltage shifter, the first terminal of the Peltier element is directly connected to an output of the first voltage shifter and the second terminal of the Peltier element is directly connected to an output of the second voltage shifter, wherein the first GPIO pin outputs a first logic signal to cause the first voltage shifter to only output one a voltage level and ground to the first terminal and the second GPIO pin outputs a second logic signal to cause the second voltage shifter to only output the voltage level and the ground to the second terminal to cause the first polarity or the second polarity to be applied to the Peltier element, wherein one of the voltage shifter outputs the voltage level and another of the voltage shifter outputs the ground to cause the first polarity or the second polarity to be applied to the Peltier element. Barnard teaches wherein a first general purpose input output (GPIO) pin of a processor of the controller is directly connected to a first voltage shifter and a second GPIO pin of the processor of the controller is directly connected to a second voltage shifter, the first terminal of the Peltier element is directly connected to an output of the first voltage shifter and the second terminal of the Peltier element is directly connected to an output of the second voltage shifter, wherein the first GPIO pin outputs a first logic signal to cause the first voltage shifter to only output one a voltage level and ground to the first terminal and the second GPIO pin outputs a second logic signal to cause the second voltage shifter to only output the voltage level and the ground to the second terminal to cause the first polarity or the second polarity to be applied to the Peltier element, wherein one of the voltage shifter outputs the voltage level and another of the voltage shifter outputs the ground to cause the first polarity or the second polarity to be applied to the Peltier element (See annotated Fig. 2 of Barnard below, first general purpose input output (GPIO) pin 118a of controller 118 is directly connected to DAC 120 and a second GPIO pin 118b of the processor of the controller is directly connected DAC 122; Pg. 7-8, In order to control the direction of the current through the TEC 102, the microprocessor 118 determines which MOSFETs of the H-bridge need to be activated. Digital signals are sent to the DACs 120 and 122, which produce corresponding analogue voltage levels. The output of the DAG 120 is applied to the gates of the MOSFETs 104 and 108, and the output of the DAG 122 is applied to the gates of the MOSFETs 106 and 110. These signals switch the MOSFETs on or off in order to set the direction of current through the TEC 102. For a given gate signal from PAC 120, the NMOS 104 and the PMOS 108 will be in opposite on and off states, and likewise for a given signal from DAG 122, the NIVIOS 106 and PMOS 110 will also be .in opposite on and off states). Yang as modified fails to teach wherein a first general purpose input output (GPIO) pin of a processor of the controller is directly connected to a first voltage shifter and a second GPIO pin of the processor of the controller is directly connected to a second voltage shifter, the first terminal of the Peltier element is directly connected to an output of the first voltage shifter and the second terminal of the Peltier element is directly connected to an output of the second voltage shifter, wherein the first GPIO pin outputs a first logic signal to cause the first voltage shifter to only output one a voltage level and ground to the first terminal and the second GPIO pin outputs a second logic signal to cause the second voltage shifter to only output the voltage level and the ground to the second terminal to cause the first polarity or the second polarity to be applied to the Peltier element, wherein one of the voltage shifter outputs the voltage level and another of the voltage shifter outputs the ground to cause the first polarity or the second polarity to be applied to the Peltier element, however Barnard teaches that it is a known method in the art of power circuits for Peltier elements to include wherein a first general purpose input output (GPIO) pin of a processor of the controller is directly connected to a first voltage shifter and a second GPIO pin of the processor of the controller is directly connected to a second voltage shifter, the first terminal of the Peltier element is directly connected to an output of the first voltage shifter and the second terminal of the Peltier element is directly connected to an output of the second voltage shifter, wherein the first GPIO pin outputs a first logic signal to cause the first voltage shifter to only output one a voltage level and ground to the first terminal and the second GPIO pin outputs a second logic signal to cause the second voltage shifter to only output the voltage level and the ground to the second terminal to cause the first polarity or the second polarity to be applied to the Peltier element, wherein one of the voltage shifter outputs the voltage level and another of the voltage shifter outputs the ground to cause the first polarity or the second polarity to be applied to the Peltier element. This is strong evidence that modifying Yang as modified as claimed would produce predictable results (i.e. providing voltage and polarity control to ensure efficient operation of the Peltier element). Accordingly, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yang as modified by Barnard and arrive at the claimed invention since all claimed elements were known in the art and one having ordinary skill in the art could have combined the elements as claimed by known methods with no changes in their respective functions and the combination would have yielded the predictable result of providing voltage and polarity control to ensure efficient operation of the Peltier element. Regarding claim 4, Yang as modified discloses the system of claim 3 (see the combination of references used in the rejection of claim 1 above), wherein the first voltage shifter is arranged to output a greater voltage than the second voltage shifter to apply the first polarity and the first voltage shifter is arranged to output a voltage less than the second voltage shifter to apply the second polarity (Yang, Fig. 4, flow diagram 400, blocks 401-405; Pg. 3-4, paragraph 49-50, To have a negative current, which is a reverse polarity of the input voltage and current, the switch Q3 303 and the switch Q5 305 may be turned on while the switch Q4 304 and the switch Q6 306 may be turned off. Thus, a current may be flowing from the converter positive output to the switch Q3 303, then a load (the TEE 102), then the switch Q5 305, then back to the converter negative output (e.g., the node coupled to the anode of diode D1). The current flow direction of the bidirectional current 110 in the TEE 102 may be in a negative direction in this case. To have a positive current, the switch Q4 304 and the switch Q6 306 may be turned on while the switch Q3 303 and the switch Q5 305 may be off. The current direction of the bidirectional current 110 in the TEE 102 may be reversed compared to the negative current setting. The current may be flowing from the converter positive output to the switch Q4 304, then the load (the TEE 102), then the switch Q6 306, then back to the converter negative output. The current flow direction of the bidirectional current 110 in the TEE 102 may be in a positive direction in this case; Pg. 5, paragraph 54, FIG. 4 is a flow diagram 400 illustrating a control of a polarity change of an electrical circuit of a cooling and heating system according to some embodiments. The electrical circuit may be the electrical circuit 104 in the cooling and heating system 100 in FIG. 1. As illustrated in FIG. 4, at 401, the system may be started; Pg. 5, paragraph 57-58, At block 404, in response to determining that the negative current is needed, the switch Q3 303 and the switch Q5 305 are turned on while the switch Q4 304 and the switch Q6 306 are turned off. Thus, a current flow direction of the bidirectional current 110 in the TEE 102 is in a negative direction. At block 405, in response to determining that the negative current is not needed, the switch Q4 304 and the switch Q6 306 are turned on while the switch Q3 303 and the switch Q5 305 are turned off. Thus, a current flow direction of the bidirectional current 110 in the TEE 102 is in a positive direction). Claims 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yang as modified by Chou as applied to claims 6 and 9 above, respectively and further in view of Suski et al. (US Patent No. 5,419,780), hereinafter Suski. Regarding claim 7, Yang as modified discloses the system of claim 6 (see the combination of references used in the rejection of claim 6 above). However, Yang as modified does not disclose further comprising a fan arranged to draw heat from heatsink fins of the heatsink when the fan is enabled. Suski teaches further comprising a fan arranged to draw heat from heatsink fins of the heatsink when the fan is enabled (Fig. 3, fan 70; Col. 5-6, lines 63-68 and 1-12, As schematically illustrated in FIG. 5, the thermoelectric generator 50 is electrically connected to the fan 70 via a pair of wires 72 so that the voltage and current generated by the thermoelectric generator 50 is conducted to the fan 70. In operation, when the temperature of the integrated circuit 12 rises, a temperature differential ΔT develops across the thermoelectric generator 50 between the integrated circuit 12 and the heatsink 60. When the temperature differential ΔT reaches a sufficient magnitude (e.g., 50 degrees Centigrade), the voltage and current generated by the thermoelectric generator 50 is sufficient to cause the fan 70 to operate. The operation of the fan 70 causes airflow across the fins 64 of the heatsink 60 which reduces the temperature of the heatsink 60 thus causing more heat to be drawn away from the integrated circuit 12 to thereby reduce the temperature of the integrated circuit 12). Therefore, it would have been obvious before the effective filing date of the claimed invention to modify the system of Yang as modified to include a fan arranged to draw heat from heatsink fins of the heatsink when the fan is enabled as taught by Suski. One of ordinary skill in the art would have been motivated to make this modification to provide increased cooling capacity to the heat sink to improve overall system efficiencies. Regarding claim 10, Yang as modified discloses the system of claim 9 (see the combination of references used in the rejection of claim 9 above). However, Yang as modified does not disclose comprising a fan arranged to draw heat from heatsink fins. Suski teaches further comprising a fan arranged to draw heat from heatsink fins (Fig. 3, fan 70; Col. 5-6, lines 63-68 and 1-12, As schematically illustrated in FIG. 5, the thermoelectric generator 50 is electrically connected to the fan 70 via a pair of wires 72 so that the voltage and current generated by the thermoelectric generator 50 is conducted to the fan 70. In operation, when the temperature of the integrated circuit 12 rises, a temperature differential ΔT develops across the thermoelectric generator 50 between the integrated circuit 12 and the heatsink 60. When the temperature differential ΔT reaches a sufficient magnitude (e.g., 50 degrees Centigrade), the voltage and current generated by the thermoelectric generator 50 is sufficient to cause the fan 70 to operate. The operation of the fan 70 causes airflow across the fins 64 of the heatsink 60 which reduces the temperature of the heatsink 60 thus causing more heat to be drawn away from the integrated circuit 12 to thereby reduce the temperature of the integrated circuit 12). Therefore, it would have been obvious before the effective filing date of the claimed invention to modify the system of Yang as modified to include comprising a fan arranged to draw heat from heatsink fins as taught by Suski. One of ordinary skill in the art would have been motivated to make this modification to provide increased cooling capacity to the heat sink to improve overall system efficiencies. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yang as modified by Chou as applied to claim 1 above, and further in view of Rangarajan et al. (US 9,297,559), hereinafter Rangarajan. Regarding claim 11, Yang as modified discloses the system of claim 1 (see the combination of references used in the rejection of claim 1 above). However, Yang as modified does not disclose wherein at least a portion of circuitry of the controller is located in the integrated circuit. Rangarajan teaches disposing wherein at least a portion of circuitry of the controller is located in the integrated circuit (Fig. 1A, processor 110, package 118, TEC controller 120, thermoelectric cooling (TEC) device 130; Col. 3, lines 1-3, In some embodiments, the processor 110 may be mounted on or within a package 118). Yang as modified fails to teach wherein at least a portion of circuitry of the controller is located in the integrated circuit, however Rangarajan teaches that it is a known method in the art of thermoelectric temperature control to include wherein at least a portion of circuitry of the controller is located in the integrated circuit. This is strong evidence that modifying Yang as modified as claimed would produce predictable results (i.e. providing cooling to circuitry of the controller). Accordingly, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yang as modified by Rangarajan and arrive at the claimed invention since all claimed elements were known in the art and one having ordinary skill in the art could have combined the elements as claimed by known methods with no changes in their respective functions and the combination would have yielded the predictable result of providing cooling to circuitry of the controller. Response to Arguments Applicant's arguments filed May 13th, 2026 have been fully considered but they are not persuasive. Applicant argues on Pg. 7 (as numbered by Applicant) of the remarks, “The Office also objects to claim 3 on the basis that lines 1-6 which recite, "wherein a first general purpose input output (GPIO) pin of a processor of the controller is directly connected to a first voltage shifter and a second GPIO pin of the processor of the controller is directly connected to a second voltage shifter, the first terminal of the Peltier element is directly connected to an output of the first voltage shifter and a second terminal of the Peltier element is directly connected to an output of the second voltage shifter" are not supported by the disclosure. The Office contends that although, Figures 3-6 depict GPIOm and GPIOn of MCU 302 to be connected to voltage shifter 304 and voltage shifter 306 via inputs 310 and voltage shifter 304 and voltage shifter 306 to be connected to terminals 126 and 128 of Peltier element 114 via outputs 312, the drawings are not detailed schematics showing all of the electrical connections between components of the controller 136 and cannot be solely relied upon to support direct connections of the electrical components of the system. Applicant respectfully submits that one skilled in the art would understand the drawings are not detailed schematics that necessarily enumerates every physical interconnect detail and instead focus on illustrating functional relationships. With this understanding, a "direct connection" denotes the absence of intervening control logic, not the absence of ordinary interface circuitry that may be omitted from a block diagram for clarity. The drawings depict components interacting without intervening control blocks, which reasonably conveys possession of a direct connection as claimed. Withdrawal of the rejection of claim 3 is respectfully requested.” However, this argument is not persuasive as the Examiner maintains the drawings are not detailed schematics showing all of the electrical connections between components of the controller 136 and cannot be solely relied upon to support direct connections of the electrical components of the system. Further, the Examiner disagrees with the Applicant’s newly presented interpretation of “direct connection” as the Applicant’s proposed interpretation of “direct connection” to mean “the absence of intervening control logic, not the absence of ordinary interface circuitry that may be omitted from a block diagram for clarity” is far more broad and inclusive of additional intervening components than what a PHOSITA would interpret from “directly connected”. The Examiner maintains the 35 U.S.C 112(a) rejection for at least the reasons described herein. Applicant’s arguments with respect to claims 1 and 3 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The rejection of independent claim 1 is maintained. The rejections of dependent claims 2-11 are also maintained for at least the reasons described herein. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chaparro Monferrer et al. (US Patent No. 8,209,989) discloses a system that includes a Peltier element and sensors for monitoring and controlling temperature of a integrated circuit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVON T MOORE whose telephone number is 571-272-6555. The examiner can normally be reached M-F, 7:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Frantz Jules can be reached at 571-272-6681. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DEVON MOORE/Examiner, Art Unit 3763 June 08th, 2026
Read full office action

Prosecution Timeline

Nov 01, 2023
Application Filed
Nov 20, 2025
Non-Final Rejection mailed — §103, §112
Feb 19, 2026
Response Filed
Mar 18, 2026
Final Rejection mailed — §103, §112
May 13, 2026
Request for Continued Examination
May 19, 2026
Response after Non-Final Action
Jul 09, 2026
Non-Final Rejection mailed — §103, §112 (current)

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3-4
Expected OA Rounds
47%
Grant Probability
80%
With Interview (+32.7%)
3y 1m (~4m remaining)
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