DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. S tatus of C laims Claims 1 - 29 are pending. Claims 1 and 15 are independent apparatus and method claims, respectively. Claim 29 is an independent wireless device claim. Claims 2 - 14 and 16 - 28 are dependent. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 13 - 15, and 27 - 29 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Watanabe (US 2002/0070809 A1 , cited by the applicant ). Claim 1 recites an amplifier comprising: (a) an active path coupled between an input node and an output node, the active path comprising a first transistor coupled to the input node and a first inductive element coupled between the first transistor and the output node; and (b) a bypass path coupled between the input node and the output node, the bypass path comprising the first inductive element. Watanabe discloses each limitation of claim 1. Watanabe describes a low noise amplifier 10 (the "amplifier") having an amplifier mode and a bypass mode. (Abstract; § 0001; Fig. 1.) . Fig. 1 of Watanabe reproduced for ease of reference. The active path of claim 1 corresponds to the signal path in Watanabe's amplifier mode running from input terminal 12 (the "input node") through transistor 40 (the "first transistor") — which is coupled to the base/input terminal 12 via impedance matching circuit 14 — and continuing through impedance matching circuit 44, which includes inductor 46 (the "first inductive element") shunt-coupled between the collector of transistor 40 and the output terminal 50 (the "output node"). ( § 0007 –[ 0008; § 0012–[0013; Fig. 1) . The first inductive element (inductor 46) is coupled between the first transistor 40 and the output node 50 because inductor 46 has a first terminal connected to the collector of transistor 40 (via the input of impedance matching circuit 44) and is shunted to VCC, while capacitor 48 connects that same node to output terminal 50. Inductor 46 and capacitor 48 together form the output matching network that delivers the amplified signal to output terminal 50. ( § 0012; Fig. 1) . The bypass path of claim 1 corresponds to Watanabe's bypass circuit 22, which is coupled between the input terminal 12 (input node) and the collector of transistor 40, which is coupled through the output impedance matching circuit 44 to output terminal 50 (output node). Because inductor 46 sits at the common output node shared by both the active path and the bypass path, inductor 46 constitutes the shared "first inductive element" recited by claim 1 as forming part of the bypass path. (¶ [0010 –[ 0011; § 0014–[0016; Fig. 1.) Accordingly, Watanabe anticipates every limitation of claim 1 under § 102(a)(1). Claim 13 depends on claim 1 and further recites "wherein the active path comprises a capacitive element coupled between the first inductive element and the output node." Watanabe discloses capacitor 48 explicitly coupled between the input of impedance matching circuit 44 (i.e., the node where inductor 46 is connected, which is identified herein as the "first inductive element") and output terminal 50 (the "output node"). ( § 0012; Fig. 1.) Capacitor 48 is a discrete capacitive element that sits in the active path between inductor 46 and the output. Accordingly, this limitation is disclosed by Watanabe. Claim 14 depends on claim 1 and further recites "a second inductive element coupled between the input node and a gate of the first transistor." Watanabe discloses impedance matching circuit 14 coupled between input terminal 12 (the "input node") and the base (gate equivalent for a BJT) of transistor 40 (the "first transistor"). Impedance matching circuit 14 comprises inductor 16 having a first terminal connected to the input and a second terminal connected to the output of impedance matching circuit 14, which feeds the base of transistor 40. ( § 0008; Fig. 1.) Inductor 16 thus constitutes the "second inductive element coupled between the input node and a gate of the first transistor." Accordingly, this limitation is disclosed by Watanabe. Claim 15 is an independent method claim reciting: receiving a signal at an input node; amplifying via an active path comprising a first transistor and a first inductive element; and activating a bypass path comprising the first inductive element. Watanabe explicitly discloses both an amplifier mode and a bypass mode of operation for LNA 10. In the amplifier mode, signal SIN is received at input terminal 12 (input node), amplified by transistor 40 (first transistor), and passed through impedance matching circuit 44 including inductor 46 (first inductive element) to output terminal 50. ( § 0013; Fig. 1.) In the bypass mode, the bypass circuit 22 is activated to transfer signal SIN from the input terminal to the output terminal, sharing the output path through inductor 46. ( § 0014; Fig. 1.) These modes correspond precisely to the "amplifying" and "activating a bypass path" steps of claim 15. Watanabe therefore anticipates every limitation of claim 15. Claim 27 depends on claim 15 and recites "further comprising adjusting a capacitance of a capacitive element of the active path coupled between the first inductive element and the output node." Watanabe discloses capacitor 48 in the active path coupled between inductor 46 (first inductive element) and output terminal 50. ( § 0012; Fig. 1.) To the extent claim 27 requires adjustment of the capacitance value, it is noted that Watanabe teaches selecting values for capacitor 48 to achieve a target output impedance ( § 0012), which constitutes design-phase adjustment. Moreover, as set forth in the § 103 rejection below, adjustable/variable capacitors in this role were well known in the art and would have been obvious to the skilled person. Claim 27 is therefore anticipated by or at least rendered obvious by Watanabe. Claim 28 depends on claim 15 and recites "wherein the amplifier further comprises a second inductive element coupled between the input node and a gate of the first transistor." This is the method counterpart of apparatus claim 14. For the same reasons set forth with respect to claim 14, Watanabe's inductor 16 coupled between input terminal 12 and the base of transistor 40 discloses this limitation. ( § 0008; Fig. 1.) Accordingly, claim 28 is anticipated by Watanabe. Claim 29 recites a wireless device comprising one or more antennas and a low-noise amplifier (LNA) having an active path and a bypass path, both sharing an inductive element — essentially the same combination of elements as claim 1 in a wireless device context. Watanabe discloses that LNA 10 is used in a radio frequency (RF) context where an RF signal received through an antenna is amplified prior to passing to a mixer for frequency conversion ( § 0002) . The wireless device comprising an antenna and an LNA meeting all the structural limitations of claim 1 is therefore implicitly disclosed by Watanabe. As a practical matter, an LNA operating on signals received "through an antenna" at 900 MHz to 5 GHz inherently implies a wireless device with antennas. Accordingly, claim 29 is anticipated by Watanabe. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 2 and 16 are rejected under 35 U.S.C. § 103 as being unpatentable over Watanabe in view of Seshita et al. ( US 2020/0382080 A 1 ) . Claims 2 and 16 Claim 2 depends on claim 1 and recites "wherein the active path further comprises a second transistor coupled in cascode with the first transistor and wherein the first inductive element is coupled between the second transistor and the output node." Claim 16 is the method counterpart, depending on claim 15. Watanabe anticipates the base amplifier structure as discussed in regarding claim 1 . Watanabe does not explicitly disclose a cascode second transistor in the active path. Seshita discloses a low noise amplifier comprising an amplifying circuit 501 with a cascode transistor arrangement ( Seshita , Fig. 1; § 008 7 ) . Seshita thus teaches using a second transistor coupled in cascode with the first transistor in an LNA active path. Cascoded transistors in the amplifying path of an LNA is a common design choice and WO2024055759, US20250309835, US20240372512, US20230023111, US20210217713 are only few examples of prior arts teaches LNA with cascoded transistors in the amplifying path. It would have been obvious to a Person of Ordinary Skill in The Art ( POSITA ) to incorporate Seshita 's well-known cascode transistor arrangement into the Watanabe LNA to improve gain , reduce the Miller effect , and increase the reverse isolation of the amplifier , as well as increase the breakdown voltage — all standard and well-documented benefits of cascode LNA design that were universally known in the RF circuit design art. The combination requires only routine skill and yields entirely predictable results. Claim 16 is a Method Counterpart of claim 2 : Claims 16 is a method claim depending on independent method claim 15. Claim 16 recite s the method counterpart to apparatus claim 2. Therefore, the same prior art analysis and reasoning set forth above with respect to the corresponding apparatus claim (claim 2 ) applies with equal force to the method claim. A method of operating an apparatus is not separately patentable where the apparatus itself is unpatentable, when the method steps are simply the natural operation of that apparatus. See MPEP § 2181. Please note, in following rejections of claims 3-12 the same argument of respective method counterparts 17-26 would be equally applicable. Claims 3 - 8, 10-12 and 17 - 2 2, 24-26 are r ejected under § 103 over Watanabe in view of Wang (US 2017/0201218 A1). Claim 3 depends on claim 1 and recites "further comprising a second inductive element coupled to the first inductive element, wherein a tap between the first inductive element and the second inductive element is coupled to the output node." Claim 17 is the method counterpart. Watanabe discloses the first inductive element (46) at the output of the active path. Watanabe does not explicitly disclose a series-connected second inductive element with a tap to the output node. Wang discloses, in Fig. 5 in the output load and matching network of its LNA (552A or 552B) , an inductive load ( L1 A -L2 A or L1B-L2B) that can be implemented as two inductors connected in series with a tap between them driving the output node. ( Wang , Fig. 5 ) This tapped-inductor configuration is a standard technique for impedance matching in LNA output stages and was well-known in the art. A POSITA would have been motivated to implement Watanabe's output impedance matching circuit 44 using the tapped inductor arrangement taught by Wang to improve impedance matching flexibility and bandwidth. The combination is straightforward and produces predictable results. Claim 4 depends on claim 3 and recites "further comprising a capacitive element coupled in parallel with a series combination of the first inductive element and the second inductive element." Claim 18 is the method counterpart. As established above, the combination of Wa ta nabe and Wang renders claim 3 obvious. Wang further discloses a capacitive element (C1A or C1B respectively with L1A-L2A or L1B-L2B ) and coupled in parallel with the inductive load in an LNA output impedance matching circuit, forming an LC tank circuit. (Wang, Fig. 5; § 0044) Placing a capacitive element in parallel with the inductor combination to form a resonant matching network is a fundamental and ubiquitous technique in RF LNA design. A POSITA would have been motivated to add Wang's parallel capacitor to the Watanabe/Okayama tapped-inductor arrangement to create a tunable LC matching network at the LNA output, enabling improved impedance matching over a broader frequency range. The motivation, the technique, and the result were all well-known. Accordingly, claims 4 and 18 are unpatentable under § 103. Claim 5 depends on claim 4 and recites "wherein the capacitive element is a variable capacitive element and wherein the variable capacitive element, the first inductive element, and the second inductive element form an impedance matching circuit for the active path." Claim 19 is the method counterpart, which additionally recites "tuning the impedance matching circuit by adjusting a capacitance of the variable capacitive element." The combination of Watanabe and Wang teaches the LC matching circuit at the output. Wang further discloses that the capacitive element in the parallel matching circuit can be a variable capacitor (varactor), enabling the resonant frequency of the matching network to be tuned by adjusting the capacitance value. (Wang, Fig. 5; § 0044) . Claim s 6 depends on claim 3 and recites "wherein the bypass path further comprises a third inductive element coupled to the first inductive element." Claim 20 is the method counterpart. Watanabe discloses bypass circuit 22 with inductors 28 and 34 used for impedance matching within the bypass path. ( § 0011; § 0015; Fig. 1 ). In broadest reasonable interpretation of the term couple means connection, and as such this the inductor 34 on the bypass path is coupled to the first inductor 46 (i.e. connected to this inductor through switch 26 and capacitor 38 (Fig. 1). Claim 7 depends on claim 6 and recites "wherein the bypass path further comprises a capacitive element coupled between a gate of the first transistor and the second inductive element." Claim 21 is the method counterpart. Watanabe discloses bypass circuit 22 which includes capacitor 38 . ( § 0011; § 0015; Fig. 1 ). In broadest reasonable interpretation of the term couple means connection, and as such this the inductor 34 on the bypass path is coupled to the first inductor 46 (i.e. connected to this inductor through switch 26 and capacitor 38 (Fig. 1). Evidently this capacitor (38) can be considered as decoupling the gate of the first transistor 40 from the supply voltage V CC , while connected in bypass configuration. The use of a series capacitor in the bypass path for DC blocking and AC coupling is a standard and expected circuit design technique in LNA bypass paths. Claim 8 depends on claim 7 and recites "wherein the bypass path further comprises a first switch coupled between the gate of the first transistor and the capacitive element." Claim 22 is the method counterpart. Watanabe teaches transistors 24 and 26 as switching elements in its bypass circuit 22 that are turned on and off by the BYPASS control signal to enable or disable the bypass path. ( § 0010– § 0011; § 0014; Fig. 1 ). Claim s 10 -12 depends on claim 6 and recites "wherein the third inductive element is magnetically coupled with each of the first inductive element and the second inductive element." Claim 11 depends on claim 10 and recites that a first portion of the first inductive element is interleaved with a first portion of the second inductive element, and a second portion of the first inductive element is interleaved with a second portion of the second inductive element. Claim 12 depends on claim 11 and specifies that the first portions are on a first layer of an integrated circuit and the second portions are on a second layer of the IC. The combination of Watanabe and Wang teaches the amplifier structure with multiple inductive elements in the active path and the bypass path. Wang discloses output load and matching circuit implementations for LNAs comprising multiple inductors that are physically proximate and arranged on an integrated circuit. (Wang, Fig. 5; § 0044) Wang's disclosure of multi-layer, proximate inductor implementations on IC technology renders this aspect of the claims obvious. The magnetic coupling of adjacent inductors on integrated circuits being inherent physical phenomenon , if not special arrangement to isolate them are in place, that has been extensively documented and exploited in IC inductor design to favor to optimize inductance values as shown explicitly by Wang . The use of magnetically coupled inductors — including interleaved inductor layouts on multiple metal layers — to reduce the effective inductance and thus decrease the chip area required for a given inductance value is a well-known and widely published design technique in RF integrated circuit design. A POSITA would have known that placing inductor windings in close proximity or interleaving them on different IC layers creates mutual magnetic coupling and would have known how to design such inductors to achieve a desired effective inductance with reduced area. The combination of Watanabe's LNA architecture, Wagner’ s multi-inductive-element with magnetic coupling as IC inductor implementation techniques renders claims 10–12 obvious. The objective problem of reducing chip area is a standard and well-recognized design objective. A POSITA seeking to reduce the area occupied by the inductive elements of the amplifier would have been motivated to implement the inductors in an interleaved, magnetically coupled configuration as a matter of routine IC design optimization. The result — reduced inductance and reduced area — is entirely predictable. Accordingly, claims 10, 11, and 12 are unpatentable under § 103. Claims 9 and 23 are rejected under § 103 over Watanabe in view of Wang (US 2017/0201218 A1) and further in view of the combination of MiniCircuit’s application note, “ MMIC Amplifiers with Shutdown & Bypass Features De-Mystified ”, published in NOVEMBER 2021 and Analog Devices application note AN-2558 published in 2023. Fig. 4 (left ) of MiniCircuit) and Fig. 1 (right) of AN-2558 . Claim 9 depends on claim 8 and recites: (i) a second switch in the bypass path coupled between the first switch and the capacitive element; and (ii) a third switch coupled between a reference potential node and a node between the first switch and the second switch — collectively forming a T-switch topology. Claim 23 is the method counterpart. Watanabe discloses transistors 24 and 26 as two switching elements in the bypass path. ( § 0011; Fig. 1 ). MiniCircuit in view of AN-2558 exemplarily shows a s pecific T-switch configuration recited in claim 9 — two series switches with a shunt switch to ground between them — is a standard, well-known RF switch topology that was widely used in LNA bypass paths. The T-switch is employed specifically to improve input-output isolation and to minimize capacitive coupling when the bypass path is inactive. A POSITA would have been motivated to implement the bypass path switches using a T-switch configuration, as it was standard engineering practice to use T-switches in LNA bypass paths precisely to avoid capacitive coupling and improve I/O isolation. No inventive step is required. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Enter examiner's name" \* MERGEFORMAT HAFIZUR RAHMAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0659 . The examiner can normally be reached FILLIN "Work schedule?" \* MERGEFORMAT M-F: 10-6 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1769 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HAFIZUR RAHMAN/ Primary Examiner, Art Unit 2843.