DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 6-19, and 21-22 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1, 11, and 16 recites “the count value of each selected sub-pixel ending with a same third value”, however there is no indication provided by the applicant of the disclosure that provides details of the “third value” as recited. The examiner was unable to find support of a count value of each sub-pixel ending with the same third value as recited. The only other value the disclosure provides is a “characteristic value”, however no disclosure of a count value with respects to the characteristic value is detailed. Therefore claims 2-4, 6-9, 12-15, 17-19, and 21-22 are rejected as being dependent on a rejected base claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-19, and 21-22 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1, 11, and 16 recites “the count value of each selected sub-pixel ending with a same third value”, however it is not made clear by the specification or the drawings of selected sub-pixels ending count value being a same third count value as recited. The specification details a “characteristic value”, however does not provide any description of a count value related to the characteristic value as recited. Therefore the specification does not make clear how the count value of each selected sub-pixel ends with a same third value, when each selected pixel will have a different number. Claims 2-4, 6-9, 12-15, 17-19, and 21-22 are rejected as being dependent on a rejected base claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-7, 10-13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Patent Publication No. 2023/0419910; hereinafter Lee) in view of Hayafuji (US Patent Publication No. 2006/0202913) and Staggs (US Patent No. 4,775,857).
With reference claim 1, Lee discloses display device (100) (see paragraphs 39-40; Fig. 1), comprising:
a display panel (110) comprising sub-pixels (PX) arranged thereon (see paragraph 42; Fig. 1);
a gate driver (120, 160, 170) configured to apply a scan signal (SC) to the sub-pixels (PX) (see paragraph 43; Fig. 1); and
a controller (180) configured to sense (SS) a characteristic value of the sub-pixels (PX) (see paragraphs 45, 50; Fig. 1),
wherein the controller (180) is configured to output a first clock and a second clock (off/on clock) based on a count value that increases from an initial value during a sensing period for sensing a selected sub pixel (see paragraphs 109-111, Fig. 12), and a gate driver (120, IC) is configured to generate the scan signal (SC) based on the gate clock signal (SC_CLK) (see paragraphs 43, 47; Fig. 1);
While Lee discloses the display device and further discloses the usage of a level shifter to generate a gate clock signal (SC_clock) based on the first clock and the second clock (off/on clock), however fails to specifically disclose the gate clock signal is generated at the gate driver as recited.
Hayafuji discloses a device and method for driving wherein a level shifter (6b) is included within the gate driver (6) to provide necessary signals to the display panel (see paragraphs 47-49; Fig. 5).
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to allow the usage of a gate driver having a level shifter similar to that which is taught by Hayafuji to thereby provide a gate driver capable of generating clock signals similar to that which is taught by Lee thereby providing an alternative configuration as well known in the art.
Further while teaching generation of necessary clock signals for driving the display panel Lee and Hayafuji fail to disclose count values for applying signals to pixels of the display as recited.
Staggs discloses a display apparatus for displaying video wherein the controller is configured to determine the initial value of the count value to be a first value based on the selected sub-pixel is on a same pixel line as a previously sensed sub-pixel and to determine the initial value of the count value to be a second value based on the selected sub-pixel is on a different pixel line from the previously sensed sub-pixel, the first value greater than the second value (see column 6, line 17-column 7, line 11; Fig. 5), [and] the count value of each selected sub-pixel ending with a same third value (in teaching the same ending count value at the detection of end-of-line; column 6, lines 50-60; Fig. 5).
Therefore it would have been obvious to allow the usage of a count value by the controller to determine the next line to be displayed similar to that which is taught by Staggs to be carried out in a display device similar to that which is taught by Lee and Hayafuji to thereby produce the required clocking signals for the video display generator (see Staggs; column 2, lines 61-66).
With reference to claim 2, Lee, Hayafuji, and Staggs disclose the display device of claim 1, wherein Lee further discloses wherein the controller is configured to output the first clock in response to the count value reaching a first reference count value and to output the second clock in response to the count value reaching a second reference count value (in teaching outputting SC_CLK1 in response to the over current count in the kickoff/on mode; see paragraphs 117-118, 123-124; Figs. 12-14).
With reference to claim 3, Lee, Hayafuji, and Staggs disclose the display device of claim 2, wherein Lee further discloses wherein the controller is configured to generate the gate clock signal (SC_CLK) that has a rising edge aligned with a rising edge of the first clock (SC_ON_CLK) and has a falling edge aligned with a falling edge of the second clock (SC_OFF_CLK) (see paragraphs 72-73; Fig. 4).
With reference to claim 6, Lee, Hayafuji, and Staggs, disclose the display device of claim 1, wherein Staggs further discloses that the controller sets the initial value of the count value to the first reference count value in response to the selected sub-pixel being on the same pixel line as the previously sensed sub-pixel (see column 6, line 17-column 7, line 11; Fig. 5).
With reference to claim 7, Lee, Hayafuji, and Staggs disclose the display device of claim 5, wherein Staggs further discloses that the controller is configured to initialize the count value to obtain the initial value in response to the selected sub-pixels not being on the same pixel line as the previously sensed sub-pixel (see column 6, line 17-column 7, line 11; Fig. 5).
With reference to claim 10, Lee, Hayafuji, and Staggs disclose the display device of claim 1, wherein the controller is configured to sense the characteristic value of the sub-pixels in response to a power-on signal (see paragraph 68; Figs. 1, 3).
With reference to claim 11, Lee discloses a driving method of a display device (100) including a display panel (110) on which sub-pixels (PX) are arranged (see paragraph 42; Fig. 1), a gate driver (120, 160, 170) for applying a scan signal (SC) to the sub-pixels (PX) (see paragraph 43; Fig. 1), and a controller (180) for sensing a characteristic value of the sub-pixels (PX) (see paragraphs 45, 50; Fig. 1), the method comprising:
increasing, by the controller, a count value from an initial value during a sensing period for sensing a selected sub-pixel (see paragraphs 1109-111; Fig. 12);
outputting a first clock (SC_CLK_I) in response to the count value reaching a first reference count value (IL4) (see paragraph 111; Figs. 12, 14);
outputting a second clock (SC_CLK_I) in response to the count value reaching a second reference count value (IL5) greater than the first reference count value (IL4) (paragraphs 117-119; Fig. 14).
While Lee discloses the display device and further discloses the usage of a level shifter to generate a gate clock signal (SC_clock) based on the first clock and the second clock (off/on clock), however fails to specifically disclose the gate clock signal is generated at the gate driver as recited.
Hayafuji discloses a device and method for driving wherein a level shifter (6b) is included within the gate driver (6) to provide necessary signals to the display panel (see paragraphs 47-49; Fig. 5).
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to allow the usage of a gate driver having a level shifter similar to that which is taught by Hayafuji to thereby provide a gate driver capable of generating clock signals similar to that which is taught by Lee thereby providing an alternative configuration as well known in the art.
Further while teaching generation of necessary clock signals for driving the display panel Lee and Hayafuji fail to disclose count values for applagin signals to pixels of the display as recited.
Staggs discloses a display apparatus for displaying video wherein the initial value of the count value is determined by the controller to be a first value based on the selected sub-pixel is on a same pixel line as previously sensed sub-pixel and to be a second value based on the selected sub-pixel is on a different pixel line from the previously sensed sub-pixel, the first value greater than the second value (see column 6, line 17-column 7, line 11; Fig. 5), [and] the count value of each selected sub-pixel ending with a same third value (in teaching the same ending count value at the detection of end-of-line; column 6, lines 50-60; Fig. 5).
Therefore it would have been obvious to allow the usage of a count value by the controller to determine the next line to be displayed similar to that which is taught by Staggs to be carried out in a display device similar to that which is taught by Lee and Hayafuji to thereby produce the required clocking signals for the video display generator (see Staggs; column 2, lines 61-66).
With reference to claim 12, Lee, Hayafuji, and Staggs disclose the display device of claim 11, wherein Staggs further discloses wherein the determining, before the increasing the count value, whether the selected sub-pixel is on a same pixel line as the previously sensed sub-pixel; and setting the first value of the initial value of the count value to the first reference count value in response to the selected sub-pixel being on the same pixel line as the previously sensed sub-pixel (see column 6, line 17-column 7, line 11; Fig. 5).
With reference to claim 13, Lee, Hayafuji, and Staggs disclose the display device of claim 12, wherein Staggs further discloses initializing the count value to obtain the second value of the initial value in response to the selected sub-pixel being not on the same pixel line as the previously sensed sub-pixel (see column 6, line 17-column 7, line 11; Fig. 5).
With reference to claim 15, Lee, Hayafuji, and Staggs disclose the display device of claim 11, wherein Lee further discloses that the sensing of the characteristic value of the sub-pixels is performed in response to a power-on signal (see paragraph 68; Figs. 1, 3).
Claims 4, 8-9, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Hayafuji, and Staggs as applied to claim 1 or 11 above, and further in view of Jeon et al. (US Patent Publication No. 2020/0243007; hereinafter Jeon).
With reference to claim 4, Lee, Hayafuji, and Staggs disclose the display device of claim 2, however fails to disclose sensing the sub-pixels as recited.
Jeon discloses a display device including a display panel (110), a gate driver (150), a sensing unit (120) and a controller (130) (see paragraph 46; Fig. 1), wherein the controller is configured to sense the sub-pixels (PXn) sequentially in units of a pixel line and in units of color on the pixel line (see paragraphs 54-56; Figs. 1, 3).
Therefore it would have been obvious to one of ordinary skill in the art to allow the usage of a sequential sensing unit similar to that which is taught by Jeon to be carried out in a system similar to that which is taught by Lee, Hayafuji, and Staggs to thereby improve degradation of pixels in the display panel (see Jeon; paragraph 57).
With reference to claims 8 and 14, Lee, Hayafuji, Staggs, and Jeon disclose the display device of claim 4 or 11, wherein Jeon further discloses that the controller (130) comprises a memory (LUT) configured to store information on a pixel line of the selected sub pixel (in teaching compensation data; see paragraph 57).
With reference to claim 9, Lee, Hayafuji, Staggs, and Jeon disclose the display device of claim 4, wherein Lee further discloses wherein the controller (180) is configured to transmit a sensing start signal (STV) to the gate driver (120, 160, 170), and the gate driver is configured to output the gate clock signal in response to the sensing start signal (see paragraphs 90-92; Fig. 1).
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Staggs.
With reference to claim 16, Lee discloses a display device (100) (see paragraphs 39-40; Fig. 1), comprising:
a display panel (110) comprising sub-pixels (PX) arranged in pixel lines (see paragraph 42; Fig. 1);
a controller (180) configured to sense (SS) a characteristic of a driving transistor of a selected sub-pixel (PX) (see paragraphs 45, 50; Fig. 1), and
wherein: the controller is configured to output a first clock and a second clock (off/on clock) based on a count value that increases from an initial value during a sensing period for sensing the selected sub-pixel (see paragraphs 109-111, Fig. 12).
While disclosing the features as described, Lee fails to specifically disclose setting the count value as recited.
Staggs discloses an display device and method for providing signals to the display pixels, wherein the controller is configured to output a first clock and a second clock based on a count value that increases from an initial value, and the controller is configured to set the initial value of the count value to be a first value based on the selected sub-pixel is on a same pixel line as a immediately previously sensed sub-pixel and to determine the initial value of the count value to be a second value based on the selected sub-pixel is on a different pixel line from the immediately previously sensed sub-pixel, the first value greater than the second value (see column 6, line 17-column 7, line 11; Fig. 5), [and] the count value of each selected sub-pixel ending with a same third value (in teaching the same ending count value at the detection of end-of-line; column 6, lines 50-60; Fig. 5).
Therefore it would have been obvious to allow the usage of a count value by the controller to determine the next line to be displayed similar to that which is taught by Staggs to be carried out in a display device similar to that which is taught by Lee and Hayafuji to thereby produce the required clocking signals for the video display generator (see Staggs; column 2, lines 61-66).
With reference to claim 17, Lee and Staggs disclose the display device of claim 16, wherein Lee further discloses that the gate driver is configured to output a scan signal for the selected sub-pixel based on the first clock signal and the second clock signal (in teaching outputting SC_CLK1 in response to the over current count in the kickoff/on mode; see paragraphs 117-118, 123-124; Figs. 12-14).
With reference to claim 18, Lee and Staggs disclose the display device of claim 16, wherein Lee further discloses that the controller is configured to output the first clock (SC_CLK_I) in response to the count value reaching a first reference count value (IL4) (see paragraph 111; Figs. 12, 14) and to output the second clock (SC_CLK_I) in response to the count value reaching a second reference count value (IL5) that is greater than the first reference count value (IL4) (see paragraphs 117-119; Fig. 14).
With reference to claim 19, Lee and Staggs disclose the display device of claim 18, wherein Chen further discloses that the controller is configured to set the initial value of the count value to the first reference count value in response to the selected sub-pixel being on the same pixel line as the immediately previously sensed sub-pixel (see column 6, line 17-column 7, line 11; Fig. 5), and the controller is configured to set the initial value to a value smaller than the first reference count value in response to the selected sub-pixel being on a different pixel line from that of the immediately previously sensed sub-pixel (see column 6, line 17-column 7, line 11; Fig. 5).
Response to Arguments
Applicant's arguments filed 05/10/2026 have been fully considered but they are not persuasive. The applicant argues that the combination of references fails to disclose the count value of each selected sub-pixel ending with a same third value as recited in claims 1, 11, and 16. The examiner finds the limitation is new matter as there is no description provided in the specification that details a third value in relation to the count value. Further, there is no support provided by the specification that describes how each selected sub-pixel ends with the same value when each sub-pixel is assigned a different count value. Therefore as explained above the examiner finds the amended limitation to be new matter, as well as indefinite as there are no details provided by the specification that describes the recited third value. For purposes of rejection the examiner finds that Staggs discloses a same third value in teaching the value for the end-of line detector (50) (see column 6, lines 50-60; Fig. 5). For these reasons the examiner finds that the combination of references disclose the invention recited.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
SEKIGUCHI et al. (US2025/0199129) disclose a display apparatus wherein each pixels includes a sensing circuit that allows detection of incidence of a photon, and a counter circuit that counts a pulse output from the sensing circuit (see abstract; paragraphs 94-100; Fis. 5-7).
TUNG et al. (US2010/0177067) discloses a display device having a first, second, and third counter, wherein the third counter value controls the length of the horizontal line in the display period (see paragraphs 8-11, 16-21, claims 1-3; Figs. 3-4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALECIA DIANE ENGLISH whose telephone number is (571)270-1595. The examiner can normally be reached M0n.-Fri. 7:00am-3:00am.
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/ADE/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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