Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office acknowledges receipt of the following items from the Applicant:
Claims 1-21 are presented for examination.
Claim 4 amended (overcome the restriction requirement).
Claim 1-21 are pending claims.
Claims 1-5 and 19 are rejected.
Claims 6-11 and 20-21 are objected.
Claims 12-18 are allowed.
Election/Restrictions
Applicant’s election of Species I (Claims 1-18) with traverse is acknowledged. Applicant traverses the requirement for election of species because these two “group of claims contain subject matter that substantially overlaps.” As directed to the reasons for distinctness (i.e., one group requires twisted complementary global digit lines that alternate the location of the true or complementary global digit line, one vertically on top of the other), applicant amended claim 4 to recite this feature, thereby persuading the examiner that a requirement for election of species is no longer necessary. Therefore, the requirement for election of species mailed 11/5/25 is hereby withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stanfield, U.S. Patent No. 9,406,351.
With regard to claim 1, Stanfield discloses a device (fig. 6, plurality of memory unit 10) comprising: a plurality of memory cells configured to store data (fig. 6, plurality of memory cells 20) discloses an array of memory cells intersecting between WL & BL (col. 1, L42-L49), for write operation in which a data value is written to a memory cell and for reading (col. 6, line 10-12 for reading); a plurality of global digit lines (fig. 6, GBL 11, 12) configured to carry the data in memory accesses of the plurality of memory cells (fig. 6, memory cell 20); a plurality of local digit lines (fig. 6, local bitline 31, 32) configured to carry the data between the plurality of global digit lines (FIG. 6, GBL 11,12) and the plurality of memory cells (fig. 6, memory cell 20); a plurality of digit line selection circuits (fig. 6, switch 35, 36) configured to selectively couple selected local digit lines (fig. 6, local bitline 31, 32) of the plurality of local digit lines to the plurality of global digit lines (fig. 16, GBL 11, 12) (col. 5, line 25-28); and a controller (fig. 6, logic circuit 33 (i.e. extra switches 33a & 33b)) configured to select a pattern of selected digit line selection circuits (fig. 6, switch 35, 36) to at least partially cancel capacitive coupling between the selected local digit lines ((col. 4, line 58-64) and (col. 7, L36-41)) discloses the logic circuit selectively connects additional local bit lines to a global bit line to add capacitance that compensates for parasitic and coupling effects during read operations, thus, teaching claimed selection of the digit line connects to compensate for capacitive coupling.
With regard to claim 2, Stanfield discloses wherein the plurality of digit line selection circuits (fig. 6, switch 35 and 36) (col. 3, line 3-9) comprises a plurality of multiplexers (selection circuits 35 and 36 in fig. 3 are functional equivalent to multiplexers).
With regard to claim 3, Stanfield discloses wherein the plurality of digit line selection circuits comprises a plurality of access transistors (fig. (fig. 13, 40b and 41b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4, 5 and 19 are rejected under 35 U.S.C. 103(a) as being unpatentable over Stansfield Pat. No. 9,406,351, in view of Sato, US. Pat. Application No. 2011,0134678.
With regard to claim 4 and 19, Stansfield, as applied in prior rejection, disclosed all claimed subject matter including the plurality of digit line selection circuits (fig. 6, selection circuits (fig. 6, switch 35, 36). Stansfield, however, did not discloses wherein the plurality of digit line selection circuits includes a plurality of twists of the plurality of global digit lines alternating between a respective global digit line and a corresponding complementary global digit line to alternate positions, wherein each of the plurality of twists alternate between the respective global digit line and the corresponding complementary global digit line being vertically on top in a respective pair.
However, Sato discloses the digit line selection circuits (fig. 1, columns switches pair YSW0 & YSO and pair YSW1 & YS1) to includes a plurality of twists of the plurality of global digit lines (fig. 1, GBLTi & GBLBi pair) alternating between a respective global digit line (fig. 1, GBLT0) and a corresponding complementary global digit line (fig. 1, GBLB0) alternate positions, wherein each of the plurality of twists alternate between the respective global digit line and the corresponding complementary global digit line being vertically on top in a respective pair (page 3, [col. 0031], line 1-5). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the memory device of Stansfield to include the twisted complemental global digit line structure as taught by Sato. Applying the known twisting technique of Sato’s to the complementary global digit lines of Stansfield would represent the predictable use of a known design technique to improve the performance of the memory device and such modification would have been motivated by the known benefit of canceling/reducing capacitive coupling between the global and complementary digit lines, thereby, improving signal quality.
With regard to claim 5, Stansfield, as applied in prior rejection, disclosed all claimed subject matter including wherein the pattern comprises a selected local digit line in each region between each twist of the plurality of twists (page 3, [0031], L5-9).
Allowable Subject Matter
Claim 6-11 and 20-21 are objected as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record does not show the limitation of wherein the pattern comprises at least one active local digit line used to transfer data via a first region between a first pair of twists of the plurality of twists and a plurality of dummy selected local digit lines of the plurality of digit lines in other regions between other twists of the plurality of twists (claim 6 & 7).
The prior art of record does not show the limitation of wherein the pattern comprises wherein the controller is configured to select a plurality of default dummy selected local digit lines of the plurality of local digit lines during an idle mode when no memory is being accessed via the plurality of local digit lines (claim 8-11).
The prior art of record does not show the limitation of wherein the controller is configured to transition from and use an active state by unselecting one of a plurality of default dummy selected local digit lines used during an idle mode; selecting an active local digit line of the plurality of local digit lines; selecting a word line; and performing a memory access using the active local digit line, a corresponding global digit line, and the word line (claim 20-21).
Claims 12-18 are allowed.
Claims 12-18 are considered allowable since prior art made of record and considered pertinent to the applicants disclosure does not teach or suggest the claimed limitations having in combination with other features, a method for operating a memory device, comprising: selecting a local digit line of a plurality of local digit lines for a memory access to couple to a corresponding global digit line; selecting a plurality of local digit lines as dummy local digit lines in a plurality of regions to compensate for capacitive coupling between global digit lines and to compensate for capacitive coupling between local digit lines, wherein each region corresponds to a segment of a global digit line between twists of the global digit line with a corresponding complementary global digit line; and performing the memory access using the local digit line, a corresponding word line, and the corresponding global digit line.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure.
Barth Jr. (7012826) discloses a memory device having in combination with other features, a bitline structure for a memory array includes a first pair of complementary bitlines and a second pair of complementary bitlines. Both the first and second pair of complementary bitlines have a twist at a location corresponding to about 1/4 of the total length of the bitline structure. The second pair of complementary bitlines further have a twist at a location corresponding to about 1/2 of the total length of the bitline structure, and both the first and second pair of complementary bitlines have a twist at a location corresponding to about 3/4 the total length of the bitline structure.
Kim (6975552) disclose a memory a digit line architecture for an array of memory cells exhibiting characteristics of both folded digit line architectures and an open digit line architectures. The digit line architecture includes first and second digit lines having first and second digit line segments. The memory cells of a column are coupled to the first digit line segments. The second digit line segment of the first digit line is located in the memory sub-array with which the column is associated and the second digit line segment of the second digit line extending into the other memory sub-array with which the column is not associated.
When responding to the office action, Applicants’ are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to whose telephone number is (571) 272-1799. The examiner can normally be reached on Mon. - Fri. from 8:00 A.M. to 5:30 PM. The examiner's supervisor, Alexander Sofocleous, can be reached at (571) 272-0635. The fax phone number for this Group is (571) 273-8300.
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/CONNIE C YOHA/Primary Examiner, Art Unit 2825