DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is responsive to Application 18/500,147 filed 11/02/2023 in which claims 1-20 are presented for examination.
Allowable Subject Matter
Claims 7, 8 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 6, 9 and 11-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura (US 2012/0314717 A1).
Regarding claim 1, Nakamura teaches a network device (Nakamura: Fig. 1:10, [0028] Apparatus 10), comprising:
a front-end processing circuit, arranged to receive a first predetermined packet from a network interface, comprising: a receiving signal processing circuit, arranged to obtain a receiving timestamp corresponding to the first predetermined packet in response to reception of the first predetermined packet, generate a first time information corresponding to the first predetermined packet according to the receiving timestamp, and provide the first predetermined packet and the first time information to a core circuit (Nakamura: Fig. 1; [0029]-[0031], PHY processor 11 and timestamping unit 13/receiving circuit, receives a frame, generates and add a current timestamp/first time information to the received frame) and transmit the timestamped frame to the MAC processor/core circuit);
the core circuit, comprising:
a packet parser, arranged to parse the first predetermined packet to obtain a first parsing result, and determine whether to record the first time information according to the first parsing result (Nakamura: Fig. 2:14; [0032], the MAC processor 14/parser performs analysis on the frame); and
a packet modifier, wherein in response to the first time information being recorded, the packet modifier is arranged to store the first time information, and provide the first determined packet to a processor (Nakamura: Fig. 2; [0033]-[0037] MACsec processor 15/modifier, performs conversion on the frame and decide whether to store the timestamp); and
the processor, wherein in response to the first time information being recorded, the processor is arranged to obtain the first time information, and obtain the receiving timestamp according to first time information (Nakamura: Fig. 2; [0048]-[0049] timestamp restoration unit/processor, obtain the stored timestamp).
Regarding claim 9, Nakamura teaches a network device (Nakamura: Fig. 5:30, Apparatus 30), comprising:
a processor, arranged to generate a first predetermined packet, and provide the first predetermined packet to a core circuit (Nakamura: Fig. 5; [0061], upper processor generate a frame and transmits it to a flagging unit/core circuit);
the core circuit, comprising: a packet parser, arranged to parse the first predetermined packet to obtain a first parsing result, generate a control information corresponding to the first predetermined packet according to the first parsing result, and provide the first predetermined packet and the control information to a front-end processing circuit (Nakamura: Fig. 5, 7; [0062]-[0064], the frame is flagged/control information and transmits to the MAC processors); and
the front-end processing circuit, comprising: a transmitting signal processing circuit, arranged to obtain a transmitting timestamp corresponding to the first predetermined packet in response to reception of the first predetermined packet, determine to write the transmitting timestamp into the first predetermined packet or a register according to the control information, and transmit the first predetermined packet (Nakamura: Fig. 2; [0063]-[0077], the MAC processor transmit the flagged frame based on the flag information).
Regarding claim 16, Nakamura teaches a network packet processing method, applied to a network device, comprising:
by a processor of the network device, generating a first predetermined packet, and providing the first predetermined packet to a core circuit of the network device (Nakamura: Fig. 5; [0061], upper processor generate a frame and transmits it to a flagging unit/core circuit);
by a packet parser of the core circuit, parsing the first predetermined packet to obtain a first parsing result corresponding to the first predetermined packet, generating a control information corresponding to the first predetermined packet according to the first parsing result, and providing the first predetermined packet and the control information to a front-end processing circuit (Nakamura: Figs. 5 and 7; [0062]-[0064], the frame is flagged/control information and transmits to the MAC processors); and
by the front-end processing circuit, obtaining a first transmitting timestamp corresponding to the first predetermined packet in response to reception of the first predetermined packet, determining to write the first transmitting timestamp into the first predetermined packet or a register according to the control information, and transmitting the first predetermined packet (Nakamura: Figs 5 and 7; [0063]-[0077], the MAC processor transmit the flagged frame based on the flag information).
Regarding claims 3 and 11, Nakamura teaches wherein the receiving signal processing circuit comprises a physical (PHY) layer receiving signal processing circuit, the receiving timestamp is obtained by the PHY layer receiving signal processing circuit, and the first time information is generated by the PHY layer receiving signal processing circuit (Nakamura: Figs. 1,2 and 5; see description in [0028]-[0065]).
Regarding claims 4 and 12, Nakamura teaches wherein the receiving signal processing circuit comprises a media access control (MAC) layer receiving signal processing circuit, the receiving timestamp is obtained by the MAC layer receiving signal processing circuit, the first time information is generated by the MAC layer receiving signal processing circuit, and the first predetermined packet and the first time information are provided to the core circuit through a bus (Nakamura: Figs. 1,2 and 5; see description in [0028]-[0065]).
Regarding claim 6, Nakamura teaches wherein the front-end processing circuit further comprises: a transmitting signal processing circuit, arranged to receive a second predetermined packet and a control information corresponding to the second predetermined packet, obtain a first transmitting timestamp corresponding to the second predetermined packet in response to reception of the second predetermined packet, determine to write the first transmitting timestamp into the second predetermined packet or a register according to the control information, and transmit the second predetermined packet (Nakamura: Fig. 5, 7; [0061]-[0064], a generated frame in the upped layer is flagged/control information and transmitted to the MAC processors along with timestamps information).
Regarding claims 13 and 17, Nakamura teaches wherein the front-end processing circuit further comprises: a receiving signal processing circuit, arranged to receive a second predetermined packet from a network interface, obtain a receiving timestamp corresponding to the second predetermined packet in response to reception of the second predetermined packet, generate a time information corresponding to the second predetermined packet according to the receiving timestamp, and provide the second predetermined packet and the time information to the core circuit; wherein the packet parser parses the second predetermined packet to obtain a second parsing result, and determine whether to record the time information according to the second parsing result; and the core circuit further comprises: a packet modifier, wherein in response to the time information being recorded, the packet modifier stores the time information, and provides the second predetermined packet to the processor; wherein in response to the time information being recorded, the processor obtains the time information, and obtains the receiving timestamp according to the time information (Nakamura: Figs. 1-3; [0029]-[0037], PHY processor 11 and timestamping unit 13/receiving circuit, receives a frame, generates and add a current timestamp/first time information to the received frame) and transmit the timestamped frame to the MAC processor/core circuit).
Regarding claim 14, Nakamura teaches wherein the processor generates a third predetermined packet, and writes the receiving timestamp into the third predetermined packet (Nakamura: Figs. 1-3; [0029]-[0037], PHY processor 11 and timestamping unit 13/receiving circuit, receives a frame, generates and add a current timestamp/first time information to the received frame)).
Regarding claim 15, Nakamura teaches wherein the second parsing result comprises a message type of the second predetermined packet, and a parsing result corresponding to the third predetermined packet comprises a message type of the third predetermined packet (Nakamura: Figs 3 and 7; Abstract; [0098]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2012/0314717 A1) in view of Tzeng et al (US 2023/0246723 A1).
Regarding claims 2 and 10, Nakamura does not explicitly disclose wherein the first predetermined packet is a precision time protocol (PTP) packet.
Tzeng teaches wherein the first predetermined packet is a precision time protocol (PTP) packet (Tzeng: Fig. 3A and 4; [0049]-[0050]).
It would have been obvious to a person having an ordinary skill in the art before the effective filling date of the claimed invention to modify the system of Nakamura wherein the first predetermined packet is a precision time protocol (PTP) packet as disclosed by Tzeng to provide a system for time synchronization (Tzeng: Abstract).
Regarding claim 5, Nakamura in view of Tzeng teaches wherein the receiving timestamp is represented by a first number of bits, the receiving signal processing circuit simplifies the first number of bits to generate the first time information represented by a second number of bits, and the second number of bits is smaller than the first number of bits (Tzeng: [0059]-[0060], [0069]).
Conclusion
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/KODZOVI ACOLATSE/Primary Examiner, Art Unit 2478