DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 1/28/2026 have been fully considered but they are moot in view of the new grounds of rejection. Applicant's arguments with respect to claim 7 have been considered but they are not persuasive.
Applicant argues with respect to claim 7 that Jain can not disclose “all bits of the data unit are payload data” because bits of the final frame after the end packet 342 are discarded and replaced with zeros.
The Examiner disagrees with Applicant’s interpretations of the teachings of Jain. In paragraph 47, Jain clearly discloses that bits of the final frame are “downshifted” and all most significant bits are replaced with zeroes. This means that if a last byte 342 does not align with the end of the frame, then data payload data is shifted to the end of the frame with zeroes being inserted into the now empty most significant bit positions to fill out the frame.
As a side note, the first frame and the final frame having concatenated zeroes is merely a pre-process step to align the input data and does not affect what happens to the data after processing. If payload data of the final frame does not fill out the entire frame, it can be concatenated with zeroes. Once the frames are processed, if data of a final frame does not align with the end of the frame (which will have concatenated zeroes), then the data is downshifted to where those zeroes were and the now empty MSBs are replaced with zeroes.
Jain explicitly states in paragraph 47 that “For a final frame, the first stage 402 calculates the CRC value for the data in that final frame.” Therefore, all bits of the final data unit after performing the manipulation of Jain are indeed payload data as now claimed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 19, 22, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Westby (US Pat. 5,802,080) in view of Tran (US Pat. 6,202,060) in view of Greenlaw (US Pat. Pub. 2008/0115040) in view of Kamiya (US Pat. Pub. 2003/0112833).
As per claim 1: Westby teaches an electronic circuit comprising:
an interface (see Fig. 2; The Authoritative Dictionary of IEEE Standards Terms, 7th Edition defines interface: A shared boundary between two objects such as devices, systems, or networks, across which information is passed. The connection point between any two blocks shown in Fig. 2 of Westby form a boundary and may be considered part of an interface) configurable to receive a data unit (Fig. 2, DATA);
a data path coupled to the multi-bit interface (Fig. 2, DATA on path 16 and 18);
a port coupled to the data path (Fig. 2, 12);
a cyclic redundancy check (CRC) generation circuit coupled to the data path and to the interface (Fig. 2, 24 and 30), the CRC generation circuit configurable to provide a CRC based on the data unit, to the data path (col. 4, lines 30-32) and to the multi-bit interface (col. 4, lines 53-55); and
wherein the data path includes a switch configurable to selectively couple the CRC generation circuit to the port (Fig. 2, 28).
Not explicitly disclosed is the port being a serial port. However, Tran in an analogous art teaches that a fiber channel port is a serial port (col. 12, lines 25-28).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use a serial port for the fiber channel port 12 in Westby. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Westby teaches the port 12 being a fiber channel port (col. 4, lines 43-44), and a serial port would have been cost effective (col. 12, lines 25-28).
Also not explicitly disclosed is a CRC checksum. However, Greenlaw in an analogous art teaches a checksum generator (Fig. 1) for generating a CRC checksum (paragraph 5). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to either use the CRC generator of Greenlaw in the system of Westby, or label the CRC output of Westby a checksum.
This modification would have been obvious for one of ordinary skill in the art at the time of filing because Greenlaw teaches a suitable CRC generator that could have been used to perform the function required by Westby; and one of ordinary skill in the art would have recognized that the CRC of Westby was a checksum because it was well-known that a CRC is a type of checksum commonly used in the art (Greenlaw paragraph 5).
Also not explicitly disclosed is a parallel interface. However, Kamiya in an analogous art teaches a 8B/10B parallel interface (paragraph 102; Fig. 1, 101). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to label the boundary of Westby a parallel interface. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Westby also teaches using parallel 8B/10B encoders (col. 4, lines 4-12).
As per claim 2: Westby further teaches the electronic circuit of claim 1, wherein the data path is a transmit data path (Fig. 2, upper path; Fig. 3).
As per claim 4: Westby further teaches the electronic circuit of claim 1, wherein the data path includes: a data register coupled between the parallel interface and the serial port (Fig. 2, 20); and a first storage device coupled between the data register and the serial port (Fig. 2, 46).
As per claim 19: Westby further teaches the electronic circuit of claim 1, further comprising a bidirectional bus coupled between the CRC generation circuit and the multi-bit interface, the bidirectional bus being separate from the data path (Fig. 2; a bidirectional bus is shown at 16 as input/output to port A).
As per claim 22: Westby further teaches the electronic circuit of claim 1, wherein, when the switch is open, the CRC generation circuit is configured to be usable via the multi-bit interface (Fig. 2, the CRC is usable on port B via the parallel interface when MUX 28 is switched).
As per claim 23: Westby further teaches the electronic circuit of claim 22, wherein, when the switch is open, the CRC generation circuit is configured to be usable via the parallel interface by an application software (col. 4, lines 11-16; application software is necessarily present to control the disc and microprocessor hardware).
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Westby in view of Tran in view of Greenlaw in view of Kamiya in view of Lucas et al (US Pat. 5,928,375; hereinafter referred to as Lucas).
As per claim 5:
Westby et al teach the electronic circuit of claim 4. Not explicitly disclosed is wherein the first storage device is a first-in-first-out (FIFO) storage device. However, Lucas in an analogous art teaches a FIFO buffer (Fig. 2A, 60; col. 4, lines 54-55).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use a FIFO as the buffer in Westby. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Lucas teaches that a FIFO is a known way to implement a buffer.
Claim(s) 6 are rejected under 35 U.S.C. 103 as being unpatentable over Westby in view of Tran in view of Greenlaw in view of Kamiya in view of Rutman (US Pat. 5,313,5896).
As per claim 6: Westby et al teach the electronic circuit of claim 4. Not explicitly disclosed is further comprising a shift register coupled between the first storage device and the serial port. However, Rutman in an analogous art teaches a serial port (Fig. 3, 220) comprising a shift register (Fig. 3, 300; col. 4, lines 49-54).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the serial port of Rutman in the system of Westby et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because the port of Westby et al is a serial port, and Rutby provides an example of such a port that could have been used.
Claim(s) 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Westby in view of Tran in view of Greenlaw in view of Kamiya in view of Jain (US Pat. Pub. 2021/0314088).
As per claim 7: Westby further teaches the electronic circuit of claim 4, wherein the data register is an M-bit data register configured to store the data unit (buffer 20 necessarily stores more than zero bits). Not explicitly disclosed is the electronic circuit further comprising a correction circuit configured to replace an M-N most significant bits of the data unit with zeros, N being an integer greater than 0 and lower than M, and all bits of the data unit are payload data. However, Jain in an analogous art teaches a CRC correction circuit configured to replace an M-N most significant bits of the data unit with zeros (paragraph 47), with all bits being payload data (see Response to Arguments above).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the CRC circuit of Jain in the system of Westby. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Westby teaches a CRC circuit (Fig. 2, 24), and the CRC of Jain could have been used for that purpose.
As per claim 8: Westby further teaches the electronic circuit of claim 7, wherein the data register is configured to receive the data unit from a central processing unit (CPU) (col. 4, lines 15-16) or a direct memory access (DMA) controller via the parallel interface.
Claim(s) 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Westby in view of Tran in view of Greenlaw in view of Kamiya in view of Keller (US Pat. Pub. 2002/0174399).
As per claim 9: Westby further teaches the electronic circuit of claim 1, wherein the data unit is an X-bit data unit (the data necessarily has a finite number of non-zero bits), and the CRC checksum is a first CRC checksum (Fig. 2, 24).
Not explicitly disclosed is wherein the CRC generation circuit is configured to provide the first CRC checksum in response to the X-bit data unit and an X-bit polynomial. However, Keller in an analogous art teaches a CRC generator which provides a CRC result in response to a X-bit data unit and X-bit polynomial (Fig. 5, 502h: 1-bit data unit and 1-bit polynomial). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the CRC generator of Keller in the system of Westby et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Westby teaches a CRC circuit 24, and Keller shows an example of a CRC circuit that could have been used.
As per claim 10: Keller further teaches the electronic circuit of claim 9, wherein the CRC generation circuit is configured to provide a second CRC checksum in response to a 2X-bit data unit on the data path and a 2X-bit polynomial (Fig. 5, 502g: 2-bit data unit and 2-bit polynomial).
Claim(s) 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Westby in view of Tran in view of Greenlaw in view of Kamiya in view of Wyland (US Pat. 6,836,869).
As per claim 14: Westby further teaches the electronic circuit of claim 1, wherein the data unit is an X-bit data unit (the data necessarily has a finite number of non-zero bits). Not explicitly disclosed is wherein the CRC generation circuit is configured to provide the CRC checksum in response to the X-bit data unit and a 2X-bit polynomial. However, Wyland in an analogous art teaches generating a CRC in response to a X-bit data unit and a selectable 2X-bit polynomial (col. 4, lines 27-39).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the CRC generator of Wyland in the system of Westby et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Westby teaches a CRC circuit 24, and Wyland shows an example of a CRC circuit that could have been used.
As per claim 15: Wyland further teaches the electronic circuit of claim 14, wherein the CRC generation circuit is configured to provide the CRC checksum within a single clock cycle of a clock signal (col. 15, lines 45-62; CRX32).
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Westby in view of Tran in view of Greenlaw in view of Kamiya in view of Kwon et al (US Pat. Pub. 2003/0106006; hereinafter referred to as Kwon).
As per claim 16: Westby et al teach the electronic circuit of claim 1. Not explicitly disclosed is wherein the data unit is a 2X-bit data unit, and the CRC generation circuit has a collective X-bit input configured to provide the CRC checksum. However, Kwon in an analogous art teaches a CRC generation circuit have a collective 4-bit input (Fig. 5A; x1, x3, x4, x7) for providing a CRC of a 8-bit data unit (Fig. 5A, x0-x7).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the CRC generator of Kwon in the system of Westby et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Westby teaches a CRC circuit 24, and Kwon shows an example of a CRC circuit that could have been used.
Claim(s) 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Westby in view of Tran in view of Greenlaw in view of Kamiya in view of Chilton et al (US Pat. 6,279,050; hereinafter referred to as Chilton).
As per claim 17: Westby et al teach the electronic circuit of claim 1. Not explicitly disclosed is further comprising a CRC seed auto-generator configured to provide a CRC seed to the CRC generation circuit. However, Chilton in an analogous art teaches providing a CRC seed to a CRC generation circuit (col. 32, lines 14-15).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the CRC generator of Chilton in the system of Westby et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Westby teaches a CRC circuit 24, and Chilton shows an example of a CRC circuit that could have been used.
As per claim 18: Chilton further teaches the electronic circuit of claim 17, wherein the CRC seed auto-generator is configured to provide the CRC seed to the CRC generation circuit in response to a read or write operation to a register of the CRC generation circuit (col. 32, lines 8-11).
Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable over Westby in view of Tran in view of Greenlaw in view of Kamiya in view of Ripley et al (US Pat. Pub. 2010/0178960; hereinafter referred to as Ripley).
As per claim 21: Westby et al teach the electronic circuit of claim 1. Not explicitly disclosed is herein the serial port is a serial port of a serial peripheral interface (SPI), an inter-integrated circuit (I2C) interface, or a universal asynchronous receiver-transmitter (UART) interface. However, Ripley in an analogous art teaches a Serial Peripheral Interface (paragraph 16).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use a Serial Peripheral Interface in the system of Westby et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it was a well-known di-directional serial interface (paragraph 16).
Claim(s) 24 is rejected under 35 U.S.C. 103 as being unpatentable over Westby in view of Greenlaw in view of Kamiya.
As per claim 24: Westby teaches an electronic circuit comprising:
a port (Fig. 2, 12) configurable to receive a data unit (Fig. 2, 16);
a data path coupled to the port (Fig. 2, DATA on path 16 or 18);
an interface coupled to the data path (see Fig. 2; The Authoritative Dictionary of IEEE Standards Terms, 7th Edition defines interface: A shared boundary between two objects such as devices, systems, or networks, across which information is passed. The connection point between any two blocks shown in Fig. 2 of Westby form a boundary and may be considered part of an interface) and configurable to couple to a processor (Fig. 2, µP); and
a cyclic redundancy check (CRC) generation circuit coupled to the data path and to the interface (Fig. 2, 24), the CRC generation circuit configurable to provide a CRC, based on the data unit, to the interface (col. 4, lines 30-32).
Not explicitly disclosed is a CRC checksum. However, Greenlaw in an analogous art teaches a checksum generator (Fig. 1) for generating a CRC checksum (paragraph 5). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to either use the CRC generator of Greenlaw in the system of Westby, or label the CRC output of Westby a checksum.
This modification would have been obvious for one of ordinary skill in the art at the time of filing because Greenlaw teaches a suitable CRC generator that could have been used to perform the function required by Westby; and one of ordinary skill in the art would have recognized that the CRC of Westby was a checksum because it was well-known that a CRC is a type of checksum commonly used in the art (Greenlaw paragraph 5).
Also not explicitly disclosed is a parallel interface. However, Kamiya in an analogous art teaches a 8B/10B parallel interface (paragraph 102; Fig. 1, 101). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to label the boundary of Westby a parallel interface. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Westby also teaches using parallel 8B/10B encoders (col. 4, lines 4-12).
Claim(s) 25 is rejected under 35 U.S.C. 103 as being unpatentable over Westby in view of Greenlaw in view of Jain.
As per claim 25: Westby teaches an electronic circuit comprising:
a multi-bit interface (see Fig. 2; The Authoritative Dictionary of IEEE Standards Terms, 7th Edition defines interface: A shared boundary between two objects such as devices, systems, or networks, across which information is passed. The connection point between any two blocks shown in Fig. 2 of Westby form a boundary and may be considered part of an interface, and because there is more than one bit signal, it is a multi-bit interface) configurable to receive a first data unit (Fig. 2, DATA);
a data path coupled to the multi-bit interface (Fig. 2, DATA on path 16 and 18);
a port coupled to the data path (Fig. 2, 12); and
an M-bit data register coupled between the multi-bit interface and the port, the data register configurable to store the first data unit (Fig. 2, 20 necessarily stores more than zero bits);
a memory coupled between the data register and the port (Fig. 2, 52);
a cyclic redundancy check (CRC) generation circuit coupled to the data path and to the multi-bit interface (Fig. 2, 24 and 30), the CRC generation circuit configurable to provide a CRC, based on the second data unit, to the data path (col. 4, lines 30-32) and to the memory (col. 4, lines 53-55);
wherein the memory is configurable (Fig. 2, 28) to provide the third data unit to the serial port (see Fig. 1).
Not explicitly disclosed is the port being a serial port. However, Tran in an analogous art teaches that a fiber channel port is a serial port (col. 12, lines 25-28).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use a serial port for the fiber channel port 12 in Westby. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Westby teaches the port 12 being a fiber channel port (col. 4, lines 43-44), and a serial port would have been cost effective (col. 12, lines 25-28).
Also not explicitly disclosed is a CRC checksum. However, Greenlaw in an analogous art teaches a checksum generator (Fig. 1) for generating a CRC checksum (paragraph 5). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to either use the CRC generator of Greenlaw in the system of Westby, or label the CRC output of Westby a checksum.
This modification would have been obvious for one of ordinary skill in the art at the time of filing because Greenlaw teaches a suitable CRC generator that could have been used to perform the function required by Westby; and one of ordinary skill in the art would have recognized that the CRC of Westby was a checksum because it was well-known that a CRC is a type of checksum commonly used in the art (Greenlaw paragraph 5).
Also not explicitly disclosed is a correction circuit included in the data path, the correction circuit configurable to replace an M-N most significant bits of the first data unit with zeroes to provide a second data unit, N being an integer greater than 0 and lower than M, and configurable to provide the N non-zeroed bits of the second data unit to the memory as a third data unit. However, Jain in an analogous art teaches a CRC correction circuit configured to replace an M-N most significant bits of the data unit with zeros to provide a data unit (paragraph 47: “The data for the final frame is “downshifted,” and all most significant bits are replaced with zeroes”), and provide the N remaining non-zeroed bits as a data unit (paragraph 47: “For a final frame, the first stage 402 calculates the CRC value for the data in that final frame”).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the CRC circuit of Jain in the system of Westby. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Westby teaches a CRC circuit (Fig. 2, 24), and the CRC of Jain could have been used for that purpose.
Allowable Subject Matter
Claims 11-13 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached on 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVE N NGUYEN/Primary Examiner, Art Unit 2111