DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 1- 3 are rejected under 35 U.S.C. 103 as being unpatentable over [Shimamoto (Fig. 10); 11,469,713] in view of [Aude (Fig. 1); 6,747,514] . Regarding claim 1, Shimamoto discloses an amplifier circuit comprising a plurality of first unit transistors (Q1a, Q1b) connected in parallel with each other and configured to amplify a RF signal ( RFin ) and to output a first resultant signal (the signal coming out of the collector terminals of transistors Q1a and Q1b) , and a plurality of second unit transistors (Q 2 a, Q 2 b) connected in parallel with each other and configured to amplify the first resultant signal (the signal coming out of the collector terminals of transistors Q1a and Q1b) output by the first unit transistors (Q1a, Q1b) and to output a second resultant signal ( RFout ) . As described above, Shimamoto discloses all the limitations in claim 1 except for that the each of the first unit transistors is smaller than each of the second unit transistors . Aude discloses an amplifier circuit comprising first set of transistors are smaller than the second set of transistors (see claim 6) . It would have been obvious to one of ordinary skill in the art at the time the invention was made to have implemented the certain sizes of the transistors for the first and second unit transistors , such as thought by Aude since these transistors size are based on routine experimentation to obtain the optimum operating parameters in order to improve the gain of the amplifier circuit which leads to produce the linear amplifier rather than non-linear amplifier which generates a distortion signal as is typically known to one of ordinary skill in the art. Regarding claim 2, wherein the first unit transistors (Q1a, Q1b) are class A transistors. Regarding claim 3, wherein the second unit transistors (Q2a, Q2b) are class F transistors. Allowable Subject Matter Claims 4 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached Mon-Fri 6:00 AM- 6:00 PM EST. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea J Lindgren Baltzell can be reached on (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HENRY CHOE/ Primary Examiner, Art Unit 2843 #2953