DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 3, 6, 8, 10-12, 14, 17, and 19-20 are objected to because of the following informalities:
As per claim 1, “each target switch”, ll 15 should be “the each target switch in the set of target switch”. “the switch”, ll 16 should be “the each target switch in the set of target switch”.
As per claim 3, “each target switch in the set of target switches”, ll 2 should be “the each target switch in the set of target switches”. “each target switch”, ll 3 should be “the each target switch in the set of target switch”.
As per claim 6, “each GPU”, ll 1 should be “the each GPU”. “the GPU”, ll 2 should be ”the each GPU”.
As per claim 8, “third tier of switches”, ll 2 should be “the third tier of switches”. “third tier of switches”, ll 3 should be “the third tier of switches”.
As per claim 10, “a GPU”, ll 3 should be “a GPU included in the plurality of the GPU clusters.
As per claim 11, “the switch”, ll 1 should be “the switch from the plurality pf switches”. “the switch”, ll 2 should be “the switch from the plurality pf switches”.
As per claim 12, see objection on claim 1.
As per claim 14, see objection on claim 3.
As per claim 17, see objection on claim 6.
As per claim 19, see objection on claim 8.
As per claim 20, see objection on claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter.
Claims 1-20 are rejected under 35 U.S.C. 101.
As per claim 1, the claim recites a series of steps, therefore is a process.
The claim recites the limitation of “selecting one or more switches from the third tier of switches to form a set of target switches . . . generating, by each target switch in the set of target switches, a plurality of sets of address information by filtering received address information based on a condition”. These limitations, as drafted, are processes that, under its broadest reasonable interpretation, cover performance of the limitation in the mind but for the recitation of generic computer components. Thus, the claim recites a mental process.
The limitation of “receiving . . . address information of each GPU included in the plurality of GPU clusters . . . transmitting, by each target switch, the plurality of sets of address information to each switch included in the first tier of switches” amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); this limitation is also a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to the abstract idea.
As discussed above, “receiving . . . address information of each GPU included in the plurality of GPU clusters . . . transmitting, by each target switch, the plurality of sets of address information to each switch included in the first tier of switches” amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g). “providing a plurality of graphical processing unit (GPU) clusters, the plurality of GPU clusters being communicatively coupled with one another via a plurality of switches arranged in a hierarchical structure, the hierarchical structure including a first tier of switches, a second tier of switches, and a third tier of switches . . .” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See AAPA/Miriyala. The claim is ineligible.
As per claim 2, see rejection on claim 1. “wherein the plurality of GPU clusters includes at least a first GPU cluster operating at a first speed and a second GPU cluster operating at a second speed that is different than the first speed “ is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See John. The claim is ineligible.
As per claim 3, see rejection on claim 1. “configuring a connection . . . “ is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Miriyala/Xu. The claim is ineligible.
As per claim 4, see rejection on claim 3. “wherein the connection is a BGP peering connection“ is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Lo. The claim is ineligible.
As per claim 5, see rejection on claim 1. “wherein the switch included in the first tier of switches, discards other subsets of the plurality of sets of address information in accordance with the condition“ is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Srinivasan. The claim is ineligible.
As per claim 6, see rejection on claim 1. “ wherein address information of each GPU included in the plurality of GPU clusters corresponds to a MAC address of the GPU” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Lo. The claim is ineligible.
As per claim 7, see rejection on claim 1. “wherein the first tier of switches are communicatively coupled at one end to the plurality of GPU clusters and at another end to the second tier of switches, and wherein the second tier of switches communicatively couples the first tier of switches to the third tier of switches” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Miriyala. The claim is ineligible.
As per claim 8, see rejection on claim 1. “wherein the third tier of switches are partitioned into a plurality of groups of third tier of switches, and wherein the selecting further comprises selecting at least one target switch from each of the plurality of groups of third tier of switches” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Zuo. The claim is ineligible.
As per claim 9, see rejection on claim 1. “wherein a total number of target switches included in the set of target switches is in a range from 4 to 16” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Thyagarajan. The claim is ineligible.
As per claim 10, see rejection on claim 1. “wherein the condition corresponds to grouping, by the target switch, address information of GPUs included in the plurality of GPU clusters based on a VLAN of a customer that a GPU belongs to” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Nataraja. The claim is ineligible.
As per claim 11, see rejection on claim 1. “wherein the switch stores the subset of the plurality of sets of address information in an address table, and wherein the switch is further configured to purge an entry from the address table based on a timer associated with the entry” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Srinivasan. The claim is ineligible.
As per claim 12, see rejection on claim 1.
As per claim 13, see rejection on claim 2.
As per claim 14, see rejection on claim 3.
As per claim 15, see rejection on claim 4.
As per claim 16, see rejection on claim 5.
As per claim 17, see objection on claim 6.
As per claim 18, see rejection on claim 7.
As per claim 19, see rejection on claim 8.
As per claim 20, see rejection on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7, 12, 14, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art (Background, Spec) (hereinafter AAPA) in view of Miriyala et al (US 2022/0385570 ) (hereinafter Miriyala) further in view of Xu et al ( US 2020/0007440) (hereinafter Xu) .
As per claim 1, AAPA teaches:
A method comprising:
providing a plurality of graphical processing unit (GPU) clusters (AAPA, [0005]), the plurality of GPU clusters being communicatively coupled with one another via a plurality of network elements (AAPA, [0005]—under BRI, a plurality of elements can be elements in network topology that is constructed to support the GPU clusters), wherein a destination is each GPU included in the plurality of GPU clusters (AAPA, [0005]).
AAPA does not expressly teach:
the hierarchical structure including a first tier of switches, a second tier of switches, and a third tier of switches;
selecting one or more switches from the third tier of switches to form a set of target switches;
receiving, by each target switch in the set of target switches, address information of each GPU included in the plurality of GPU clusters;
generating, by each target switch in the set of target switches, a plurality of sets of address information by filtering received address information based on a condition; and
transmitting, by each target switch, the plurality of sets of address information to each switch included in the first tier of switches, wherein the switch stores a subset of the plurality of sets of address information in accordance with the condition.
However, Miriyala discloses:
the hierarchical structure including a first tier of switches, a second tier of switches, and a third tier of switches (Miriyala, Fig 1 switches 16, chassis switches 18, IP fabric 20);
selecting one or more switches from the third tier of switches to form a set of target switches (Miriyala, [0025]—under BRI, selecting one or more switches from the third tier of switches to form a set of target switches can be selecting IP fabric 20, which performs layer 3 routing to route network traffic between data centers 10 and customers 11 by service provider network 7);
receiving, by each target switch in the set of target switches, address information of the destination (Miriyala, [0027]—under BRI, , address information can be destination IP address in five-tuple, i.e., the protocol, source IP address, destination IP address, source port and destination port);
generating, by each target switch in the set of target switches, a plurality of sets of address information by filtering received address information based on a condition (Miriyala, [0086]—under BRI, filtering can be determining a policy from the destination IP address; a condition can be source identifier); and
wherein the switch stores a subset of the plurality of sets of address information in accordance with the condition (Miriyala, [0086]—under BRI, a subset of the plurality of sets of address information can be a subset of policies/ACL);
wherein the network elements are switches arranged in a hierarchical structure (Miriyala, Fig 1 switches 16, chassis switches 18, IP fabric 20);
Both Miriyala and AAPA pertain to the art of networked devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Miriyala’s method to use three tier switches because it is well-known in the art that 3-tier switches provide superior scalability, high redundancy, and enhanced fault isolation for large enterprise networks.
AAPA/Miriyala does not expressly teach:
transmitting, by each target switch, the plurality of sets of address information to each switch included in the first tier of switches;
However, Xu discloses:
transmitting, by each target switch, the plurality of sets of address information to each switch included in the first tier of switches (Xu, Fig 1, [0022]—under BRI, transmitting the plurality of sets of address information can be flow definition transmitted in switch fabric);
Both Xu and AAPA/Miriyala pertain to the art of networked devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Xu’s method to transmit address information (flow definition) because it is well-known in the art that having same set of address of information in all switches will provide redundancy in case one switch goes down.
As per claim 3, AAPA/Miriyala/Xu teaches:
The method of claim 1 (See rejection on claim 1), further comprising:
configuring a connection between each target switch in the set of target switches and each switch included in the first tier of switches (Miriyala, Fig 1), wherein each target switch receives address information of each GPU included in the plurality of GPU clusters from the first tier of switches via the connection (Xu, Fig 1, [0022]).
As per claim 7, AAPA/Miriyala/Xu teaches:
The method of claim (see rejection on claim 1), wherein the first tier of switches are communicatively coupled at one end to the plurality of GPU clusters and at another end to the second tier of switches (Miriyala, Fig 1), and wherein the second tier of switches communicatively couples the first tier of switches to the third tier of switches (Miriyala, Fig 1).
As per claim 12, see rejection on claim 1.
As per claim 14, see rejection on claim 3.
As per claim 18, see rejection on claim 7.
As per claim 20, see rejection on claim 1.
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA/Miriyala/Xu as applied above, and further in view of John et al (US 2018/0024869) (hereinafter John).
As per claim 2, AAPA/Miriyala/Xu teaches:
The method of claim 1 (See rejection on claim 1), wherein a plurality of clusters are GPU clusters (AAPA, [0005]), a first cluster is a GPU cluster (AAPA, [0005]), a second cluster is a GPU cluster (AAPA, [0005]);
AAPA/Miriyala/Xu does not expressly teach:
wherein the plurality of clusters includes at least the first cluster operating at a first speed and the second cluster operating at a second speed that is different than the first speed.
However, John discloses:
wherein the plurality of clusters includes at least the first cluster operating at a first speed and the second cluster operating at a second speed that is different than the first speed (John, [0039]).
Both John and AAPA/Miriyala/Xu pertain to the art of networked devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use John’s method to use heterogeneous clusters because it is well-known in the art that heterogeneous computer systems, which combine diverse processing units deliver significantly higher performance, energy efficiency, and task-specific optimization compared to traditional, uniform systems.
As per claim 13, see rejection on claim 2.
Claims 4, 6, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA/Miriyala/Xu as applied above, and further in view of Lo et al (US 12381807 ) (hereinafter Lo).
As per claim 4, AAPA/Miriyala/Xu teaches:
The method of claim 3 (see rejection on claim 3).
AAPA/Miriyala/Xu does not expressly teach:
wherein the connection is a BGP peering connection.
However, Lo discloses:
wherein the connection is a BGP peering connection (Lo, claim 12).
Both Lo and AAPA/Miriyala/Xu pertain to the art of networked devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adopt Lo’s method to use BGP connections because it is well-known in the art that BGP connections provide essential internet routing, offering high stability, fault tolerance, and efficient traffic management for large networks. They enable automatic rerouting around network failures, allow for multi-homing with different ISPs for redundancy, and provide granular control over traffic flow for performance optimization
As per claim 6, AAPA/Miriyala/Xu teaches:
The method of claim 1 (See rejection on claim 1).
AAPA/Miriyala/Xu does not expressly teach:
wherein address information of each GPU included in the plurality of GPU clusters corresponds to a MAC address of the GPU.
However, Lo discloses:
wherein address information of each GPU included in the plurality of GPU clusters corresponds to a MAC address of the GPU (Lo, claim 12).
Both Lo and AAPA/Miriyala/Xu pertain to the art of networked devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adopt Lo’s method to use MAC addresses because it is well-known in the art that MAC addresses provide essential, hardcoded, and unique identification for network devices, enabling reliable local data transmission at the Data Link Layer. Key benefits include enhanced network security through filtering unauthorized devices, efficient device tracking, easier network management, and stable identification that does not change like IP addresses.
As per claim 15, see rejection on claim 4.
As per claim 17, see rejection on claim 6.
Claims 5, 11, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over AAPA/Miriyala/Xu as applied above, and further in view of Srinivasan et al (US 2018/0139127) (hereinafter Srinivasan).
As per claim 5, AAPA/Miriyala/Xu teaches:
The method of claim 1 (see rejection on claim 1).
AAPA/Miriyala/Xu does not expressly teach:
wherein the switch included in the first tier of switches, discards other subsets of the plurality of sets of address information in accordance with the condition.
However, Srinivasan discloses:
wherein the switch included in the first tier of switches, discards other subsets of the plurality of sets of address information in accordance with the condition (Srinivasan, [0051]) .
Both Srinivasan and AAPA/Miriyala/Xu pertain to the art of networked devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adopt Srinivasan’s method to discard address information because it is well-known in the art that memory has limited real estate, and removing unused data would reduce memory usages.
As per claim 11, AAPA/Miriyala/Xu teaches:
The method of claim 1 (see rejection on claim 1).
AAPA/Miriyala/Xu does not expressly teach:
wherein the switch stores the subset of the plurality of sets of address information in an address table, and wherein the switch is further configured to purge an entry from the address table based on a timer associated with the entry.
However, Srinivasan discloses:
wherein the switch stores the subset of the plurality of sets of address information in an address table, and wherein the switch is further configured to purge an entry from the address table based on a timer associated with the entry (Srinivasan, [0051]).
Both Srinivasan and AAPA/Miriyala/Xu pertain to the art of networked devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adopt Srinivasan’s method to purge table entry because it is well-known in the art that tables have limited real estate, and removing unused entry would reduce memory usages.
As per claim 16, see rejection on claim 5.
Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA/Miriyala/Xu as applied above, and further in view of Zuo et al (US 2018/0262446) (hereinafter Zuo).
As per claim 8, AAPA/Miriyala/Xu teaches:
The method of claim 1 (see rejection on claim 1).
AAPA/Miriyala/Xu does not expressly teach:
wherein the third tier of switches are partitioned into a plurality of groups of third tier of switches, and wherein the selecting further comprises selecting at least one target switch from each of the plurality of groups of third tier of switches.
However, Zuo discloses:
wherein the third tier of switches are partitioned into a plurality of groups of third tier of switches, and wherein the selecting further comprises selecting at least one target switch from each of the plurality of groups of third tier of switches (Zuo, [0075]).
Both Zuo and AAPA/Miriyala/Xu pertain to the art of networked devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adopt Zuo’s method to select a group of switches because it is well-known in the art that when a Spine switch is faulty and cannot forward a communication message, another Spine switch may be used to forward or route a communication message between a server (a physical machine or a virtual machine) that is connected to a Leaf switch inside the fin and a server that is connected to a Leaf switch inside another fin.
As per claim 19, see rejection on claim 8.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over AAPA/Miriyala/Xu as applied above, and further in view of Thyagarajan et al (US 11671489) (hereinafter Thyagarajan).
As per claim 9, AAPA/Miriyala/Xu teaches:
The method of claim 1 (See rejection on claim 1).
AAPA/Miriyala/Xu does not expressly teach:
wherein a total number of target switches included in the set of target switches is in a range from 4 to 16.
However, Thyagarajan discloses:
wherein a total number of target switches included in the set of target switches is in a range from 4 to 16 ( Thyagarajan, col 14, ll28-29) .
Both Thyagarajan and AAPA/Miriyala/Xu pertain to the art of networked devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adopt Thyagarajan’s method to use 8 switches because it is well-known in the art that more than one target switch would improve liability, and 8 switches also do not introduce excessive HW costs.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over AAPA/Miriyala/Xu as applied above, and further in view of Nataraja et al (US 2016/0103696) (hereinafter Nataraja)
As per claim 10, AAPA/Miriyala/Xu teaches:
The method of claim 1(see rejection on claim 1).
AAPA/Miriyala/Xu does not expressly teach:
wherein the condition corresponds to grouping, by the target switch, address information of GPUs included in the plurality of GPU clusters based on a VLAN of a customer that a GPU belongs to.
However, Nataraja discloses:
wherein the condition corresponds to grouping, by the target switch, address information of GPUs included in the plurality of GPU clusters based on a VLAN of a customer that a GPU belongs to (Nataraja, [0016]).
Both Nataraja and AAPA/Miriyala/Xu pertain to the art of networked devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adopt Nataraja’s method to group switches based on VLAN because it is well-known in the art that logical grouping of devices enhances network performance by isolating traffic and reducing broadcast domains, which improves speed and efficiency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2015/0131663 teaches a method of routing packets through leaf network devices and spine network devices,.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLIE SUN whose telephone number is (571)270-5100. The examiner can normally be reached 9AM-5PM.
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/CHARLIE SUN/Primary Examiner, Art Unit 2198