DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant's election with traverse of invention I in the reply filed on 04 March 2026 is acknowledged. The traversal is on the ground(s) that no serious search and/or examination burden exists. This is not found persuasive because, as noted in the action dated 20 February 2026, the separate classification thereof and a separate field of search, as the product will not require text strings to the dummy region required by the method, establish a serious search and/or examination burden per MPEP 808.02. The requirement is still deemed proper and is therefore made FINAL. Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 04 March 2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 , 2 , 6-9 and 1 4 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Schaeffer et al. (US 2018/0166324 A1) . Regarding claim 1 , Schaeffer discloses a n integrated circuit element (Fig 8B) comprising: a substrate including a first region (13) and a second region (10) ; a first element (the MOSFET having gate contact 53) in the first region of the substrate and configured to generate an electric field in a horizontal direction (having a lateral channel) ; and a second element (having gate contact 51, either a IGBT or vertical MOSFET depending on the doping of 16) in the second region of the substrate and configured to generate an electric field in a vertical direction, wherein a thickness of the second region is thicker than a thickness of the first region (the oxide 22 not being part of the first region) . Regarding claim 2, Schaeffer discloses that the first element is a metal oxide semiconductor field effect transistor (the left element of Fig 8B is clearly a lateral MOSFET) . Regarding claim 6, Schaeffer discloses that the second element includes at least one of a bipolar junction transistor, a PN junction diode, and an electrostatic discharge element (¶168-¶169, the right element of Fig 8B is either an IGBT or MOS FET depending on the doping of 16) . Regarding claim 7, Schaeffer discloses that the second element includes a PNP-type transistor or an NPN-type transistor , when 16 has same doping type as described in ¶164 to form a MOFET . Regarding claim 8, Schaeffer discloses that the second element comprises: a first well region (15) ; a second well region (14) surrounding side and bottom surfaces of the first well region; and a third well region (10) surrounding side and bottom surfaces of the second well region, and the second well region is doped with a different material than the first well region and the second well region (14 must be oppositely doped in order to form the channel of the MOSFET) . Regarding claim 9, Schaeffer discloses that the second element is configured to move a carrier in a direction perpendicular to an upper surface of the substrate along the first well region, the second well region, and the third well region (flowing from contact 50 to bottom contact 52) . Regarding claim 14, Schaeffer discloses an integrated circuit element (Fig 8B) comprising: a substrate including a first region (13) and a second region (10); a first element (the lateral MOSFET having gate contact 53) on the first region of the substrate; and a second element (the IGBT or vertical MOSFET having gate contact 50) on the second region of the substrate, wherein the first region and the second region of the substrate have different thicknesses (as the first region does not include oxide 22). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 3-5 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schaeffer . Regarding claim 3, Schaeffer discloses that the first element is a lateral device (¶186 & ¶187) while illustrating a lateral MOSFET (Fig 8B). While Schaeffer does not list the specific devices contemplated as the lateral device of Fig 8B, it would have been obvious to one of ordinary skill in the art at the time of filing to select a known device type to use as the lateral device of Schaeffer in order to integrate the given lateral device with a vertical device in the scheme of Schaeffer. Regarding claim 4, Schaeffer discloses that the first element comprises: a source region and a drain region (15) in the first region (13) of the substrate and spaced apart from each other; a gate electrode (to which 53 makes contact) on the first region of the substrate and between the source region and the drain region; and a gate insulation layer (unlabeled in Fig) between the substrate and the gate electrode. Regarding claim 5, Schaeffer discloses that the first element is configured to move a carrier in a direction parallel to the substrate between the source region (connected to 54) and the drain region (connected to 55) . Regarding claim 11, Schaeffer does not disclose that a thickness of the first region of the substrate is 200 nm or more and 300 nm or less, and a thickness of the second region of the substrate is greater than 500 nm and less than 1 μm . However, it would have been obvious to one of ordinary skill in the art at the time of filing to form the substrate to have the regions having the claimed thicknesses, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller , 220 F.2d 454, 105 USPQ 233 (CCPA 1955). Allowable Subject Matter Claims 10, 12, 13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 10, Schaeffer does not disclose the first or second element isolation regions as claimed, nor is there found any prior art which would render that particular arrangement with the devices of Schaeffer obvious. Regarding claims 12, 13, and 15, prior art does not disclose or render obvious the addition of a through via to a first region as found in Schaeffer, especially as the drain electrode of the vertical device region is covering the backside of the first region. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT DANIEL P SHOOK whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7890 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9:00 am - 5:00 pm, Mon-Fri . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT WILLIAM KRAIG can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)272-8660 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL P SHOOK/ Primary Examiner, Art Unit 2896