DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the photoresist pattern" in line 10. There is insufficient antecedent basis for this limitation in the claim since claim 1 rather recites “a first photoresist pattern” and “a second photoresist pattern”. Claims 2-8, which depend from claim 1, are also rejected by virtue of their dependencies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2020/0411318 A1; hereinafter “Lee”) in view of Seong et al. (US 2021/0082924 A1; hereinafter “Seong”).
Regarding claim 1, Lee teaches a method of forming a pattern, the method comprising: forming an etch target layer (130) over a substrate (110) including a first area (AR1) and a second area (AR2) (Fig. 3A and paragraphs 36-37); forming a hardmask structure comprising a plurality of hardmask layers (140 comprising a plurality of hardmask layers), over the etch target layer in the first area and the second area (Fig. 3B and paragraphs 38-40); forming a photoresist layer (150) over the hardmask structure in the first area and the second area (Fig. 3B and paragraph 41); forming a first photoresist pattern (150P1) comprising an engraved pattern in the first area and a second photoresist pattern (150P2) comprising an embossed pattern in the second area from the photoresist layer (Fig. 3C and paragraphs 42-45); forming, in the first area and the second area, an upper hardmask pattern (145P) including a plurality of openings (145O) by transferring a shape of the photoresist pattern to an upper hardmask layer (145) (Fig. 3D and paragraphs 46-47); forming a reversible hardmask pattern (160P) by filling the plurality of openings in the first area (Figs. 3E-3F and paragraphs 48-50); and forming a feature pattern comprising a first pattern (PA) in the first area and a second pattern (PB) in the second area, by transferring a shape of the reversible hardmask pattern to the etch target layer in the first area and transferring a shape of the upper hardmask pattern to the etch target layer in the second area (Figs. 3G-3M and paragraphs 51-60), wherein the first pattern comprises a plurality of island patterns (PA) (Figs. 1-2A and paragraphs 24-31).
While Lee further teaches that the plurality of island patterns 130P(PA) function as landing pads LP for a semiconductor memory device (Fig. 3M, 8A, and 9A and paragraphs 24, 83, and 91), Lee does not further teach a dam structure surrounding the plurality of island patterns. Seong teaches a semiconductor memory device (paragraph 24), comprising a dam structure (a dam structure DM) surrounding a plurality of island patterns (landing pads LP as island patterns) in order to secure structural reliability of the semiconductor memory device (Figs. 1-3 and 9A and paragraphs 14-22 and 105-106). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Lee with that of Seong in order to secure structural reliability of the semiconductor memory device.
Regarding claim 2, Seong teaches wherein the dam structure has a shape and surrounds the first area (Fig. 3).
Regarding claim 3, Seong teaches wherein, the dam structure has a tetragonal ring shape and a vertex with a curvature (Fig. 3).
Regarding claim 4, Lee teaches wherein the plurality of island patterns are spaced apart from each other and form a regular arrangement (Fig. 2A and paragraphs 26-31), and the second pattern comprises a plurality of line patterns having a nonuniform width and length and spaced apart from each other with a space of a nonuniform size therebetween (Fig. 2B and paragraphs 32-35).
Regarding claim 5, Lee teaches wherein the forming of the reversible hardmask pattern comprises forming a reversible hardmask layer (160) over the first area (Fig. 3E and paragraphs 40 and 48). While Lee in view of Seong does not explicitly teach that forming is by atomic layer deposition (ALD) and the reversible hardmask layer comprises an oxide, it would have been obvious to one of ordinary skill in the art to utilize ALD processing as a readily available deposition process with a different hardmask material including oxide material in order to provide the predictable dielectric pattern.
Regarding claim 6, Lee teaches wherein a thickness of the reversible hardmask pattern is about 30 Å to about 300 Å (a thickness of 160P is a thickness of 145, which is 300 Å) (paragraph 40).
Regarding claim 7, Lee teaches wherein a first pattern density in the first area is greater than a second pattern density in the second area (paragraph 24).
Regarding claim 8, Lee teaches wherein the plurality of hardmask layers further comprise a lower hardmask layer (142) and a main hardmask layer (144) arranged between the etch target layer and the upper hardmask layer, and the lower hardmask layer and the main hardmask layer comprise different materials, where the lower hardmask layer is selected from the group consisting of polysilicon, silicon oxide, silicon nitride, and amorphous carbon (paragraphs 39-40).
Regarding claim 9, Lee teaches a method of forming a pattern, the method comprising: forming an etch target layer (130) over a substrate (110) including a first area (AR1) and a second area (AR2) (Fig. 3A and paragraphs 36-37); forming a hardmask structure comprising a plurality of hardmask layers (140 comprising a plurality of hardmask layers), over the etch target layer (Fig. 3B and paragraphs 38-40); forming a first photoresist pattern (150P1) that is an engraved pattern having a planar shape reverse to a planar shape of a first pattern (PA) to be formed in the first area, over the hardmask structure in the first area, and forming a second photoresist pattern (150P2) that is an embossed pattern having a planar shape the same as a planar shape of a second pattern (PB) to be formed in the second area, over the hardmask structure in the second area (Fig. 3C and paragraphs 42-45); and forming the first pattern and the second pattern from the etch target layer by etching the hardmask structure and the etch target layer using the first photoresist pattern and the second photoresist pattern (Figs. 3D-3F and paragraphs 46-50), wherein the first pattern comprises a plurality of island patterns (PA) (Figs. 1-2A and paragraphs 24-31 and 83).
While Lee further teaches that the plurality of island patterns 130P(PA) function as landing pads LP for a semiconductor memory device (Fig. 3M, 8A, and 9A and paragraphs 24, 83, and 91), Lee does not further teach a dam structure planarly surrounding the plurality of island patterns. Seong teaches a semiconductor memory device (paragraph 24), comprising a dam structure (a dam structure DM) planarly surrounding a plurality of island patterns (landing pads LP as island patterns) in order to secure structural reliability of the semiconductor memory device (Figs. 1-3 and 9A and paragraphs 14-22 and 105-106). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Lee with that of Seong in order to secure structural reliability of the semiconductor memory device.
Regarding claim 10, Seong teaches wherein the dam structure surrounds the first area and has a vertex with a curvature (Fig. 3).
Regarding claim 11, Seong teaches wherein each of an outer surface and an inner surface of the dam structure has an even shape (Fig. 1).
Regarding claim 12, Seong teaches wherein an outer surface of the dam structure has an even shape, and an inner surface of the dam structure has an uneven shape (Fig. 3).
Regarding claim 13, Lee teaches wherein the plurality of island patterns each have an upper surface with a circular disc shape and are formed in a honeycomb shape in a horizontal direction (Fig. 2A).
Regarding claim 14, Seong teaches wherein each of an upper surface and a lower surface of the dam structure is at a same vertical level as an upper surface and a lower surface of the plurality of island patterns (Fig. 9A, upper and lower main surfaces of 190D is the same as upper and lower main surfaces of 190).
Regarding claim 15, While Lee in view of Seong teaches a distance from the dam structure to the second pattern closest to the dam structure (Seong, Fig. 1, a distance between DM and GLP), Lee in view of Seong does not explicitly teach that the distance is about 100 nm to about 300 nm. Nevertheless, it would have been obvious to one of ordinary skill in the art to adjust the distance by a routine experimentation in order to obtain the optimal distance, including the claimed distance of about 100 nm to about 300 nm, between the dam structure and the second pattern.
Regarding claim 16, Lee teaches a method of manufacturing a semiconductor memory device, the method comprising: form an etch target layer (130) over a substrate (110) including a memory cell array (AR1) and a peripheral circuit area (AR2) (Figs. 1-3A and paragraphs 24-37); forming a hardmask structure comprising a plurality of hardmask layers (140 comprising a plurality of hardmask layers) over the etch target layer (Fig. 3B and paragraphs 38-40); forming a photoresist layer (150) over the hardmask structure (Fig. 3B and paragraph 41); forming a first photoresist pattern (150P1) comprising an engraved pattern in the memory cell array, and in which a plurality of holes (H1) spaced apart from each other are formed, and a second photoresist pattern (150P2) comprising an embossed pattern in the peripheral circuit area, and having a shape of a plurality of lines (Figs. 2B and 3C and paragraphs 42-45); forming an upper hardmask pattern (145P) including a plurality of openings (145O) in the memory cell array and the peripheral circuit area (Fig. 3D and paragraphs 46-47); forming a reversible hardmask pattern (160P) filling the plurality of openings only in the memory cell array among the memory cell array and the peripheral circuit area (Figs. 3E-3F and paragraphs 48-50); and forming a plurality of island patterns (PA) from the etch target layer in the memory cell array by transferring a shape of the reversible hardmask pattern to the etch target layer, and forming a plurality of line patterns (PB) from the etch target layer in the peripheral circuit area by transferring a shape of the upper hardmask pattern to the etch target layer (Figs. 3G-3M and paragraphs 51-60).
While Lee further teaches that the plurality of island patterns 130P(PA) function as landing pads LP for a semiconductor memory device (Fig. 3M, 8A, and 9A and paragraphs 24, 83, and 91), Lee does not further teach a dam structure. Seong teaches a semiconductor memory device (paragraph 24), comprising a dam structure (a dam structure DM) surrounding a plurality of island patterns (landing pads LP as island patterns) in order to secure structural reliability of the semiconductor memory device (Figs. 1-3 and 9A and paragraphs 14-22 and 105-106). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Lee with that of Seong in order to secure structural reliability of the semiconductor memory device.
Regarding claim 17, Seong teaches wherein the dam structure extends along a side of the memory cell array, surrounds the plurality of island patterns, has a tetragonal ring shape, and has a vertex with a curvature (Fig. 3).
Regarding claim 18, Lee teaches wherein the reversible hardmask pattern is formed over the memory cell array and the peripheral circuit area (Fig. 3E and paragraphs 40 and 48). While Lee in view of Seong does not explicitly teach that forming is by atomic layer deposition (ALD) and the reversible hardmask layer comprises an oxide, it would have been obvious to one of ordinary skill in the art to utilize ALD processing as a readily available deposition process with a different hardmask material including oxide material in order to provide the predictable dielectric pattern.
Regarding claim 19, Lee teaches further comprising: forming a gap-fill hardmask pattern (160P) filling the plurality of openings of the memory cell array and the peripheral circuit area; and removing a gap-fill hardmask pattern in the memory cell array (Figs. 3E-3G and paragraphs 48-51).
Regarding claim 20, Lee in view of Seong teaches wherein an upper surface of each of the plurality of island patterns and the dam structure is at a different vertical level than an upper surface of each of the plurality of line patterns (Lee, Figs. 4A-4C showing different vertical levels for 130P in AR1 and AR2 and Seong, Fig. 1 and paragraph 15 teaching the dam structure DM at the same level as the landing pads LP).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893