Prosecution Insights
Last updated: April 19, 2026
Application No. 18/500,844

HIGH ELECTRON MOBILITY TRANSISTOR

Non-Final OA §102§103
Filed
Nov 02, 2023
Examiner
KUSUMAKAR, KAREN M
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan-Asia Semiconductor Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
825 granted / 949 resolved
+18.9% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
16 currently pending
Career history
965
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
46.4%
+6.4% vs TC avg
§102
32.4%
-7.6% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 949 resolved cases

Office Action

§102 §103
DETAILED ACTION Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/2/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 and 11 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Dasgupta (US 10,658,471). As to claim 1, Dasgupta teaches a high electron mobility transistor (fig. 4B), including: a substrate (205, col. 4:59-61), a buffer layer (col. 4:33-47 and col. 5:13-20 and 43-50, obvious, if not inherent, that there would be a buffer layer for lattice matching), located on the substrate; a gallium nitride layer (230B), located on the buffer layer and forming a channel layer (col. 6:52-60); a two-dimensional material structure (235), located on the channel layer (col. 5:59-65); a covering layer (280), partially covering the two-dimensional material structure (fig. 4B, not described in the specification but obviously an insulating layer of some sort to separate the gate electrode from the source/drain contacts); a drain and a source (450), arranged on the two-dimensional material structure (col. 15:7-10); and a gate (465), arranged on the covering layer (col. 14:65-67). As to claim 11, Dasgupta further teaches the two-dimensional material structure is made of a material selected from a group consisting of MoS2, WS2, α-P, Sb, TiCO2, Hf2CO2, Zr2CO2, BCN, B2Se2, BCP, BP, and Bas (col. 6:1-8). Allowable Subject Matter Claims 2-10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art fails to teach a combination of all of the features in the claims. As to claim 2, Dasgupta fails to teach the two-dimensional material structure includes two connection parts and an extension part, each connection part is connected to the extension part, and each connection parts has a thickness greater than that of the extension part. The 2D material structure is a single-thickness, epitaxially-grown material with no teaching or motivation to vary its thickness. As to claim 12, Dasgupta fails to teach the covering layer is made of aluminum gallium nitride. The purpose of the covering layer is for electrical isolation between the source/drain contacts and the gate electrode. AlGaN would not be used for that purpose. The remaining claims are allowable at least because they depend from allowable claim 2. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any response to this Office Action should be faxed to (571) 273-8300 or mailed to: Commissioner for Patents P.O. Box 1450 Alexandria, VA 22313-1450 Hand-Delivered responses should be brought to: Customer Service Window Randolph Building 401 Dulany Street Alexandria, VA 22313 Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KAREN KUSUMAKAR/ Primary Examiner, Art Unit 2897 3/16/26
Read full office action

Prosecution Timeline

Nov 02, 2023
Application Filed
Mar 16, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SUBSTRATE-INTEGRATED WAVEGUIDE
2y 5m to grant Granted Apr 07, 2026
Patent 12598882
LIGHT EMITTING DISPLAY APPARATUS
2y 5m to grant Granted Apr 07, 2026
Patent 12588564
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12588212
INTEGRATED ASSEMBLIES, AND METHODS OF FORMING INTEGRATED ASSEMBLIES
2y 5m to grant Granted Mar 24, 2026
Patent 12581927
CONTACT OVER ACTIVE GATE STRUCTURES WITH CONDUCTIVE TRENCH CONTACT TAPS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+9.8%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 949 resolved cases by this examiner. Grant probability derived from career allow rate.

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