DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 20 July 2026 has been entered.
The indicated allowability of claim 1 is withdrawn in view of the newly discovered reference(s) on the applicant’s IDS. Rejections based on the newly cited reference(s) follow.
Response to Arguments
The arguments with respect to claim 1 have been considered but are moot for not addressing the references in the present rejection.
Claim 23 appears to be a distinct invention. Since applicant has already received an action on the merits per MPEP 821.03 and 37 CFR 1.145, these claims are not being considered.
Election/Restrictions
Newly submitted claims 23-26 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: The original claims correspond to a digital logic or counter circuit classified in h02m1/0012 and the new claims correspond to a current and voltage control in h02m3/156. Restriction for examination purposes as indicated is proper because all these inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because the following reason applies: the inventions have acquired a separate status in the art in view of their different classification.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 23-36 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for domestic priority based on a parent application filed on 28 December 2021.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 8, 10 are rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being anticipated by Tateshi (US 20060119340).
As to claim 1, Tateshi discloses a circuit comprising: a control circuit having an input and including: a control signal generation circuit having an input (R, S) and an output (Q), the control signal generation circuit configurable to provide a modulated signal at its output responsive to a state of its input; a counter circuit including an input (gate of unlabelled transistor parallel Coff) and an output (output of comparator/XOR gate), wherein the input of the counter circuit is coupled to the output of the control signal generation circuit; and a comparator circuit including a control input (- terminal), a current sense input (+ terminal), and an output, wherein the control input is coupled to the output of the counter circuit (coupled via the ZC latch), and the output of the comparator circuit is coupled to the input of the control signal generation circuit (connected via vout, which feeds back into the control input).
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As to claim 2, Tateshi teaches further comprising a high side transistor having a control terminal coupled to the output of the control signal generation circuit (see image agbove).
As to claim 8, Tateshi teaches wherein the comparator circuit is configurable to adjust a reference signal responsive to a value at the output of the counter circuit (the counter feeds the latch which tells which sensing input to use).
As to claim 10, Tateshi teaches further comprising a current sensor having a first terminal coupled to a terminal of the high-side transistor and a second terminal coupled to a current sense terminal (this would be taught by the comparator sensing the gate signal and comparing to a reference, and senses whether there is current flowing to the HS gate).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 are rejected under 35 U.S.C. 103 as being unpatentable over Tateshi (US 20060119340)
As to claim 3, Tateshi does not explicitly wherein the counter circuit includes an up/down counter. However, going from an analog to digital circuitry is design choice and not patentable (See MPEP 2144.03 and US 5045774 Col. 3, lines 64-67; US 5138250 Claim 6; US 5574635, Col. 5 lines 41-45). The advantages of each are known. Digital control elements are generally easier to synchronize, whereas analog components are generally less bandwidth do not lose data when signals are digitized. The advantages and disadvantages of each are well known to ordinary skill, and therefore choosing one over the other is not patentable.
Allowable Subject Matter
Claims 4, 5, 7, 8, 9, 18, 22 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
Claims 11-17, 19, 20 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 4, the prior art fails to disclose: “wherein the control circuit includes a logic circuit having an input coupled to the output of the control signal generation circuit and having an output coupled to the input of the counter circuit, and the logic circuit is configurable to provide a timeout signal at the output of the logic circuit responsive to an expiration of a time period following a transition of the modulated signal.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 8, the prior art fails to disclose: “wherein the comparator circuit includes:a comparator having the a reference input;a first current source;a first switch coupling the first current source to the reference input, the first switch having a control terminal coupled to the output of the counter circuit;a second current source; anda second switch coupling the second current source to the reference input, the second switch having a control terminal coupled to the output of the counter circuit.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 11, the prior art fails to disclose " a gate control circuit having a first output coupled to the first input of the transistor driver circuit and a second output coupled to the second input of the transistor driver circuit; and a logic circuit having an input coupled to the first output of the gate control circuit and having an output; and a comparator circuit having a current sense input,” in combination with the additionally claimed features, as are claimed by the Applicant.
Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, new claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839
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