DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Remarks
This office action is in response to the amendment/remarks filed on 06/22/2026.
Claims 1-20 are presented for further examination.
Applicant's argument concerning newly added claim limitation is not taught in the cited prior art has been fully considered but moot in view of the new ground(s) of rejection as set forth below. In particular, Applicant argues that Krueger and Cammarota do not teach determining a memory region from an address of a memory access command by querying a region table that maps memory regions to address ranges, followed by retrieval of a region-associated cache parameter. The present rejection further relies on Day for these limitations.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8, 11-13, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Krueger (US 2018/0203807) in view of Cammarota et al. (US 2017/0017576; hereinafter Cammarota), further in view of Day et al. (US 2005/0055507; hereinafter Day).
Regarding independent claims 1, 8 and 12, taking claim 1 as exemplary analysis, Krueger teaches A memory device comprising: a memory array; and a controller (Fig. 13 & [0128], The cache 300 has cache storage (cache RAM) 302 for storing the information to be cached. [0137], a cache controller 312 controls allocation in dependence on a set of resource control parameters which is selected based on the security state and the partition ID of the corresponding memory transaction;
Krueger's cache 300 includes cache RAM 302 having storage entries 304, and a cache controller controls allocation of data into the cache. Krueger further teaches that a memory-system component receives a memory transaction specifying a partition identifier and selects a set of resource-control parameters based on the partition identifier, where the selected parameters control allocation of memory-system resources including cache capacity ([0123]-[0124]) configured to:
receive a cache parameter comprising configuration data for implementing a
[0124], At step 200 the memory system component receives a memory transaction which specifies a partition ID, performance monitoring group and a security state indication as discussed above … At step 206, allocation of resources is controlled using the selected set of resource control parameters, or contention for those resources is managed using the selected set of resource parameters;
[0137], a cache controller 312 controls allocation in dependence on a set of resource control parameters which is selected based on the security state and the partition ID of the corresponding memory transaction. The cache has a set of resource control parameter registers 320 as mentioned above, each register 320 storing the resource control parameters for a corresponding software execution environment. A selector 322 selects one of the registers based on the partition ID and the security state of the incoming memory transaction which requires allocation of data to the cache. The parameters stored in the selected register are used to control whether and how, data is allocated to the cache;
[0140], If an eviction or replacement is required, the partition IDs 314 (and if provided, the victim selection information) stored in each entry of the cache can be used to determine what data evict. It will be appreciated that the above means of counting capacity is just one example and other techniques may also be used to track cache capacity),
Krueger [0126] teaches that each memory-system component supporting resource partitioning may include “a set of parameter registers which store different sets of memory system component parameters,” wherein the control parameters are logically an array indexed by partition ID.
Krueger's cache may restrict allocation to particular portions of cache storage according to parameters associated with the applicable partition ID ([0144]-[0146]). Krueger further teaches replacement or eviction of data associated with a partition when cache-allocation constraints require replacement ([0140], [0143]).
Krueger, however, does not expressly teach that the cache parameter comprises configuration data identifying a cache replacement scheme.
In an analogous art of cache configuration, Cammarota teaches receive a cache parameter comprising configuration data for implementing a cache replacement scheme ([0008], receiving a plurality of cache memory parameters, in which each of the plurality of cache memory parameters are associated with context data, … and at least one cache memory configuration; [0080], An example cache memory configuration vector may be visually represented as a series of cache memory configuration parameters, such as <cache partition size, associativity, cache line size, cache replacement policy>. Values for each cache memory configuration parameters may be used to instruct the cache memory configuration component to create, edit, or remove cache partitions based on the cache memory configuration parameters… the cache memory configuration vector may be visually represented as a series of values of cache memory configuration parameters, such as <16-128K, 2-4 ways 64K, pseudo-least recently used (LRU) or LRU>.
[0081], The example cache memory 900 includes five partitions 934-942. Each cache memory partition 934-942 may be dictated with a different cache memory configuration vector and associated for use by a predicted application within a context for the computing device having the cache memory 900. In an example, each cache memory partition 934-942 may correspond with one of the pairs of threshold hardware data values 806, 810, 814 and cache memory configuration vectors 808, 812, 816 of the groups of cache memory configuration parameters 818-826),
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention was made, with the teachings of Krueger and Cammarota before them, to modify Krueger's partition-specific resource-control parameters to include Cammarota's cache-configuration parameters, including an explicit replacement-policy parameter, because Cammarota teaches that cache partitions may advantageously be independently configured with parameters including partition size, associativity, line size, and replacement policy to adapt cache operation to the workload and desired cache behavior
The combination of Krueger and Cammarota further teaches store the cache parameter in a register file of the controller, the register file storing a plurality of cache parameters, each cache parameter associating the cache parameter with a respective region of the memory array (Krueger [0126] expressly teaches an array/set of parameter registers storing different parameter sets indexed by partition ID.
Krueger [0148]-[0151] further teaches memory-mapped configuration registers, including selector register 364 and configuration registers 366, by which a parameter set is written into a corresponding resource-control-parameter register 320, and alternatively an array of N control-setting registers may be exposed. Cammarota teaches that different cache partitions may have different cache-configuration vectors
Krueger [0126], Each memory system component which supports resource monitoring partitioning may have a set of parameter registers which store different sets of memory system component parameters, which are selected based on the partition ID. The control parameters for a partitioning control are logically an array of control parameters indexed by partition ID. …the configuration software first stores a partition ID to configure into the selector register and then stores the desired control parameters in to the one or more control parameter configuration registers; [0148], The configuration registers 360 include an ID register 362 for identifying hardware capabilities of the cache 300, a selector register 364 for selecting a set of resource control parameters to update, and one or more configuration registers 366 for specifying the parameters to be written to the selected set of resource control parameters),
Krueger and Cammarota do not expressly teach the newly recited limitation:
determine, based on an address included in a memory access command (MAC), which region of the memory array the MAC is accessing, by querying a region table that maps memory regions to address ranges.
Day teaches the missing address-based region-identification mechanism.
Day teaches a CPU/cache subsystem in which different L2-cache replacement strategies are associated with different requested memory-address ranges through range registers and a replacement management table (“RMT”) 160. Day's requested memory address is sent to range registers 140/145 and tested to determine whether the address falls within a predefined range. If the address falls within a defined range, a classID corresponding to the appropriate address range is generated.
Day further teaches that the classID represents a memory region/address range: a missed address is mapped by range registers 140/145 to a classID, the classID is associated with “one or more memory regions or [a] given address range,” and the classID is thereafter used as an index to access RMT 160.
Day's range-register structure expressly stores address-range boundary information. Day teaches a range-start register (“RSR”) and range-mask register (“RMR”), wherein a requested address is masked and compared with the RSR to determine a range hit; the RSR defines the starting address and the RMR defines the address range being tested. Day further teaches repeating the comparison for each address range and generating the classID corresponding to the matching range. Fig. 4; Figs. 5A-5B; Fig. 6; claims 5, 13-14.
Thus, Day teaches or at least renders obvious the claimed region table that maps memory regions to address ranges, because Day maintains a plurality of programmed address-range descriptors and corresponding class identifiers identifying memory regions/classes, queries those descriptors using the requested memory address, and returns the class identifier associated with the matching address range.
It would have been obvious to further modify the Krueger/Cammarota cache-control system to employ Day's address-range classification mechanism so that the applicable cache region and its cache-control parameters are selected based upon the address of the incoming memory transaction. Day expressly teaches that different requested address ranges may employ different replacement strategies. Such modification would have predictably enabled Krueger's per-partition register-based cache controls, as modified by Cammarota's per-partition replacement-policy parameters, to be selected according to the actual memory region addressed by the request rather than only according to software-execution metadata. Day itself identifies the benefit of applying different replacement behavior to different address ranges.
Accordingly, the combination teaches determine, based on an address included in a memory access command (MAC), which region of the memory array the MAC is accessing, by querying a region table that maps memory regions to address ranges, and in response to receiving the MAC, identify the region based on the address, because Day tests the requested memory address against programmed address ranges, determines the matching range, and generates the classID corresponding to that range.
The combination further teaches retrieve from the register file the cache parameter associated with the identified region (
Day teaches that the classID generated from the address-range lookup is used as an index into a corresponding row of RMT 160, from which replacement information is read.
Krueger teaches the analogous hardware organization in which a region/partition identifier indexes an array of corresponding parameter registers, while Cammarota teaches different configuration vectors for different cache partitions. Thus, a POSITA applying Day's address-derived region identifier to the Krueger/Cammarota architecture would use the address-derived identifier to select/retrieve the corresponding region-associated parameter set.
Day additionally provides independent reinforcement for the last limitation. Day teaches that RMT rows are indexed by classID and include an algorithm bit “a” that specifies the replacement algorithm to be used for the class. Day expressly discloses LRU and alternatives such as MRU and FIFO. Day then uses the retrieved RMT information to determine cache replacement eligibility and overwrite an eligible cache line. Fig. 7; claims 1-2, 6-7, 10-11, 20-21.
Therefore, the combination teaches process the MAC by implementing the cache replacement scheme identified by the retrieved cache parameter for data stored in the allocated region through Cammarota's explicit region-specific LRU/pseudo-LRU replacement-policy parameter, reinforced by Day's class-specific algorithm bit and replacement-management information. Accordingly, claim 1 is unpatentable over Krueger in view of Cammarota and further in view of Day.
Regarding independent claim 8, Krueger teaches A system (Figs. 1-3, system) comprising: … (Claim recites substantially the same limitations as in claim 1 and is therefore rejected for the same reasons set forth in the analysis of claim 1).
Additionally, the combination of Krueger, Cammarota and Day teaches the system comprising a solid-state storage device; a volatile memory array (Cammarota [0040], memories 16 may be configured to temporarily hold a limited amount of data and/or processor-executable code instructions that are requested from non-volatile memory, loaded to the memories 16 from non-volatile memory); and … processing the MAC by causing the controller to persist a portion of the volatile memory array to the storage device while implementing the retrieved replacement policy (
Krueger teaches that when cached data is evicted, a write-back transaction may be generated to a further cache or memory, and Krueger expressly teaches victim-selection/eviction behavior for cache entries ([0120], [0128]-[0135], [0140], [0143]).
Day likewise teaches that, upon a miss, information in an eligible cache set is overwritten as a function of the retrieved replacement-control information and selected replacement algorithm. Day supplies the newly recited address-derived region-identification path in the same manner discussed for claim 1: requested address → range-register lookup → corresponding classID → class-indexed replacement information.)
Accordingly, claim 8 is unpatentable over Krueger in view of Cammarota and further in view of Day.
Regarding independent claim 12, Krueger, Cammarota, and Day teach the common address-based region-identification, register-file retrieval, and region-specific replacement-scheme limitations for the reasons discussed with respect to claim 1.
With respect to the cache parameter comprising a cache property defining a cache type, Cammarota [0035]-[0036] teaches cache-configuration parameters including activation/deactivation, reservation for a particular use, size, level-usage settings, associativity, line size, and management policy, used to configure an entire cache or portions/partitions thereof. Cammarota [0080] further teaches that configurable cache elements include cache ways, sets, words, lines, pages, partitions, banks, and cache levels, together with management-policy parameters. These teachings provide cache properties defining how/type of cache resources are configured.
Day additionally teaches in Fig. 3 & [0035] a bypass bit specifying whether data of a given class is cached at a particular level of the cache hierarchy and an algorithm bit specifying the replacement algorithm applicable to that class, thus reinforcing class/region-specific cache behavior. Accordingly, the combination teaches managing the identified region according to a cache property/type and applying the replacement scheme identified by the region-associated cache parameter.
Therefore, claim 12 is unpatentable over Krueger in view of Cammarota and further in view of Day.
Regarding claim(s) 2, the combination further teaches wherein receiving the cache parameter further comprises receiving the cache parameter and a size of memory, wherein the region of the memory array is allocated based on the size of memory (Cammarota, [0055], Partitioning the system cache memory space may result in cache memory partitions of various sizes and locations in the system cache memory space. The size, location, and other aspects of the cache memory partitions may be dictated by the cache memory configuration parameters; [0080], An example cache memory configuration vector may be visually represented as a series of cache memory configuration parameters, such as <cache partition size, associativity, cache line size, cache replacement policy>. Values for each cache memory configuration parameters may be used to instruct the cache memory configuration component to create, edit, or remove cache partitions based on the cache memory configuration parameters… the cache memory configuration vector may be visually represented as a series of values of cache memory configuration parameters, such as <16-128K, 2-4 ways 64K, pseudo-least recently used (LRU) or LRU>).
Regarding claim(s) 3, the combination further teaches wherein allocating the region of memory array comprises selecting the region based on the cache parameter (Cammarota, [0055], Partitioning the system cache memory space may result in cache memory partitions of various sizes and locations in the system cache memory space. The size, location, and other aspects of the cache memory partitions may be dictated by the cache memory configuration parameters; [0080], An example cache memory configuration vector may be visually represented as a series of cache memory configuration parameters, such as <cache partition size, associativity, cache line size, cache replacement policy>. Values for each cache memory configuration parameters may be used to instruct the cache memory configuration component to create, edit, or remove cache partitions based on the cache memory configuration parameters… the cache memory configuration vector may be visually represented as a series of values of cache memory configuration parameters, such as <16-128K, 2-4 ways 64K, pseudo-least recently used (LRU) or LRU>).
Regarding claim(s) 4, the combination further teaches wherein the cache parameter comprises one of an SSD-backed parameter, a large page size parameter, a cache size parameter, a cache associativity type parameter, a locality parameter, and a high bandwidth parameter (Cammarota, [0055], Partitioning the system cache memory space may result in cache memory partitions of various sizes and locations in the system cache memory space. The size, location, and other aspects of the cache memory partitions may be dictated by the cache memory configuration parameters; [0080], An example cache memory configuration vector may be visually represented as a series of cache memory configuration parameters, such as <cache partition size, associativity, cache line size, cache replacement policy>. Values for each cache memory configuration parameters may be used to instruct the cache memory configuration component to create, edit, or remove cache partitions based on the cache memory configuration parameters… the cache memory configuration vector may be visually represented as a series of values of cache memory configuration parameters, such as <16-128K, 2-4 ways 64K, pseudo-least recently used (LRU) or LRU>).
Regarding claim(s) 5, the combination further teaches wherein processing the MAC based on the cache parameter comprises modifying the MAC prior to accessing the region of memory (Cammarota, [0036], The cache memory configuration engine may modify the configuration of a cache memory by modifying the cache configuration memory parameters (e.g., cache memory activation/deactivation, reservation for a particular use, size, level usage settings, associativity, line size, and management policy) of the cache memory as provided from the second classification model).
Regarding claim(s) 6, the combination further teaches wherein modifying the MAC prior to accessing the region of memory comprises: supplementing an address in the MAC with an age bit ( Krueger, [0150], When setting the set of resource control parameters for a given partition ID, software writes that partition ID to the selector register 364 and the parameters to be written to the corresponding configuration registers 366, by issuing memory transactions specifying the memory addresses mapped to those registers 364, 366. In response, the cache 300 reads the parameters from the configuration registers 366 and writes them to the corresponding resource control parameter register 320 identified by the relevant partition ID.
Cammarota [0033], state information may include a variety of parameters including general historic usage information (e.g., types of usage at various locations {address} and times {age})) and transferring an oldest entry in the region of the memory array to a persistent storage device prior to writing data received in the MAC (Cammarota [0080], cache memory configuration parameters, such as <cache partition size, associativity, cache line size, cache replacement policy>. Values for each cache memory configuration parameters may be used to instruct the cache memory configuration component to create, edit, or remove cache partitions based on the cache memory configuration parameters… the cache memory configuration vector may be visually represented as a series of values of cache memory configuration parameters, such as <16-128K, 2-4 ways 64K, pseudo-least recently used (LRU) or LRU>).
Regarding claim(s) 7, the combination further teaches wherein the MAC comprises one of a read or write command (Krueger [0150], When setting the set of resource control parameters for a given partition ID, software writes that partition ID to the selector register 364 and the parameters to be written to the corresponding configuration registers 366, by issuing memory transactions specifying the memory addresses mapped to those registers 364).
Regarding claim(s) 11, the combination further teaches wherein the at least one cache parameter is defined for an individual process (Krueger, [0059], individual parts of a single processes (e.g. different functions or sub-routines) can be regarded as separate execution environments and allocated separate partition IDs. For example, FIG. 5 shows an example where virtual machine VM 3 and the two applications 3741, 3974 executing under it are all allocated PARTID 1, a particular process 3974 executing under a second virtual machine, VM 7, is allocated PARTID 2, and the VM7 itself and another process 1473 running under it is allocated PARTID 0; [0128], On evictions of data from the cache, the ID fields 314, 316, 318 are used to derive the partition ID, performance monitoring group ID and security state indication for the write back transaction; [0140], If an eviction or replacement is required, the partition IDs 314 (and if provided, the victim selection information) stored in each entry of the cache can be used to determine what data evict;
Cammarota [0080], An example cache memory configuration vector may be visually represented as a series of cache memory configuration parameters, such as <cache partition size, associativity, cache line size, cache replacement policy>. Values for each cache memory configuration parameters may be used to instruct the cache memory configuration component to create, edit, or remove cache partitions based on the cache memory configuration parameters… the cache memory configuration vector may be visually represented as a series of values of cache memory configuration parameters, such as <16-128K, 2-4 ways 64K, pseudo-least recently used (LRU) or LRU>).
Regarding claim(s) 13, the combination further teaches wherein the cache type comprises a cache replacement scheme comprising one of first in first out (FIFO), last in first out (LIFO), first in last out (FILO), least recently used (LRU), time aware least recently used (TLRU), least frequently used (LFU) schemes (Cammarota [0080], An example cache memory configuration vector may be visually represented as a series of cache memory configuration parameters, such as <cache partition size, associativity, cache line size, cache replacement policy>. Values for each cache memory configuration parameters may be used to instruct the cache memory configuration component to create, edit, or remove cache partitions based on the cache memory configuration parameters… the cache memory configuration vector may be visually represented as a series of values of cache memory configuration parameters, such as <16-128K, 2-4 ways 64K, pseudo-least recently used (LRU) or LRU>).
Regarding claim(s) 19, the combination further teaches wherein cache configuration registers configured to store microcode associated with cache parameters (Cammarota, [0055], The system cache controller 404 may include hardware, such as a number of registers, configured to maintain records of these cache memory partitions and relate various traits/features/parameters to each of the cache memory partitions; [0067], [0080] An example cache memory configuration vector may be visually represented as a series of cache memory configuration parameters, such as <cache partition size, associativity, cache line size, cache replacement policy>. Values for each cache memory configuration parameters may be used to instruct the cache memory configuration component to create, edit, or remove cache partitions based on the cache memory configuration parameters… the cache memory configuration vector may be visually represented as a series of values of cache memory configuration parameters, such as <16-128K, 2-4 ways 64K, pseudo-least recently used (LRU) or LRU>).
Regarding claim(s) 20, the combination further teaches wherein the microcode includes one or more of a replacement policy, an eviction policy, microcode for tracking cache line locality, microcode for determining cache line use frequency, and microcode governing cache tagging (Krueger [0126], Each memory system component which supports resource monitoring partitioning may have a set of parameter registers which store different sets of memory system component parameters, which are selected based on the partition ID. The control parameters for a partitioning control are logically an array of control parameters indexed by partition ID. …the configuration software first stores a partition ID to configure into the selector register and then stores the desired control parameters in to the one or more control parameter configuration registers; [0148], The configuration registers 360 include an ID register 362 for identifying hardware capabilities of the cache 300, a selector register 364 for selecting a set of resource control parameters to update, and one or more configuration registers 366 for specifying the parameters to be written to the selected set of resource control parameters; Cammarota [0067], [0080] An example cache memory configuration vector may be visually represented as a series of cache memory configuration parameters, such as <cache partition size, associativity, cache line size, cache replacement policy>. Values for each cache memory configuration parameters may be used to instruct the cache memory configuration component to create, edit, or remove cache partitions based on the cache memory configuration parameters… the cache memory configuration vector may be visually represented as a series of values of cache memory configuration parameters, such as <16-128K, 2-4 ways 64K, pseudo-least recently used (LRU) or LRU>).
Claim(s) 9 are rejected under 35 U.S.C. 103 as being unpatentable over Krueger (US 2018/0203807) in view of Cammarota et al. (US 2017/0017576; hereinafter Cammarota) and Day et al. (US 2005/0055507; hereinafter Day), further in view of Bauer et al. (US 8151077; hereinafter Bauer).
Regarding claim(s) 9, Krueger, Cammarota and Day do not expressly teach, in an analogous art of cache management, Bauer teaches wherein persisting the portion of volatile memory array comprises implementing a write-through cache or write-back cache (col. 21, ll. 44-57, Cache parameters configured by application and device best practices may include one or more of the following: overall cache size for the application, amount dedicated to write cache, amount dedicated to read cache, caching algorithms appropriate for the application (e.g., write through, write back, least recently used (LRU), most recently used (MRU)), page size, whether high availability (HA) is needed, whether cache needs to be crash-resistant, cache protection strategy (e.g., mirrored, flash-based, not mirrored), prioritization (which may also be time based), application aware prefetching and flushing (e.g., by file type), read ahead, file level vs. block caching (which can be even more complicated and it can be important to do tuning and configuring for the user)).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention was made, with the teachings of Krueger, Cammarota, Day and Bauer before them, to improve Krueger, Cammarota and day’s caching policies permit an application to control caching of data with Bauer’s Cache parameters configured by application including write through, write back for the motivation of a very flexible and powerful technique for determining caching behavior based on data accesses.
Claim(s) 10 are rejected under 35 U.S.C. 103 as being unpatentable over Krueger (US 2018/0203807) in view of Cammarota et al. (US 2017/0017576; hereinafter Cammarota) and Day et al. (US 2005/0055507; hereinafter Day), further in view of Kelly et al. (US 2021/0406145; hereinafter Kelly).
Regarding claim(s) 10, Krueger, Cammarota and Day do not expressly teach, in an analogous art of cache management, Kelly teaches wherein persisting the portion of volatile memory array comprises implementing a first set of pages of the volatile memory array as write-through caches and a second set of pages of the volatile memory array as write-back caches ([0021], a cache policy controls when modified copies of data are written back to lower level caches and/or memory, such as with a write-through or write back cache policy;
[0027], a test region includes a block, portion, or section of memory circuitry in the cache that is used for performing cache operations using a given configuration of a combination of two or more cache policies being tested. In some embodiments, the testing of two or more configurations of combinations of two or more cache policies is performed simultaneously in separate test regions in the cache, possibly with a separate test region being used for each available configuration of the combination of two or more cache policies. For example, assuming that each of cache policies A and B (e.g., a write-through policy and a replacement policy, etc.) can each be used in a first configuration (0) or a second configuration (1), four separate test regions can be used to test the following configurations of the combination of cache policies A and B: 00, 01, 10, and 11).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention was made, with the teachings of Krueger, Cammarota, Day and Kelly before them, to improve Krueger, Cammarota and Day’s caching policies permit an application to control caching of data with Kelly’s cache policy including write through, write back policy and the different policies can be performed simultaneously in separate test regions in the cache for the motivation of a very flexible and powerful technique for determining caching behavior based on data accesses.
Claim(s) 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Krueger (US 2018/0203807) in view of Cammarota et al. (US 2017/0017576; hereinafter Cammarota) and Day et al. (US 2005/0055507; hereinafter Day), further in view of Robinson (US 2007/0233964).
Regarding claim(s) 14, the combination of Krueger, Cammarota and Day further teaches wherein the cache type comprises a LRU type (Cammarota [0067], [0080] values of cache memory configuration parameters, such as <16-128K, 2-4 ways 64K, pseudo-least recently used (LRU) or LRU>).
Krueger, Cammarota and Day do not expressly teach, in an analogous art of cache management, Roberson teaches managing a portion of the volatile memory array based on the cache type comprises adding an age bit to data written to the volatile memory array ([0013], The age bits can be used to register the age of each line within a set (e.g., the age bits can be used to register a relative length of time since the line was last accessed). For example, all age bits for a particular line can be reset to “0”, when that line is accessed; [0015], These replacement policies can include, but are not limited to, selecting the least recently used (LRU) line based upon a comparison of the age bits of each line within the set).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention was made, with the teachings of Robinson, Krueger, Cammarota and Day before them, to improve Krueger, Cammarota and Day’s replacement policy based on a least recently used (LRU) algorithm with Robinson’s age bits used to register the age of each line within a set for the motivation that age bits can be used to register a relative length of time since the line was last accessed (Robinson, [0013])
Regarding claim(s) 15, the combination of Krueger, Cammarota, Day and Robinson further teaches wherein adding the age bit is performed for write operations (Mu, col. 15, ll. 13-17, request parameters related to a write request are analyzed and compared against caching definitions 136 to determine when specific data modified in write cache 144 should be flushed to mass storage device 114; Robison, [0013], The age bits can be used to register the age of each line within a set (e.g., the age bits can be used to register a relative length of time since the line was last accessed). For example, all age bits for a particular line can be reset to “0”, when that line is accessed; [0015], These replacement policies can include, but are not limited to, selecting the least recently used (LRU) line based upon a comparison of the age bits of each line within the set).
Regarding claim(s) 16, the combination of Krueger, Cammarota, Day and Robinson further teaches wherein managing a portion of the volatile memory array based on the cache type comprises identifying an oldest entry in the volatile memory array based on age bits of data in the volatile memory array (Robinson, [0013], The age bits can be used to register the age of each line within a set (e.g., the age bits can be used to register a relative length of time since the line was last accessed). For example, all age bits for a particular line can be reset to “0”, when that line is accessed; [0015], These replacement policies can include, but are not limited to, selecting the least recently used (LRU) line based upon a comparison of the age bits of each line within the set).
Regarding claim(s) 17, the combination of Krueger, Cammarota, Day and Robinson further teaches wherein managing a portion of the volatile memory array based on the cache type comprises transferring the oldest entry to the solid-state storage device (Robinson, [0013], The age bits can be used to register the age of each line within a set (e.g., the age bits can be used to register a relative length of time since the line was last accessed). For example, all age bits for a particular line can be reset to “0”, when that line is accessed; [0015], These replacement policies can include, but are not limited to, selecting the least recently used (LRU) line based upon a comparison of the age bits of each line within the set).
Regarding claim(s) 18, the combination of Krueger, Cammarota, Day and Robinson further teaches wherein managing a portion of the volatile memory array based on the cache type comprises writing new data to the volatile memory array and setting its age bit to zero (Robinson, [0013], The age bits can be used to register the age of each line within a set (e.g., the age bits can be used to register a relative length of time since the line was last accessed). For example, all age bits for a particular line can be reset to “0”, when that line is accessed; [0015], These replacement policies can include, but are not limited to, selecting the least recently used (LRU) line based upon a comparison of the age bits of each line within the set).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/TRACY C CHAN/ Primary Examiner, Art Unit 2138
