Prosecution Insights
Last updated: August 17, 2026
Application No. 18/501,048

CHARGING CONTROL CIRCUIT

Non-Final OA §102§103
Filed
Nov 03, 2023
Priority
Feb 20, 2023 — TW 112106075
Examiner
TARDIF, DAVID P
Art Unit
Tech Center
Assignee
ASUSTeK Computer Inc.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
378 granted / 526 resolved
+11.9% vs TC avg
Moderate +10% lift
Without
With
+10.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
18 currently pending
Career history
543
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
64.1%
+24.1% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
4.5%
-35.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 526 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Priority claim to TW112106075 is acknowledged. Information Disclosure Statement The information disclosure statement (IDS) submitted on11/03/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 1. Claims 1-3 and 5-6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Melanson (2008/0048618). As to claim 1: Melanson teaches a charging control circuit, comprising: a battery module configured to provide a power supply voltage in a shipping mode (figure 1, 10); an oscillator configured to generate an oscillation signal according to the power supply voltage (paragraph 0027, element 40); a charge pump (16 and 16A) configured to receive the power supply voltage and boost the power supply voltage in response to the oscillation signal (paragraph 0027, pulse signals charge pumps to vias the bulk and gate), thereby providing an output voltage to a positive terminal of the battery module (paragraphs 0021 and 0028 explain that the charge pump is connected to the positive terminal of the battery module and selectively provides output); and a first switch circuit coupled between the battery module, the oscillator, and the charge pump (switches S40, S42, S41 and S43, figure 5, paragraph 0026, controlled by switch circuit 42 which is between the battery, oscillator and switches) and configured to be turned on according to a first switch signal to provide the power supply voltage to the oscillator and the charge pump (paragraphs 0026-0027). As to claim 2: Melanson teaches that the output voltage exceeds a first threshold value for a specified time, the battery module releases the shipping mode (claim 2, paragraph 0025, wherein a mode change occurs when the current reaches a certain level threshold, and further explaining this is within a certain time period, figure 6). As to claim 5: Melanson teaches a detection circuit coupled to the positive terminal of the battery module and configured to generate a second switch signal according to a battery voltage on the positive terminal; and a second switch circuit coupled to the positive terminal of the battery module and the detection circuit and configured to be turned on according to the second switch signal to provide the battery voltage to a load (switch S43, wherein paragraph 0027 explains that switch S43 operates on a separate threshold from S40, S42). As to claim 6: Melanson teaches that when the second switch circuit is turned off, when the battery voltage is greater than a second threshold value, the detection circuit outputs the second switch signal of a first logic level to turn on the second switch circuit, when the second switch circuit is turned on, when the battery voltage is less than a third threshold value, the detection circuit outputs the second switch signal of a second logic level to turn off the second switch circuit, wherein the second threshold value is greater than the third threshold value (as seen in figure 6, the two threshold values are considered to be Vbb and Vbboost, wherein the boost voltage is a level greater than the other threshold value, wherein the “first threshold value” is considered to be the minimum allowable charge). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 2. Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Melanson (2008/0048618) as applied to claim 1, and further in view of Muramatsu (10,560,017). The teachings of Melanson are discussed above. As to claim 3: Melanson teaches the limitations of claim 1. Melanson is silent as to a power button; and a logic circuit, wherein a first input end thereof is coupled to the power button, an output end thereof is coupled to the first switch circuit, and when the power button is detected to be pressed, the logic circuit outputs the first switch signal of a first logic level to turn on the first switch circuit. Muramatsu teaches a power button (column 4, lines 8-29); and a logic circuit, wherein a first input end thereof is coupled to the power button, an output end thereof is coupled to the first switch circuit, and when the power button is detected to be pressed, the logic circuit outputs the first switch signal of a first logic level to turn on the first switch circuit (column 4, lines 8-29, explaining a button pressed causes an on/off control of the power supply switch to activate, and turn on the power supply). It would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to modify the teachings of Melanson with the teachings of Muramatsu so that the battery pump and switch is operated by button to add external actuation of the battery, which adds the ability to operate the device in a special mode which is not indicated by internal power and time readings (Muramatsu, column 4, lines 8-29). Muramatsu and Melanson are highly overlapping fields of endeavor, both explaining a battery charge and pump system, wherein it is well known the in art that electrically powered and battery devices operate with the aid of a button. It would not require undue testing to combine these references as a result. As to claim 4: Muramatsu teaches that a second input end of the logic circuit receives a reset signal, the logic circuit outputs the first switch signal of a second logic level to turn off the first switch circuit (Muramatsu, column 4, lines 8-29, that the button depress both turns off and turns on the switch circuit). The following references are not relied upon in the applied rejections, but are considered pertinent art, and are being added for the purposes of expediting prosecution: Koc (2024/0066301) Bolz (7,714,544) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID P TARDIF whose telephone number is (571)270-7810. The examiner can normally be reached on M-F 11AM-7:30PM. If the examiner cannot be reached by telephone, he can be reached through the following email address: david.tardif@uspto.gov If attempts to reach the examiner by telephone and email are unsuccessful, the examiner’s supervisor, Thomas Pham can be reached on (571)272-3689. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form. DAVID TARDIF Examiner Art Unit 2876 /DAVID TARDIF/ Examiner, Art Unit 2876 david.tardif@uspto.gov /THOMAS K PHAM/Supervisory Patent Examiner, Art Unit 2876
Read full office action

Prosecution Timeline

Nov 03, 2023
Application Filed
Jul 27, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
82%
With Interview (+10.4%)
3y 0m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 526 resolved cases by this examiner. Grant probability derived from career allowance rate.

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