DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections Claims 1, 7, 10, 13 , 17 and 20 are objected to because of the following informalities: In claim 1 line 8, “the second side” ---, should be corrected to ---, “the first side” ---. In claim 7 lines 2-3, “ to the first electrode of the capacitor and the second surface of the resistor being coupled to the first power rail” ---, should be corrected to ---, “to the second electrode of the capacitor and the second surface of the resistor being coupled to the second power rail” ---. In claim 10 line 3, “the first ” ---, should be corrected to ---, “the second ” ---. In claim 10 line 3, “the second ” ---, should be corrected to ---, “the first ” ---. In claim 13 line 7, “ the backside ” ---, should be corrected to ---, “the frontside ” ---. In claim 17 line 12, “the second side” ---, should be corrected to ---, “the first side” ---. In claim 20 lines 2-3, “to the first electrode of the capacitor and the second surface of the resistor being coupled to the first power rail” ---, should be corrected to ---, “to the second electrode of the capacitor and the second surface of the resistor being coupled to the second power rail” ---. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7, 9-10, 12-15 and 17-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Makiyama et al (US Publication No. 20120061761). Regarding claim 1 , Makiyama discloses a semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown below, para. [0105]- [0108]), comprising: a transistor device (T) at a first side (side1) of the semiconductor structure (ESD) ; a control circuit (Y) at the first side (side1) of the semiconductor structure (ESD) ; and a resistor-capacitor circuit (X) comprising a resistor (R1) and a capacitor (C1) ; wherein the resistor (R1) is in a power delivery network (i.e., PW; for instance, mid terminal PW distinguishes between side1 and side2 ) at a second side (side2) of the semiconductor structure (ESD) and the capacitor (C1) is at the first side (side1) of the semiconductor structure (ESD) ; wherein a first electrode (E1) of the capacitor (C1) is coupled to a first power rail (P1) in the power delivery network (i.e., PW; for instance, mid terminal PW distinguishes between side1 and side2) at the second side (i.e., as second to be corrected to first and that is side1) of the semiconductor structure (ESD) ; wherein a second electrode (E2) of the capacitor (C1) is coupled (i.e., E2 of C1 is coupled to P2 via R1) to a second power rail (P2) in the power delivery network (i.e., PW; for instance, mid terminal PW distinguishes between side1 and side2) at the second side (side2) of the semiconductor structure (ESD) ; wherein an input (A) of the control circuit (Y) is coupled to the resistor (R1) ; and wherein a gate (G) of the transistor device (T) is coupled to an output (B) of the control circuit (Y). center 2137276 Regarding claim 2 , Makiyama discloses the semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; wherein the first power rail (P1) is coupled to a ground voltage (GND) and the second power rail (P2) is coupled to a positive supply voltage (VCC). Regarding claim 3 , Makiyama discloses the semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; wherein a source (S) of the transistor device (T) is coupled to the first power rail (P1) and a drain (D) of the transistor device (T) is coupled to the second power rail (P2). Regarding claim 4 , Makiyama discloses the semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; wherein the first electrode (E1) of the capacitor (C1) is coupled to the first power rail (P1) through at least one via interconnecting (i.e., such as interconnecting as of coupling the internal components to fabricate the external interface of the IC chips; for instance, FIG. 5 illustrates the details of the ESD protection circuit portion (ESD) in FIG. 3. As illustrated in FIG. 5, for example, the following are coupled between the high-voltage power supply potential and the ground potential: a series coupled circuit of a polysilicon resistor R1 and a capacitor CHSM3 (for example, that having the same structure as the n-channel high-breakdown voltage symmetric MOS capacitors CHSM1, CHSM2 and the like); a high-breakdown voltage asymmetric low-Vth CMISFET inverter group INVALG (group of series coupled multiple inverters) that receives the potential at the intermediate point of this series coupled circuit and is made up of multiple source/drain asymmetric high-breakdown voltage MISFET pairs; an n-channel high-breakdown voltage asymmetric low-Vth MISFET (QNHAL4) that short-circuits the high-voltage power supply potential and the ground potential by the output of the high-breakdown voltage asymmetric low-Vth CMISFET inverter group INVALG; an ESD protection diode Dl; and the like. When power supply voltage is normally applied to this ESD protection circuit portion (ESD), the potential at the intermediate point between the polysilicon resistor R1 and the capacitor CHSM3 is high. As a result, the output of the series coupled multiple inverter group INVALG is low and the shunt MISFET (QNHAL4) is off; see for example fig. 5, para. [0105]) the first power rail (P1) and one or more back-end-of-line interconnects (i.e., such as back-end-of-line interconnects; for instance, the BEOL process begins with the formation of an M1 wiring layer and ranges to the formation of pad openings in a final passivation film over an aluminum pad electrode or so. (In case of wafer level package process, that process is also included.) In the FEOL process, gate electrode patterning step, contact hole formation step, and the like are micromachining steps calling for especially minute processing. In the BEOL process, meanwhile, via and trench formation step, especially, local wiring in relatively low layers and the like calls for especially minute processing. (Examples of local wiring in relatively low layers are the following fine buried wiring: fine buried wiring of M1 to M3 or so for buried wiring with a configuration of four layers or so and fine buried wiring of M11 to M5 or so for buried wiring with a configuration of 10 layers or so.) "MN (usually, N=1 to 15 or so)" denotes wiring in the Nth layer from bottom. M1 denotes wiring in the first layer and M3 denotes wiring in the third layer; see for example fig. 5, para. [0065]) at the first side (side1) of the structure (i.e., such as the structure; for instance, when a term of "semiconductor device" or "semiconductor integrated circuit device" is used in this specification, it mainly refers to various types of single transistors (active elements) and what is obtained by integrating a resistor, a capacitor, or the like over a semiconductor chip or the like (for example, a single crystal silicon substrate) with them at the center. A representative example of various types of transistors is MISFET (Metal Insulator Semiconductor Field Effect Transistor) typified by MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A representative example of integrated circuitry is CMIS (Complementary Metal Insulator Semiconductor) integrated circuit typified by CMOS (Complementary Metal Oxide Semiconductor) integrated circuit obtained by combining an n-channel MISFET and a p-channel MISFET. Wafer processes for today's semiconductor integrated circuit devices, that is, LSI (Large Scale Integration) are usually roughly classified into FEOL (Front End of Line) process and BEOL (Back End of Line) process. The FEOL process ranges from carrying-in of silicon wafers as raw material to pre - metal process (process made up of the formation of an interlayer insulating film or the like between the lower end of an Ml wiring layer and a gate electrode structure, the formation of contact holes, tungsten plug, embedding, and the like) or so; see for example fig. 5, para. [0064]) . Regarding claim 5 , Makiyama discloses the semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; wherein the gate (G) of the transistor device (T) is coupled to the output (B) of the control circuit (Y) through one or more back-end-of-line interconnects (i.e., such as back-end-of-line interconnects; for instance, the BEOL process begins with the formation of an M1 wiring layer and ranges to the formation of pad openings in a final passivation film over an aluminum pad electrode or so. (In case of wafer level package process, that process is also included.) In the FEOL process, gate electrode patterning step, contact hole formation step, and the like are micromachining steps calling for especially minute processing. In the BEOL process, meanwhile, via and trench formation step, especially, local wiring in relatively low layers and the like calls for especially minute processing. (Examples of local wiring in relatively low layers are the following fine buried wiring: fine buried wiring of M1 to M3 or so for buried wiring with a configuration of four layers or so and fine buried wiring of M11 to M5 or so for buried wiring with a configuration of 10 layers or so.) "MN (usually, N=1 to 15 or so)" denotes wiring in the Nth layer from bottom. M1 denotes wiring in the first layer and M3 denotes wiring in the third layer; see for example fig. 5, para. [0065]) at the first side (side1) of the semiconductor structure (i.e., such as the structure; for instance, when a term of "semiconductor device" or "semiconductor integrated circuit device" is used in this specification, it mainly refers to various types of single transistors (active elements) and what is obtained by integrating a resistor, a capacitor, or the like over a semiconductor chip or the like (for example, a single crystal silicon substrate) with them at the center. A representative example of various types of transistors is MISFET (Metal Insulator Semiconductor Field Effect Transistor) typified by MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A representative example of integrated circuitry is CMIS (Complementary Metal Insulator Semiconductor) integrated circuit typified by CMOS (Complementary Metal Oxide Semiconductor) integrated circuit obtained by combining an n-channel MISFET and a p-channel MISFET. Wafer processes for today's semiconductor integrated circuit devices, that is, LSI (Large Scale Integration) are usually roughly classified into FEOL (Front End of Line) process and BEOL (Back End of Line) process. The FEOL process ranges from carrying-in of silicon wafers as raw material to pre - metal process (process made up of the formation of an interlayer insulating film or the like between the lower end of an M 1 wiring layer and a gate electrode structure, the formation of contact holes, tungsten plug, embedding, and the like) or so; see for example fig. 5, para. [0064]) . Regarding claim 6 , Makiyama discloses the semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; wherein the input (A) of the control circuit (Y) is coupled to the resistor (R1) through one or more vias (i.e., such as one or more vias; for instance, i n the BEOL process, meanwhile, via and trench formation step, especially, local wiring in relatively low layers and the like calls for especially minute processing. (Examples of local wiring in relatively low layers are the following fine buried wiring: fine buried wiring of M1 to M3 or so for buried wiring with a configuration of four layers or so and fine buried wiring of M11 to M5 or so for buried wiring with a configuration of 10 layers or so.) "MN (usually, N=1 to 15 or so)" denotes wiring in the Nth layer from bottom. M1 denotes wiring in the first layer and M3 denotes wiring in the third layer; see for example fig. 5, para. [0065]) formed through a shallow trench isolation region (i.e., such as a shallow trench isolation region; for instance, the asymmetric high-breakdown voltage MISFET region 21 (accurately, n-channel asymmetric high-breakdown voltage MISFET region) is surrounded by the following region in the front surface 1a region of the semiconductor chip 2: an element isolation region, such as an STI (Shallow Trench Isolation) insulating film 23. (Any other isolation scheme is also acceptable.) This surrounded region is designated as active region. Over the active region, there is provided a gate electrode 16 (first gate electrode) with a gate insulating film 15h (high-breakdown voltage portion gate insulating film) in between. A side wall spacer insulating film 17 is provided in the periphery of them. In the front surface 1a of the semiconductor chip 2, a relatively deep high-breakdown voltage portion p-well region 11ph is provided throughout the active region (the active region of the n-channel asymmetric high-breakdown voltage MISFET); see for example fig. 5, para. [0091]) . Regarding claim 7 , Makiyama discloses the semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; wherein the resistor (R1) has a first surface (S1) and a second surface (S2) opposite the first surface (S1) , the first surface (S1) of the resistor (R1) being coupled to the first electrode (i.e., as the first electrode to be corrected to the second electrode and that is E2) of the capacitor (C1) and the second surface (S2) of the resistor (R1) being coupled to the first power rail (i.e., as the first power rail to be corrected to the second power rail and that is P2) . Regarding claim 9 , Makiyama discloses the semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; wherein the control circuit (Y) comprises an inverter (INVALG). Regarding claim 10 , Makiyama discloses the semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; wherein the inverter (INVALG) comprises a complementary metal-oxide-semiconductor inverter (i.e., such as complementary metal-oxide-semiconductor inverter; for instance, a representative example of various types of transistors is MISFET (Metal Insulator Semiconductor Field Effect Transistor) typified by MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A representative example of integrated circuitry is CMIS (Complementary Metal Insulator Semiconductor) integrated circuit typified by CMOS (Complementary Metal Oxide Semiconductor) integrated circuit obtained by combining an n-channel MISFET and a p-channel MISFET; see for example fig. 5, [0064]) comprising a p-type transistor (QPHAL1) and an n-type transistor (QNHAL1) with a shared gate (A) , wherein a source (source/ QPHAL1) of the p-type transistor (QPHAL1) is coupled to the first power rail (i.e., as to be corrected to the second power rail and that is P2) , wherein a drain (drain/QNHAL1) of the n-type transistor (QNHAL1) is coupled to the second power rail (i.e., as to be corrected to the first power rail and that is P 1 ) , and wherein the shared gate (A) provides an input (A) coupled to the resistor (R1). Regarding claim 12 , Makiyama discloses the semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; wherein the transistor device (T) is coupled, in parallel (i.e., T is in parallel with the transistors array K and L) with one or more additional (i.e., array of two MOSFETs K and L) transistor devices (K, L) , between the first power rail (P1) and the second power rail (P2). Regarding claim 13 , Makiyama discloses a n electrostatic discharge clamp circuit (i.e., such as electrostatic discharge clamp circuit ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; comprising: a resistor-capacitor circuit (X) ; a control circuit (Y) ; and an electrostatic discharge clamp device (Z) ; wherein the resistor-capacitor circuit (X) comprises a resistor (R1) in a backside (side2) power delivery network (i.e., PW; for instance, mid terminal PW distinguishes between side1 /frontside and side2 /backside ) and a capacitor (C1) at a frontside (side1) of the electrostatic discharge clamp circuit (ESD) ; wherein the capacitor (C1) has a first electrode (E1) coupled to a first power rail (P1) in the backside (i.e., as to be corrected to frontside and that is side1) power delivery network (i.e., PW; for instance, mid terminal PW distinguishes between side1 /frontside and side2 /backside ); wherein the capacitor (C1) has a second electrode (E2) coupled to a first surface (S1) of the resistor (R1) ; wherein a second surface (S2) of the resistor (R1) , opposite the first surface (S1) of the resistor (R1) , is coupled to a second power rail (P2) in the backside (side2) power delivery network (i.e., PW; for instance, mid terminal PW distinguishes between side1 /frontside and side2 /backside ) ; wherein an input (A) of the control circuit (Y) is coupled to the resistor (R1) ; and wherein the electrostatic discharge clamp device (Z) is coupled to an output (B) of the control circuit (Y). Regarding claim 1 4 , Makiyama discloses the electrostatic discharge clamp circuit (i.e., such as electrostatic discharge clamp circuit ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) . As for the rest of the limitations/features in claim 1 4 is rejected for the same reasons that have already been stated/discussed above in rejected claim 1 0 . {See rejection of claim 10} Regarding claim 15 , Makiyama discloses the electrostatic discharge clamp circuit (i.e., such as electrostatic discharge clamp circuit ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; wherein the electrostatic discharge clamp device (Z) comprises a transistor device (T) coupled between the first power rail (P1) and the second power rail (P2). Regarding claim 17 , Makiyama discloses a n integrated circuit (i.e., such as integrated circuit ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; comprising: an electrostatic discharge clamp circuit structure (i.e., such as electrostatic discharge clamp circuit structure ESD; see for example fig. 5 as shown above , para. [0105]- [0108]) ; the second side (i.e., as to be corrected to the first side and that is side1) ; wherein a second electrode (E2) of the capacitor (C1) is coupled (i.e., E2 of C1 is coupled to P2 via R1) to a second power rail (P2) in the power delivery network (i.e., PW; for instance, mid terminal PW distinguishes between side1 and side2) at the second side (side2) of the electrostatic discharge clamp circuit structure (ESD). As for the rest of the limitations/features in claim 1 7 is rejected for the same reasons that have already been stated/discussed above in rejected claim 1. {See rejection of claim 1} Regarding claim 18 , is rejected for the same reasons that have already been stated/discussed above in rejected claim 2 . {See rejection of claim 2 } Regarding claim 19 , is rejected for the same reasons that have already been stated/discussed above in rejected claim 6 . {See rejection of claim 6 } Regarding claim 20 , is rejected for the same reasons that have already been stated/discussed above in rejected claim 7 . {See rejection of claim 7 } Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Makiyama et al (US Publication No. 20120061761) in view of Kong et al (US Publication No. 20040150026). Regarding claim 8 , Makiyama discloses the semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown above, para. [0105]- [0108]) . Makiyama does not explicitly disclose wherein the capacitor comprises a metal-insulator-metal capacitor. Kong discloses a capacitor structure in a semiconductor device (i.e., such as capacitor structure 100; see for example fig. 2A, para. [0025]- [0032]); wherein the capacitor (i.e., such as capacitor 122; see for example fig. 2A, para. [0025]- [0032]) comprises a metal-insulator-metal capacitor (i.e., such as metal-insulator-metal capacitor as of conductive layer-dielectric layer-conductive layer; for instance, the conductive layer 104 is disposed over and electrically connected with the power rail 108 and extends to a region over the dielectric layer 106. The dielectric layer 106 is defined over the power rail 112 so the conductive layer 104 does not come into direct electrical contact with the power rail 112. A dielectric material 110 may be located between the power rail 108 and the power rail 112 to electrically separate the power rail 108 from the power rail 112. Therefore, as shown in the structure 100, the conductive layer 104 is capable of applying electrical charge from the power rail 108 to a region over the power rail 112. In such an embodiment, the conductive layer 104 is a top plate of a capacitor 122, the dielectric layer 106 is the dielectric of the capacitor 122, and the power rail 112 is a bottom plate of the capacitor 122. In this type of configuration, the conductive layer 104 may be defined over a topmost level of the semiconductor device as discussed in reference to FIG. 3A thereby not interfering with the internal structure of the semiconductor device; see for example fig. 2A, para. [0026]) . Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the MIM capacitor in Makiyama , as taught by Kong, as it provides the advantage of optimizing the circuit design towards high capacitance density, low parasitic capacitance, and low leakage current. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Makiyama et al (US Publication No. 20120061761) in view of Wu et al (US Publication No. 20200168715 ). Regarding claim 11 , Makiyama discloses the semiconductor structure (i.e., such as semiconductor structure ESD; see for example fig. 5 as shown above, para. [0105]- [0108]) . Makiyama does not explicitly disclose wherein the transistor device comprises a nanosheet transistor structure. Wu discloses GAA method and devices (i.e., such as GAA transistor; see for example fig. 19B, para. [0043]); wherein the transistor device (i.e., such as transistor device GAA; see for example fig. 19B, para. [0043 ] ) comprises a nanosheet transistor structure (i.e., such as nanosheet transistor GAA; for instance, after the selective removal of the first semiconductor layers 205a and 205b, the second semiconductor layers 207a and 207b remain in fins 303 and are referred to herein as a first stack of nanosheets 407a and a second stack of nanosheets 407b, respectively. GAA transistor devices using the nanosheet structures can be logic devices, static random-access memory (SRAM) devices, IO devices, electro-static discharge (ESD) devices, or passive devices. In another embodiment, after etching, bottom-most first semiconductor layers 205a and 205b (e.g., SiGe layers) may remain below the upper surface of the STIs 313 as a stress layer within the fins 303a and 303b to provide certain strains or relaxations of the fin materials; see for example fig. 19B, para. [0043]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the nanosheet transistor in Makiyama , as taught by Wu , as it provides the advantage of optimizing the circuit design towards higher performance, lower power consumption, and superior scaling. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Makiyama et al (US Publication No. 20120061761) in view of Verhaege et al (US Publication No. 20020033507). Regarding claim 16 , Makiyama discloses the electrostatic discharge clamp circuit (i.e., such as electrostatic discharge clamp circuit ESD; see for example fig. 5 as shown above, para. [0105]- [0108]) . Makiyama does not explicitly disclose wherein the electrostatic discharge clamp device comprises two or more transistor devices connected in parallel between the first power rail and the second power rail. Verhaege discloses a multi-finger electro-static discharge (ESD) protection circuit (i.e., such as ESD CKT 1400; see for example fig. 14, para. [0104]- [0119]); wherein the electrostatic discharge clamp device (i.e., such as electrostatic discharge clamp device ESD MFT; see for example fig. 14, para. [0104]- [0119]) comprises two or more transistor devices (i.e., such as the array of parallel transistors G1-Gn; see for example fig. 14, para. [0104]- [0119]) connected in parallel (i.e., such as the array of parallel transistors G1-Gn; see for example fig. 14, para. [0104]- [0119]) between the first power rail (i.e., such as first power rail VSS/552; see for example fig. 14, para. [0104]- [0119]) and the second power rail (i.e., such as second power rail Pad/520; see for example fig. 14, para. [0104]- [0119]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the array of transistor in Makiyama , as taught by Verhaege , as it provides the advantage of optimizing the circuit design towards increasing current handling capability, lowers on-resistance to efficiently shunt surge currents to ground, and reduces heat generation per device. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MUAAMAR Q AL-TAWEEL whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0339 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 0730-1700 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MUAAMAR QAHTAN AL-TAWEEL/ Examiner, Art Unit 2838 /THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838