METHOD AND APPARATUS WITH SCHEDULING NEURAL NETWORK

Application No. 18/501,135

• Filed: Nov 03, 2023
• Priority: Nov 28, 2022 — RE 10-2022-0161575
• Examiner: RAMIREZ BRAVO, BEATRIZ A
• Assignee: Seoul National University R&DB Foundation
• OA Round: 1 (Non-Final)

Office Action

DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Status of Claims
Claims 1-20 are pending examination.

Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted by Applicant on 11/03/2023 has been considered.

Claim Objections
Claim 12 is objected to because of the following informalities:
Typographical error in claim 12 – “acrylic” should read “acyclic”.
Appropriate correction is required.

Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.

The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.

Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 20, it is not clear whether the limitation “corresponding the generated loop structures to a neural network (NN) model” is an incomplete sentence. Hence, the claim is rendered indefinite under 35 U.S.C. 112(b). [Note: For purposes of compact prosecution, Examiner has interpreted the limitation to mean that the generated loop structures correspond to operations of the neural network model]

Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.

Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (abstract idea) without significantly more.
Regarding claim 1,
Step 1: Claim 1 is directed towards a method.
Step 2A, Prong 1: Claim 1 recites the following limitations:
generating operation sets based on the loop structure; (i.e., generating operation sets is a process that can be done in the human mind and/or with the aid of pen and paper.)
generating a priority table for the operation sets based on memory benefits of the operation sets”; (i.e., generating a priority table for the operation sets is a process that can be done in the human mind and/or with the aid of pen and paper.)
scheduling the operation sets based on the priority table (i.e., scheduling operation sets based on a priority table is a process that can be done in the human mind and/or with the aid of pen and paper.)
Hence, the claim recites an abstract idea.
Step 2A, Prong 2: Claim 1 recites the additional element of “A processor-implemented scheduling method, comprising:”. This limitation is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components. (see MPEP 2106.05(f). Furthermore, the claim recites the additional element of “receiving a loop structure corresponding to a neural network (NN) model”. This limitation amounts to no more than insignificant extra-solution activity consisting of mere data transmission. (see MPEP 2106.05(g)). Hence, the claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 1 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of “A processor-implemented scheduling method, comprising:” is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components. (see MPEP 2106.05(f)). Furthermore, the additional element of “receiving a loop structure corresponding to a neural network (NN) model” was considered insignificant extra-solution activity consisting of mere data transmission. (see MPEP 2106.05(g)) As such, this limitation is re-evaluated under Step 2B to see if it is more than what is considered by the courts as well-understood, routine, and conventional activity in the field. The court decisions cited in MPEP 2106.05(d)(II) have determined that mere data transmission (as it is presently claimed) is well-understood, routine, and conventional activity in the field which is supported under Berkheimer. (See MPEP 2106.05(d)(II) i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350) 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network)). Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 2,
Step 2A, Prong 1: Claim 2 recites an abstract idea as inherited from claim 1. Claim 2 further recites the following limitations:
wherein the generating of operation sets comprises:
generating a first operation list based on the loop structure; (i.e., a person can mentally and/or with the aid of pen and paper generate an operation list)
updating the first operation list to a second operation list based on the first operation scheduling; (i.e., a person can mentally and/or with the aid of pen and paper update an operation list to a second operation list)
generating operation sets based on the second operation list (i.e., a person can mentally and/or with the aid of pen and paper generate operation sets based on the updated second operation list)
Hence the claim recites an abstract idea.
Step 2A, Prong 2: Claim 2 recites the addition element of “performing a first operation scheduling according to the first operation list;”. This limitation is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components. (see MPEP 2106.05(f)) Hence, the claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements, individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 2 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of “performing a first operation scheduling according to the first operation list;” is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components. (see MPEP 2106.05(f)) Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 3,
Step 2A, Prong 1: Claim 3 recites an abstract idea as inherited from claim 1.
Step 2A, Prong 2: Claim 3 recites the additional element of “performing an operation of the NN model based on a result of the scheduling of the operation sets”. This limitation is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components. (MPEP 2106.05(f)). Hence, the claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional element that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 3 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of “performing an operation of the NN model based on a result of the scheduling of the operation sets” is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components. (see MPEP 2106.05(f)) Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 4,
Step 2A, Prong 1: Claim 4 recites an abstract idea as inherited from claim 1. Claim 4 recites the following additional limitation:
wherein the generating of the priority table comprises arranging the operation sets in an ascending order of the memory benefits of the operation sets. (i.e., a person can mentally and/or with the aid of pen and paper generate a priority table wherein the operation sets are arranged in ascending order as claimed)
Step 2A, Prong 2: Claim 4 does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional element that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 4 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 5,
Step 2A, Prong 1: Claim 5 recites an abstract idea as inherited from claim 1.
Step 2A, Prong 2: Claim 5 recites the additional element of “wherein the memory benefits of the operation sets are determined based on a reusability data size and/or a spilling data size”. This limitation merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional element that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 5 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of “wherein the memory benefits of the operation sets are determined based on a reusability data size and/or a spilling data size” merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 6,
Step 2A, Prong 1: Claim 6 recites an abstract idea as inherited from claim 1.
Step 2A, Prong 2: Claim 6 recites the additional element of “wherein the reusability data size is a data transfer size that is to be reduced by reusing data used in an operation, and the spilling data size is a data transfer size that increases by avoiding data used in an operation from being reused.” This limitation merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional element that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 6 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of “wherein the reusability data size is a data transfer size that is to be reduced by reusing data used in an operation, and the spilling data size is a data transfer size that increases by avoiding data used in an operation from being reused” merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 7,
Step 2A, Prong 1: Claim 7 recites an abstract idea as inherited from claim 1. Claim 7 recites the following additional limitation:
wherein the generating of the priority table comprises, in response to a difference in the memory benefits between at least two of the operation sets being less than a first threshold value, arranging the at least two operation sets in an ascending order of memory utilization of the at least two operation sets (i.e., a person can mentally and/or with the aid of pen and paper generate a priority table, arranging the at least two operation sets in ascending order, as claimed)
Hence, the claim recites an abstract idea.
Step 2A, Prong 2: The claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional element that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 7 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 8,
Step 2A, Prong 1: Claim 8 recites an abstract idea as inherited from claims 1 and 7. Claim 8 recites the following additional limitation:
wherein the generating of the priority table comprises, in response to a difference in the memory utilization between at least two of the operation sets being equal to or less than a second threshold value, arranging the at least two operation sets in a descending order of memory overhead of the at least two operation sets. (i.e., a person can mentally and/or with the aid of pen and paper generate a priority table, arranging the at least two operation sets in a descending order, as claimed)
Hence, the claim recites an abstract idea.
Step 2A, Prong 2: The claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional element that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 8 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 9,
Step 2A, Prong 1: Claim 9 recites an abstract idea as inherited from claims 1, 7, and 8.
Step 2A, Prong 2: Claim 9 recites the additional elements of “wherein the memory overhead is a memory state used in an operation for the operation sets; and the memory state is determined based on a memory loading data size and a memory storing data size.” This limitation merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional element that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 9 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of “wherein the memory overhead is a memory state used in an operation for the operation sets; and the memory state is determined based on a memory loading data size and a memory storing data size” merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 10,
Step 2A, Prong 1: Claim 10 recites an abstract idea as inherited from claim 1.
Step 2A, Prong 2: Claim 10 recites the additional elements of “wherein the loop structure is one of a plurality of loop structures, which are generated to include different tiling sizes and data flows by receiving a network configuration and a specification of hardware components.” This limitation merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional element that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 10 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of “wherein the loop structure is one of a plurality of loop structures, which are generated to include different tiling sizes and data flows by receiving a network configuration and a specification of hardware components” merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 11,
Step 2A, Prong 1: Claim 11 recites an abstract idea as inherited from claim 1.
Step 2A, Prong 2: Claim 11 recites the additional elements of “wherein the specification of the hardware components comprise a number of cores included in the hardware components.” This limitation merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional element that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 11 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of “wherein the specification of the hardware components comprise a number of cores included in the hardware components” merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 12,
Step 2A, Prong 1: Claim 12 recites an abstract idea as inherited from claims 1 and 2.
Step 2A, Prong 2: Claim 12 recites the additional elements of “wherein the first operation list is generated using a directed acrylic graph (DAG) of the loop structure.” This limitation merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional element that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 12 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of “wherein the first operation list is generated using a directed acrylic graph (DAG) of the loop structure” merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 13,
Step 1: Claim 13 is directed towards an apparatus.
Step 2A, Prong 1: Claim 13 recites the same limitations as claim 1 above. Analysis of Step 2A, Prong 1 from claim 1 is incorporated here by reference.
Hence the claim recites an abstract idea.
Step 2A, Prong 2: Claim 13 recites the additional element of “a processor configured to:”. This limitation is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components. (see MPEP 2106.05(f). Furthermore, the claim recites the additional element of “receive a loop structure corresponding to processing operations of a neural network (NN) model”. This limitations amounts to no more than insignificant extra-solution activity consisting of mere data transmission. (see MPEP 2106.05(g)). Hence, the claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 13 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of “a processor configured to:” is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components. (see MPEP 2106.05(f)). Furthermore, the additional element of “receive a loop structure corresponding to processing operations of a neural network (NN) model” was considered insignificant extra-solution activity consisting of mere data transmission. (see MPEP 2106.05(g)) As such, this limitation is re-evaluated under Step 2B to see if it is more than what is considered by the courts as well-understood, routine, and conventional activity in the field. The court decisions cited in MPEP 2106.05(d)(II) have determined that mere data transmission (as it is presently claimed) is well-understood, routine, and conventional activity in the field which is supported under Berkheimer. (See MPEP 2106.05(d)(II) i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350) 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network)). Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Regarding claim 14,
Claim 14 recites the same and/or analogous limitations as claim 2 above. Hence, claim 14 is rejected under the same rationale as claim 2.

Regarding claim 15,
Claim 15 recites the same and/or analogous limitations as claim 4 above. Hence, claim 15 is rejected under the same rationale as claim 4.

Regarding claim 16,
Claim 16 recites the same and/or analogous limitations as claim 5 above. Hence, claim 16 is rejected under the same rationale as claim 5.

Regarding claim 17,
Claim 17 recites the same and/or analogous limitations as claim 6 above. Hence, claim 17 is rejected under the same rationale as claim 5.

Regarding claim 18,
Claim 18 recites the same and/or analogous limitations as claim 7 above. Hence, claim 18 is rejected under the same rationale as claim 7.

Regarding claim 19,
Claim 19 recites the same and/or analogous limitations as claim 8 above. Hence, claim 19 is rejected under the same rationale as claim 8.

Regarding claim 20,
Step 1: Claim 20 is directed towards a method.
Step 2A, Prong 1: Claim 20 recites the following limitations:
generating loop structures by receiving a network configuration and a specification of related hardware components; (i.e., generating loop structures is a process that can be done in the human mind and/or with the aid of pen and paper.)
generating scheduled operation lists for the loop structures, respectively, based on predetermined priorities of operating the NN model; (i.e., generating scheduled operation lists is a process that can be done in the huma mind and/or with the aid of pen and paper)
determining a final scheduled operation list among the generated scheduled operations lists, wherein the final scheduled operation list has a smallest latency and data transfer size among the scheduled operation lists (i.e., determining a final operation list among the generated scheduled operation list is a process that can be done in the human mind and/or with the aid of pen and paper)
Step 2A, Prong 2: Claim 20 recites the additional element of “corresponding the generated loop structures to a neural network (NN) model”. This limitation merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim does not recite additional elements that integrate the judicial exception into a practical application. Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional element that are indicative of integration into a practical application, the claim is directed to an abstract idea.
Step 2B: Claim 12 does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of “corresponding the generated loop structures to a neural network (NN) model” merely generally links the use of the judicial exception to a technological environment or field of use. (see MPEP 2106.05(h)) Hence, the claim lacks limitations which amount to significantly more than the judicial exception or an inventive concept, and is rejected. Considering the additional elements individually and in combination, and the claim as a whole, the additional element does not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.

Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 3, 5, 6, 10, 11, 12, 13, 14, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng et al. (U.S. Patent No. 11809849, filed May 20, 2021 and published Nov. 7, 2023) in view of Fishel et al. (US 20190340490 A1, filed May 4, 2018 and published Nov. 7, 2019)

Regarding claim 1, Zheng teaches a processor-implemented scheduling method, comprising:
receiving a loop structure corresponding to a neural network (NN) model (Zheng, Fig. 10, 1002 teaches receiving information representing a dataflow graph of a neural network, the neural network comprising a neural network operator.; Zheng, Col. 2, lines 49-67 further teaches the repetitive operations in a neural network operator can be represented in the form of an affine loop.);
generating operation sets based on the loop structure (Zheng, Fig. 10, 1012 further teaches generating a schedule of execution of batches of the iterations of the operations; Zheng, Col. 3, lines 14-38 further teaches a compiler can compile input codes representing a neural network operator into executable instructions that can be in the form of binary codes. As part of the compiling process, the compiler can generate a loop-nest representation of the neural network operator. The generation of the loop-nest representation allows the compiler to determine the schedule of execution of each loop and, based on the schedule, generate the executable binary codes to control the order of execution of the loops.);
However, Zheng does not distinctly disclose:
generating a priority table for the operation sets based on memory benefits of the operation sets; and
scheduling the operation sets based on the priority table.

Nevertheless, Fishel teaches:
generating a priority table for the operation sets based on memory benefits of the operation sets (Fishel, [0091] FIG. 11 is a diagram illustrating retrieval of task descriptors 1012 using a task queue 1004, according to one embodiment. The task queue 1004 includes a reference, such as a set of pointers, to the task descriptors 1012A through 1012N stored in the system memory 230. To that end, the task queue 1004 may include a memory storing a head parameter 1102, a network identifier (ID) 1104, a base address index 1106, a tail parameter 1108, a count parameter 1110, and a priority parameter 1112. The head parameter 1102 is a pointer to a location of the system memory 230 storing the task descriptor 1012A at the head of the task queue 1004. The network ID 1104 identifies the neural network 900 of the task descriptor 1012 at the head of the task queue 1004, and the base address index 1106 is an index to a base-address table 1114 tagged with the network ID 1104 of the task descriptor 1012A at the head of the task queue 1004. The count parameter 1110 defines the number of task descriptors 1012 in the task queue 1004. The priority parameter 1112 defines the priority of the task queue 1004, which is used by the task arbiter 1002 to select between multiple task queues 1004.; Fishel [0063] further teaches Input data is typically split into smaller pieces of data for parallel processing at multiple neural engines 314. Often multiple cycles of operations are performed to generate output for a task associated with a neural network. A compiler executed by CPU 208 analyzes the hierarchy and nodes of the neural network and determines how the input data is to be segmented based on the hardware constraints of the neural processor circuit 218 B [i.e., based on hardware constraints understood to read on memory benefits, as claimed]. One of functions of the compiler is to determine how input data is to be split into smaller data units for processing at the neural engines 314, and how the processing is to be iterated in loops to produce the result for tasks.; Fishel, [0038] teaches neural processor circuit 218 is a circuit that performs various machine learning operations based on computations including multiplication, addition and accumulation. Such computations may be arranged to perform, for example, convolution of input data and kernel data. Neural processor circuit 218 is a configurable circuit that performs these operations in a fast and power-efficient manner while relieving CPU 208 of resource-intensive operations associated with neural network operations.); and
scheduling the operation sets based on the priority table (Fishel, [0022] teaches The neural task manager includes multiple task queues and a task arbiter. Each task queue stores a task list of tasks for a machine learning operation. Each task list or task queue may be associated with a priority parameter. [Note: the task queues storing task list of tasks of a machine learning operation understood to read on scheduling the operation sets] The task arbiter retrieves configuration data for a task from an external memory based on the priority parameters, and provides the configuration data to components of the neural processor circuit including the one or more neural engines.; Fishel [0092] teaches when a particular task queue 1004 is selected (e.g., according to the priority parameter 1112), the task arbiter 1002 references the head parameter 1102, the network ID 1104, the base address index 1106, and the base address table 1114 to retrieve a task descriptor 1012 from the system memory 230, and places the task descriptor 1012 into the fetch queue 1008 to initiate commitment of the task for execution. In each configuration period, the task arbiter 1002 may continue to place a task descriptor 1012 into the fetch queue 1008 according to the order of tasks defined by the task list 904 of the task queue 1004, such as by retrieving the next task descriptor 1012B, and so forth.; See also Fishel Fig. 11; [Note: As stated above, Zheng, Col. 3, lines 14-38 also teaches the generation of the loop-nest representation allows the compiler to determine the schedule of execution of each loop and, based on the schedule, generate the executable binary codes to control the order of execution of the loops; See also Zheng Fig. 10, 1012]).

Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to have modified the method performed by a compiler, as taught by Zheng, to include the task queue and base address table, as taught by Fishel, in order to perform neural network operation in a fast and power-efficient manner while relieving the CPU of resource-intensive operations associated with neural network operations. (Fishel, [0038])

Regarding claim 2, the combination of Zheng in view of Fishel teaches all of the limitations of claim 1, and the combination further teaches wherein the generating of operation sets comprises: generating a first operation list based on the loop structure; performing a first operation scheduling according to the first operation list (Zheng, Abstract, teaches and generating a schedule of execution of the batches of the iterations of the operations; Zheng, Col. 2, lines 40-52 teaches The repetitive operations in a neural network operator can be represented in the form of an affine loop. An affine loop is a loop with a canonical induction variable that starts at zero and increments by one for each iteration.; Zheng, Col. 2, lines 49-67 and Col. 3, lines 1-13 teaches in a case where the repetitive operations involve a multi-dimensional tensor that includes multiple tensors defined along different dimensions, the repetitive operations can be represented in a loop-nest, which may be manifested at certain intermediate representations generated by the compiler. In a simple example, a loop-nest includes an outer loop and an inner loop within the body of the outer loop. The outer loop and the inner loop may each iterate across a different range of induction variable values. Each range of values can correspond to a range of a dimension of the multi-dimensional tensor. For example, in a case of a two-dimensional tensor, the first iteration of the outer loop triggers the inner loop, which executes across its entire range of values to index the elements of a first tensor along a first column in multiple iterations. [Note: the first iteration of the repetitive operations in the loop has been understood to read on a first operation scheduling]); updating the first operation list to a second operation list based on the first operation scheduling (Zheng, Abstract, teaches and generating a schedule of execution of the batches of the iterations of the operations; Zheng, Col. 2, lines 40-52 teaches The repetitive operations in a neural network operator can be represented in the form of an affine loop. An affine loop is a loop with a canonical induction variable that starts at zero and increments by one for each iteration. [note: the first iteration in the loop of operations reading on based on the first operation scheduling]; Zheng, Col. 4, lines 41-67 teaches the loops can update the induction variables to select different tensors in different iterations.;); and generating operation sets based on the second operation list (Zheng, Col. 3, lines 1-13 teaches Upon completion of the inner loop, the outer loop moves to a second value within its range of values and again triggers the inner loop, which again executes across its entire range of values to index the elements of a second tensor along a second column in multiple iterations.).
Motivation to combine same as stated for claim 1.

Regarding claim 3, the combination of Zheng in view of Fishel teaches all of the limitations of claim 1, and the combination further teaches further comprising: performing an operation of the NN model based on a result of the scheduling of the operation sets (Fishel, Abstract and [0004]-[0005] teaches embodiments relate to managing tasks that when executed by a neural processor circuit instantiates a neural network. The neural processor circuit includes neural engine circuits and a neural task manager circuit. The neural task manager circuit includes multiple task queues and a task arbiter circuit. Each task queue stores a reference to a task list of tasks for a machine learning operation. Each task queue may be associated with a priority parameter. Based on the priority of the task queues, the task arbiter circuit retrieves configuration data for a task from a memory external to the neural processor circuit, and provides the configuration data to components of the neural processor circuit including the neural engine circuits. The configuration data programs the neural processor circuit to execute the task. [Note: the neural task manager circuit including task queues and a task arbiter that retrieves configuration data, wherein the configuration data programs the neural processor circuit to execute a task understood to read on the limitation as claimed.]).
Motivation to combine same as stated for claim 1.

Regarding claim 5, the combination of Zheng in view of Fishel teaches all of the limitations of claim 1, and the combination further teaches wherein the memory benefits of the operation sets are determined based on a reusability data size and/or a spilling data size (Zheng, Col. 4, lines 11-40 teaches examples described herein provide methods, systems, and other techniques to improve the scheduling of repetitive operations of a neural network operator. The compiler can determine a number of iterations of the operations to be included in a batch, where operations within a batch can be executed in parallel and can access different memory addresses, while different batches are executed sequentially. Moreover, the compiler can determine an address mapping scheme in which the different batches of operations reuse the same set of memory addresses, to reduce the total memory footprint by the neural network operator. The compiler can determine the address mapping scheme and assign the iterations into batches based on the computation and memory resources assigned to the neural network operator. The assignment of the computation and memory resources to the neural network operator can be made by, for example, an administration/management software of the neural network hardware accelerator, and the information of about the computation and memory resources (e.g., a number of iterations of operations that can be executed in parallel, a size of a local memory space assigned to the particular neural network operator or to the entire neural network, etc.) can be part of configuration parameters of the compiler to configure the compilation operation. After determining the address mapping scheme and the batches, the compiler can determine a schedule of execution of the batches, as well as the addresses of the memory accessed by the iterations of operations within each batch, and generate binary codes based on the schedule of execution of the batches and the addresses of the memory accessed by the batches.).

Regarding claim 6, the combination of Zheng in view of Fishel teaches all of the limitations of claim 5, and the combination further teaches wherein the reusability data size is a data transfer size that is to be reduced by reusing data used in an operation, and the spilling data size is a data transfer size that increases by avoiding data used in an operation from being reused (Zheng, Col. 4, lines 11-40 teaches examples described herein provide methods, systems, and other techniques to improve the scheduling of repetitive operations of a neural network operator. The compiler can determine a number of iterations of the operations to be included in a batch, where operations within a batch can be executed in parallel and can access different memory addresses, while different batches are executed sequentially. Moreover, the compiler can determine an address mapping scheme in which the different batches of operations reuse the same set of memory addresses, to reduce the total memory footprint by the neural network operator. The compiler can determine the address mapping scheme and assign the iterations into batches based on the computation and memory resources assigned to the neural network operator. The assignment of the computation and memory resources to the neural network operator can be made by, for example, an administration/management software of the neural network hardware accelerator, and the information of about the computation and memory resources (e.g., a number of iterations of operations that can be executed in parallel, a size of a local memory space assigned to the particular neural network operator or to the entire neural network, etc.) can be part of configuration parameters of the compiler to configure the compilation operation. After determining the address mapping scheme and the batches, the compiler can determine a schedule of execution of the batches, as well as the addresses of the memory accessed by the iterations of operations within each batch, and generate binary codes based on the schedule of execution of the batches and the addresses of the memory accessed by the batches.; Zheng, Col. 8, lines 1-9 teaches In some examples, the neural network operator can also include one or more tensors accessed by direct memory access (DMA) instructions (“DMA tensors”) to transfer data between an external memory and the local memory of the neural network hardware accelerator. The DMA instructions can also be included in the same loop as other instructions of a neural network operator (e.g., additions, multiplications, activation function processing, etc.), to provide memory data transfer to support those instructions.; Zheng, Col. 8, lines 48-60 teaches after the global modulo allocation operation completes and the modulo operators for the tensors of the program are determined, the compiler can determine a schedule of execution of the different iterations of the loops in the program and the mapping of the tensors to the memory addresses based on the modulo operators. The compiler can perform the scheduling based on estimating the total completion time of the DMA operations, which can include the memory access delay as well as memory data transfer delay over the interconnect, as well as data dependency between the tensors. The compiler can then generate executable instructions that reflect the schedule of execution of the different iterations of the loops in the program.; Col. 32, lines 48-62 further teaches based on the data dependency of addition operations 906a and 906b on DMA operations 904a and 904b, where addition operations 906a and 906b consume tensor elements L0(0) and L0(1) generated by DMA operations 904a and 904b, the compiler can schedule parallel execution of a first group of addition operations, including addition operations 906a and 906b, at time T1. The compiler can also have addition operations 906a and 906b to reuse the memory addresses allocated to DMA operations 904a and 904b such that the compiler does not need to allocate additional memory addresses to addition operations 906a and 906b, and the total memory footprint remains within total memory footprint 920 when addition operations 906a and 906b are executed in parallel with DMA operations 904c and 904d at time T1.).

Regarding claim 10, the combination of Zhen in view of Fishel teaches all of the limitations of claim 1, and the combination further teaches wherein the loop structure is one of a plurality of loop structures (Zheng, Fig. 8A teaches plurality of loop structures), which are generated to include different tiling sizes and data flows by receiving a network configuration and a specification of hardware components (Zheng Fig. 5D teaches different loop tiling sizes [i.e., different orders]; see also Zheng, Fig. 5B, dataflow graph 510; Zheng Col. 33, lines 29-60 further teaches method 1000 start with step 1002, in which compiler 330 receives information representing a dataflow graph of a neural network, the neural network comprising a neural network operator. In some examples, compiler 330 can receive input codes involving neural network computations and compile the input codes to generate a dataset representing the dataflow graph of the neural network. An example of the dataflow graph is shown in FIG. 5B, which may include a plurality of neural network operators, such as an addition operator, a convolution operator, an activation function (e.g., ReLU) operator, etc. Each neural network operator can be represented as a node in the dataflow graph. The compiler can generate a linear graph from the dataflow graph by performing, for example, a topological sort as shown in FIG. 5B to assign each node (and the associated neural network operator) to the linear graph. The compiler can then generate a program representing the linear graph based on translating each neural network operator represented in the linear graph into a loop including instructions to access a tensor. In step 1004, compiler 330 receives first information of computation resources of the neural network hardware accelerator assigned (or intended) to execute the neural network operator. Moreover, in step 1006, compiler 330 receives second information of a portion of a local memory of the neural network hardware accelerator assigned to execute the neural network operator. The first information may indicate, for example, a number of parallel execution of the neural network operator supported by the neural network hardware accelerator. The second information may indicate a size of the portion of the local memory, which can represent the memory space available to support the parallel execution.).

Regarding claim 11, the combination of Zheng in view of Fishel teaches all of the limitations of claim 10, and the combination further teaches wherein the specification of the hardware components comprise a number of cores included in the hardware components (Zheng, Col. 3, lines 39-59 teaches a hardware neural network accelerator typically includes computation resources, such as multiple computation engines, to support parallel execution of the different iterations of a neural network operator, as well as an on-chip memory to provide intermediate storage for the input and output of the neural network operator, all of which can speed up the execution of the neural network operator. But the level of parallelism supported by the hardware neural network accelerator can be limited by the amount of computation resources and memory space assigned (or intended) to the execution of the neural network operator. For example, the number of computation engines assigned to the execution of the neural network operator can limit a number of loop iterations that can be executed in parallel at a given time. Moreover, the memory space may limit a number of elements of a tensor stored in the memory at a given time. As each iteration indexes/accesses a different element of a tensor from a different memory address, the size of the memory space can also limit the number of iterations executing in parallel that can access the different elements at a given time. [Note: “computation engines” of the neural network accelerator has been understood to read on “cores” as claimed]).

Regarding claim 12, the combination of Zheng in view of Fishel teaches all of the limitations of claim 2, and the combination further teaches wherein the first operation list is generated using a directed acrylic graph (DAG) of the loop structure (Zheng, Col. 10, lines 5-11 teaches the model 100 can be referred to as a directed, weighted graph. In a directed graph, each connection to or from a node indicates a direction (e.g., into the node or away from the node). In a weighted graph, each connection can have a weight. Tools for developing neural networks can visualize the neural network as a directed, weighted graph, for ease of understanding and debuggability.).

Regarding claim 13,
Claim 13 recites the same and/or analogous limitations as claim 1. Therefore, claim 13 is rejected under the same rationale and motivation as claim 1.
Zheng further teaches a processor configured to (Zheng, Col. 14 lines 40-54 teaches as described above, accelerator 202 may execute a set of instructions that reflects, for example, computational flow model 100 of FIG. 1, to perform the computations for a neural network. The set of instructions can be generated by a compiler. FIG. 3 includes a block diagram illustrating an example of a host system 300 on which the compiler can run. The illustrated host system 300 is an example of a computing device, and includes a processor 302, a processor memory 304, at least one storage device 306, various Input/Output (I/O) devices 308, and at least one network interface 310. In the example of FIG. 3, the host system 300 also includes an acceleration engine 312, which is an integrated circuit device that can accelerate certain operations or computations performed by the host system 300.)

Regarding claim 14,
Claim 14 recites the same and/or analogous limitations as claim 2. Therefore, claim 2 is rejected under the same rationale and motivation as claim 2.

Regarding claim 16,
Claim 16 recites the same and/or analogous limitations as claim 5. Therefore, claim 16 is rejected under the same rationale and motivation as claim 5.

Regarding claim 17,
Claim 17 recites the same and/or analogous limitations as claim 6. Therefore, claim 17 is rejected under the same rationale and motivation as claim 6.

Claims 4, 7, 8, 9, 15, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng in view of Fishel, as applied to claim 1, and further in view of Suh et al. (U.S. Patent No. 9417912, filed Mar. 11, 2011 and published Aug. 16, 2016)
Regarding claim 4, the combination of Zheng in view of Fishel teaches all of the limitations of claim 1, however, the combination does not distinctly disclose wherein the generating of the priority table comprises arranging the operation sets in an ascending order of the memory benefits of the operation sets.
Nevertheless Suh teaches wherein the generating of the priority table comprises arranging the operation sets in an ascending order of the memory benefits of the operation sets (Suh, Col. 7, lines 61-67, and Col. 8, lines 1-3 teaches in response to the tasks T1, T2, and T3, having attributes corresponding to events, being inserted in the run queue 110, the controller 130 may determine the order of priority of the tasks T1, T2, and T3 inserted into the run queue 110 with reference to the weight table 141. For example, in an example in which task 1 T1 triggered by event E1 and task 2 T2 triggered by event E2 are received, the controller 130 may give a higher priority to task 1 T1 than task 2 T2 by referring to the weight table 141. In one example, the weight may be differently applied for the respective schedulers S1 and S2.; Suh, Col. 8, lines 39-48 teaches the weight table 141, according to an example, shows priority weights that may be different with each scheduler. Therefore, the order of priority of tasks to be inserted in the run queue 130 may be adjusted depending on a scheduler used in response to the control unit 130 determining the order of priority of tasks. For example, if the order of priority is determined based on the scheduler S1, the task T1 triggered by the event E1 may have the highest priority, and the tasks T1, T2, and T3 may be inserted into the run queue 130 in the order of task 1 T1, task 2 T2, and task T3 (see, e.g., FIG. 5A).; See Fig. 3 and Fig. 5A – S1 shows priority table in ascending order T1>T2>T3).
Before the effective filing date of the claimed invention, it would have been ordinary for one of ordinary skill in the art to have modified the method performed by a compiler, as taught by Zheng in view of Fishel, to further include the scheduling method, as taught by Suh, in order to determine order of priority of tasks based on the need for urgent processing of tasks or the need for real time processing of task as required by consumer electronics, thereby overcoming conventional technology in virtual machines. (Suh, Col. 1, lines 43-51 and Col. 1, lines 64-67 and col. 2 lines 1-2)

Regarding claim 7, the combination of Zheng in view of Fishel teaches all of the limitations of claim 1, however the combination does not distinctly disclose wherein the generating of the priority table comprises, in response to a difference in the memory benefits between at least two of the operation sets being less than a first threshold value, arranging the at least two operation sets in an ascending order of memory utilization of the at least two operation sets.
Nevertheless, Suh teaches wherein the generating of the priority table comprises, in response to a difference in the memory benefits between at least two of the operation sets being less than a first threshold value, arranging the at least two operation sets in an ascending order of memory utilization of the at least two operation sets (Suh, Fig. 8 shows and example of operation sets 801 and 802 in ascending order of memory utilization; Suh, Col. 5, lines 52-67 further teaches example of the run queue 800, tasks having different attributes. The attribute task may represent a requirement for triggering the task. For example, task 1T1 and task T2 may be tasks triggered by a predetermined event [i.e., the predetermined event being understood as the threshold]; task 3T3, task 4T4, and task 5T5 may be tasks triggered by a predetermined interrupt. Such attributes of task may include event, e.g., source, deadline, and/or interrupt [i.e., the “event” and/or “deadline” being understood as the threshold]. These are nonlimiting examples of tasks.).
Before the effective filing date of the claimed invention, it would have been ordinary for one of ordinary skill in the art to have modified the method performed by a compiler, as taught by Zheng in view of Fishel, to further include the scheduling method, as taught by Suh, in order to determine order of priority of tasks based on the need for urgent processing of tasks or the need for real time processing of task as required by consumer electronics, thereby overcoming conventional technology in virtual machines. (Suh, Col. 1, lines 43-51 and Col. 1, lines 64-67 and col. 2 lines 1-2)

Regarding claim 8, the combination of Zheng in view of Fishel and Suh teaches all of the limitations of claim 7, and the combination further teaches wherein the generating of the priority table comprises, in response to a difference in the memory utilization between at least two of the operation sets being equal to or less than a second threshold value, arranging the at least two operation sets in a descending order of memory overhead of the at least two operation sets (Suh, Fig. 5B teaches S2, where T3>T = T2; Suh, Col. 8, lines 19-23 teaches as shown in FIGS. 1, 5A, and 5B, it may be presumed that three tasks T1, T2, and T3 are received, and the task T1, the task T2 and the task T3 are triggered by the events E1, E2, and E3, respectively. In addition, it may be presumed for this example that the event E3 is a time interrupt and the scheduler S1 and the scheduler S2 exist.; Col. 9, lines 49-53 teaches if the order of priority is determined based on the scheduler S2, the task T3 triggered by the event C may have the highest priority, and the tasks T1, T2, and T3 may be inserted into the run queue 130 in the order of T3, T2, and T1 (see, e.g., FIG. 5B).; Suh, Col. 5, lines 52-67 further teaches example of the run queue 800, tasks having different attributes. The attribute task may represent a requirement for triggering the task. For example, task 1T1 and task T2 may be tasks triggered by a predetermined event [i.e., triggered by a deadline and/or event being understood as triggered by a threshold]; task 3T3, task 4T4, and task 5T5 may be tasks triggered by a predetermined interrupt. Such attributes of task may include event, e.g., source, deadline, and/or interrupt [i.e., an event and/or deadline being understood to read on threshold]. These are nonlimiting examples of tasks.).

Regarding claim 9, the combination of Zheng in view of Fishel and Suh teaches all of the limitations of claim 8, and the combination further teaches wherein the memory overhead is a memory state used in an operation for the operation sets; and the memory state is determined based on a memory loading data size and a memory storing data size (Zheng, Col. 33, lines 48-60 teaches in step 1004, compiler 330 receives first information of computation resources of the neural network hardware accelerator assigned (or intended) to execute the neural network operator. Moreover, in step 1006, compiler 330 receives second information of a portion of a local memory of the neural network hardware accelerator assigned to execute the neural network operator [i.e., understood to read on memory state used in an operation for the operation sets]. The first information may indicate, for example, a number of parallel execution of the neural network operator supported by the neural network hardware accelerator [i.e, understood to read on memory loading size]. The second information may indicate a size of the portion of the local memory, which can represent the memory space available to support the parallel execution. [i.e., understood to read on memory storing size]).

Regarding claim 15,
Claim 15 recites the same and/or analogous limitations as claim 4. Therefore, claim 15 is rejected under the same rationale and motivation as claim 4.

Regarding claim 18,
Claim 18 recites the same and/or analogous limitations as claim 7. Therefore, claim 18 is rejected under the same rationale and motivation as claim 7.

Regarding claim 19,
Claim 19 recites the same and/or analogous limitations as claim 8. Therefore, claim 19 is rejected under the same rationale and motivation as claim 8.

Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zheng et a. in view of Fishel et al., and further in view of Song et al. (US 20230042773 A1, filed Aug. 8, 2022 and published Feb. 9, 2023)

Regarding claim 20, Zheng teaches a processor-implemented method (Zheng, Col. 14 lines 40-54 teaches as described above, accelerator 202 may execute a set of instructions that reflects, for example, computational flow model 100 of FIG. 1, to perform the computations for a neural network. The set of instructions can be generated by a compiler. FIG. 3 includes a block diagram illustrating an example of a host system 300 on which the compiler can run. The illustrated host system 300 is an example of a computing device, and includes a processor 302, a processor memory 304, at least one storage device 306, various Input/Output (I/O) devices 308, and at least one network interface 310. In the example of FIG. 3, the host system 300 also includes an acceleration engine 312, which is an integrated circuit device that can accelerate certain operations or computations performed by the host system 300.), comprising:
generating loop structures by receiving a network configuration and a specification of related hardware components (Zheng, Fig. 10, 1002 teaches receiving information representing a dataflow graph of a neural network, the neural network comprising a neural network operator.; Zheng, Col. 2, lines 49-67 further teaches the repetitive operations in a neural network operator can be represented in the form of an affine loop.; Zheng, Col. 6, lines 21-28 teaches the initial modulo operators for each loop can be determined based on a maximum degree of parallel execution of the neural network operator supported by the neural network hardware accelerator, as well as the size of memory space assigned to the neural network operator. Specifically, the number of iterations made available for parallel execution may be equal to the product of initial modulo operators of each loop in a loop-nest.; Zheng, col. 6, lines 64-67 and Col. 7 lines 1-10 further teaches the assignment order of initial modulo operators (parent loop followed by child loops, or vice versa) can be based on the architecture of the system that execute the neural network operators. For example, for a system that has multiple hardware processors, the compiler may preferentially set the initial modulo operators for the parent loop first, followed by the child loops, to manage parallel execution of the parent loops across the multiple hardware processors. On the other hand, for a system that has a single hardware processor with multiple execution engines, the compiler may preferentially set the initial modulo operators for the child loops first, followed by the parent loop, to manage parallel execution of the child loops across the execution engines for each iteration of the parent loop.
corresponding the generated loop structures to a neural network (NN) model (Zheng, Fig. 10, 1002 teaches receiving information representing a dataflow graph of a neural network, the neural network comprising a neural network operator.; Zheng, Col. 2, lines 49-67 further teaches the repetitive operations in a neural network operator can be represented in the form of an affine loop; Zheng, Fig. 10, 1012 further teaches generating a schedule of execution of batches of the iterations of the operations; Zheng, Col. 3, lines 14-38 further teaches a compiler can compile input codes representing a neural network operator into executable instructions that can be in the form of binary codes. As part of the compiling process, the compiler can generate a loop-nest representation of the neural network operator. The generation of the loop-nest representation allows the compiler to determine the schedule of execution of each loop and, based on the schedule, generate the executable binary codes to control the order of execution of the loops.) ;

However, Zheng does not distinctly disclose:
generating scheduled operation lists for the loop structures, respectively, based on predetermined priorities of operating the NN model; and determining a final scheduled operation list among the generated scheduled operations lists, wherein the final scheduled operation list has a smallest latency and data transfer size among the scheduled operation lists.
Nevertheless, Fishel teaches:
generating scheduled operation lists for the loop structures, respectively, based on predetermined priorities of operating the NN model (Fishel, Abstract and [0004] teaches the neural task manager circuit includes multiple task queues and a task arbiter circuit. Each task queue stores a reference to a task list of tasks for a machine learning operation. Each task queue may be associated with a priority parameter. [Note: the task queues being understood to read on scheduled operation lists]; Fishel, [0091] FIG. 11 is a diagram illustrating retrieval of task descriptors 1012 using a task queue 1004, according to one embodiment. The task queue 1004 includes a reference, such as a set of pointers, to the task descriptors 1012A through 1012N stored in the system memory 230. To that end, the task queue 1004 may include a memory storing a head parameter 1102, a network identifier (ID) 1104, a base address index 1106, a tail parameter 1108, a count parameter 1110, and a priority parameter 1112. The head parameter 1102 is a pointer to a location of the system memory 230 storing the task descriptor 1012A at the head of the task queue 1004. The network ID 1104 identifies the neural network 900 of the task descriptor 1012 at the head of the task queue 1004, and the base address index 1106 is an index to a base-address table 1114 tagged with the network ID 1104 of the task descriptor 1012A at the head of the task queue 1004. The count parameter 1110 defines the number of task descriptors 1012 in the task queue 1004. The priority parameter 1112 defines the priority of the task queue 1004, which is used by the task arbiter 1002 to select between multiple task queues 1004.; Fishel [0063] further teaches Input data is typically split into smaller pieces of data for parallel processing at multiple neural engines 314. Often multiple cycles of operations are performed to generate output for a task associated with a neural network. A compiler executed by CPU 208 analyzes the hierarchy and nodes of the neural network and determines how the input data is to be segmented based on the hardware constraints of the neural processor circuit 218 B [i.e., based on hardware constraints understood to read on memory benefits, as claimed]. One of functions of the compiler is to determine how input data is to be split into smaller data units for processing at the neural engines 314, and how the processing is to be iterated in loops to produce the result for tasks.; Fishel, [0038] teaches neural processor circuit 218 is a circuit that performs various machine learning operations based on computations including multiplication, addition and accumulation. Such computations may be arranged to perform, for example, convolution of input data and kernel data. Neural processor circuit 218 is a configurable circuit that performs these operations in a fast and power-efficient manner while relieving CPU 208 of resource-intensive operations associated with neural network operations.); and
Examiner believes that the combination teaches or at least suggests the limitation determining a final scheduled operation list among the generated scheduled operations lists, wherein the final scheduled operation list has a smallest latency and data transfer size among the scheduled operation lists (Fishel, [0095] teaches the fetch queue 1008 stores a task descriptor 1012 (e.g., including the task descriptor header 1202 and the address data 1204A through 1204N) for a task that is pending and not committed to execution. The fetch queue 1008 reduces the latency of reading the next task descriptor 1012 into the configuration queue 1010 from the system memory 230. The fetch queue 1008 stores the highest priority task descriptor 1012 as determined by the task arbiter 1002. The task arbiter 1002 may replace the task descriptor 1012 stored in the fetch queue 1008 if a higher priority task descriptor 1012 has been has been enqueued (e.g., from a higher priority task queue 1004).; [Note; Zheng teaches in, Col. 8, lines 48-60 teaches after the global modulo allocation operation completes and the modulo operators for the tensors of the program are determined, the compiler can determine a schedule of execution of the different iterations of the loops in the program and the mapping of the tensors to the memory addresses based on the modulo operators. The compiler can perform the scheduling based on estimating the total completion time of the DMA operations, which can include the memory access delay as well as memory data transfer delay over the interconnect, as well as data dependency between the tensors.]). Song, more clearly teaches the limitation as provided below.
Song teaches determining a final scheduled operation list among the generated scheduled operations lists, wherein the final scheduled operation list has a smallest latency and data transfer size among the scheduled operation lists (Song [0019] teaches in an embodiment, the at least one processor may identify computation costs required for performing the convolution operation for each of the plurality of schedule candidates. In an embodiment, the at least one processor may identify a schedule candidate, which has the smallest computation costs among the plurality of schedule candidates, as the neural network computation schedule. In the process, the computation costs may include at least one of energy and time required for performing the convolution operation. [Note: here the identified schedule candidate from among a plurality of candidates is being understood as the final schedule operation list]; Song [0030] further teaches the identifying of the neural network computation schedule may include identifying computation costs required for performing the convolution operation for each of the plurality of schedule candidates, and identifying a schedule candidate, which has the smallest computation costs among the plurality of schedule candidates, as the neural network computation schedule. In the process, the computation costs may include at least one of energy and time required for performing the convolution operation. [Note: selecting the schedule with the smallest computation costs being defined here as the time required to perform the convolution operation being understood to read on the schedule having the smallest latency and data transfer size]; Song, [0043] teaches FIG. 8A, FIG. 8B and FIG. 8C are diagrams illustrating a process of performing bottom-up scheduling using a scheduling table, according to an embodiment of the present disclosure; Song, [0047] further teaches FIG. 12A and FIG. 12B show a table and a graph of comparing a scheduling method according to an embodiment of the present disclosure with a scheduling method according to a conventional art; Song [0007] teaches reducing time required for performing scheduling through bottom-up scheduling where scheduling for a low level section of the neural network computing device is performed first, and scheduling for a high level section is then performed [Note: bottom-up scheduling further reading on schedule having the smallest latency and data transfer size)
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified the method performed by a compiler, as taught by Zheng in view of Fishel, to further include the scheduling for movement of neural network computation data, as taught by Song, in order to provide a device capable of reducing time required for performing scheduling through bottom-up scheduling where scheduling for a low level section of the neural network computing device is performed first, and scheduling for a high level section is then performed. (Song, [0007])

Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chinya et al. (US 20200410327 A1) – [0032] The data reuse scheme depends on the loop order, loop blocking and partition for tensor processing. The “schedule” as used herein refers to these elements together. In fixed-schedule inference engines 16 having the loop order, blocking, and partition in convolution operations fixed, an accelerator 24 can only implement one type of dataflow with one scheme of data. [0035] Thus, the FSAD may be configured to distribute the IF and FL tensor data to PE 30 arrays based on the current layer N's optimal schedule with no bank conflicts. The FSAD may also re-arrange the OF tensor data of the DNN layer N according to the layer N+1's optimal schedule before writing the activations to the SRAM banks.
Kim (US 20220138586 A1) - [0668] The NPU scheduler may schedule the operation sequence of the PE array based on the ANN data locality information, for example, data arrangement for layers of an artificial neural network of an artificial neural network model or information about a structure.
Ambrose et al. (US 10740674 B2) - A method of configuring a System-on-Chip (SoC) to execute a Convolutional Neural Network (CNN) by (i) receiving scheduling schemes each specifying a sequence of operations executable by Processing Units (PUs) of the SoC; (ii) selecting, a scheduling scheme for a current layer of the CNN; (iii) determining a current state of memory for a storage location in the SoC allocated for storing feature map data from the CNN; (iv) selecting, from the plurality of scheduling schemes and dependent upon the scheduling scheme for the current layer of the CNN, a set of candidate scheduling schemes for a next layer of the CNN; and (v) selecting, from the set of candidate scheduling schemes dependent upon the determined current state of memory, a scheduling scheme for the next layer of the CNN.

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/B.R.B./Examiner, Art Unit 2146 /USMAAN SAEED/Supervisory Patent Examiner, Art Unit 2146

Prosecution Timeline

• Nov 03, 2023: Application Filed
• Jun 16, 2026: Non-Final Rejection mailed — §101, §103, §112 (current)