Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1) and Sato (US 20120018741 A1).
Regarding claim 1, Hiyoshi discloses a semiconductor device (1) comprising: a conductive pattern (132) provided on an insulating substrate (130) (paragraph 52, Fig. 2); and a plurality of semiconductor chips (140a-e, Fig. 2) that is mounted on the conductive pattern and electrically connected in parallel to each other (paragraph 22) and that includes a first semiconductor chip and two or more second semiconductor chips (Fig, 2)
However, Hiyoshi does not disclose wherein the first semiconductor chip is more likely to be affected by thermal interference than the two or more second semiconductor chips, and a thickness of the conductive pattern immediately below the first semiconductor chip is larger than a thickness of the conductive pattern immediately below each of the two or more second semiconductor chips.
On the other hand, Sato disclose first semiconductor chip is more likely to be affected by thermal interference than the two or more second semiconductor chips (paragraph 21).
On the other hand, Danno et al. disclose a thickness of the conductive pattern (DP2, paragraph 67: die pads can be conductive) immediately below the first semiconductor chip (CP2) is larger than a thickness of the conductive pattern immediately below the other semiconductor chip (DP1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyoshi in view of Danno and Sato such that the conductive pattern is thicker below one of the semiconductor chips than a second semiconductor chip. Doing so would improve thermal management and enable high-power handling.
Regarding claim 15, Hiyoshi discloses the semiconductor device according to claim 1, wherein each semiconductor chip in the plurality of semiconductor chips connected in parallel has an identical structure (paragraph 53, Fig. 1).
Claims 4, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1) and Sato (US 20120018741 A1) as applied to claims 1 above, in further view of Hamaguchi et al (US 20220173043 A1).
Regarding claim 4, Hiyoshi, Danno, and Sato are discussed above. None of these references disclose the semiconductor device according to claim 2, wherein each of the plurality of semiconductor chips connected in parallel is a power semiconductor chip including a switching element.
However, Hamaguchi et al. disclose each of the plurality of semiconductor chips (10-1, 10-2) connected in parallel (Fig. 1) is a power semiconductor chip including a switching element (paragraph 72).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyoshi, Danno, and Sato in view of Hamaguchi such that each of the semiconductor chip connected in parallel is a power semiconductor chip including a switching element. Doing so would increase the total current-carrying capacity and power handling of the module while reducing conduction losses.
Regarding claim 18, Hiyoshi discloses the semiconductor device according to claim 4, wherein each semiconductor chip in the plurality of semiconductor chips connected in parallel has an identical structure (paragraph 53, Fig. 1).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1), Sato (US 20120018741 A1), and Hamaguchi et al (US 20220173043 A1) as applied to claim 4 above, in further view of Yano (US 20210098428 A1).
Regarding claim 10, Hiyoshi, Danno, Sato and Hamaguchi are discussed above. None of these references disclose the semiconductor device according to claim 4, wherein the plurality of semiconductor chips connected in parallel includes three semiconductor chips including the first semiconductor chip and a pair of the second semiconductor chips.
However, Yano discloses the plurality of semiconductor chips connected in parallel includes three semiconductor chips (17, 19, 21, Fig.2) including the first semiconductor chip (32) and a pair of the second semiconductor chips (17, 19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyoshi, Danno, and Sato in view of Yano such that he plurality of semiconductor chips are connected in parallel. Doing so would maximize performance, increase power efficiency, and improve manufacturing yield.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1), Sato (US 20120018741 A1) and Hamaguchi et al (US 20220173043 A1) as applied to claim 4 above, in further view of Kitajima et al. (US 20190109116 A1).
Regarding claim 14, Hiyoshi, Danno, Sato and Hamaguchi are discussed above. None of these references disclose the semiconductor device according to claim 4, wherein the plurality of semiconductor chips connected in parallel includes four semiconductor chips including a pair of the first semiconductor chips and a pair of the second semiconductor chips.
However, Kitajima et al. disclose the plurality of semiconductor chips connected in parallel includes four semiconductor chips (Fig. 5A) including a pair of the first semiconductor chips (100a) and a pair of the second semiconductor chips (100b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the prior references in view of Kitajima such that the four semiconductor chips are connected in parallel including a pair of the first semiconductor chip and a pair of the second semiconductor chip. Doing so would increase total current capacity, reduce power dissipation, and improve thermal management.
Claims 7, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1) and Sato (US 20120018741 A1) as applied to claim 1 above, in further view of Yano (US 20210098428 A1).
Regarding claim 7, Hiyoshi, Danno, and Sato are discussed above. None of these references disclose the semiconductor device according to claim 1, wherein the plurality of semiconductor chips connected in parallel includes three semiconductor chips including the first semiconductor chip and a pair of the second semiconductor chips.
However, Yano discloses the plurality of semiconductor chips connected in parallel includes three semiconductor chips (17, 19, 21, Fig.2) including the first semiconductor chip (32) and a pair of the second semiconductor chips (17, 19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyoshi, Danno, and Sato in view of Yano such that he plurality of semiconductor chips are connected in parallel. Doing so would maximize performance, increase power efficiency, and improve manufacturing yield.
Regarding claim 19, Hiyoshi discloses the semiconductor device according to claim 7, wherein each semiconductor chip in the plurality of semiconductor chips connected in parallel has an identical structure (paragraph 53, Fig. 1).
Claims 11, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1) and Sato (US 20120018741 A1) as applied to claim 1 above, in further view of Kitajima et al. (US 20190109116 A1).
Regarding claim 11, Hiyoshi, Danno, and Sato are discussed above. None of these references disclose the semiconductor device according to claim 1, wherein the plurality of semiconductor chips connected in parallel includes four semiconductor chips including a pair of the first semiconductor chips and a pair of the second semiconductor chips.
However, Kitajima et al. disclose the plurality of semiconductor chips connected in parallel includes four semiconductor chips (Fig. 5A) including a pair of the first semiconductor chips (100a) and a pair of the second semiconductor chips (100b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the prior references in view of Kitajima such that the four semiconductor chips are connected in parallel including a pair of the first semiconductor chip and a pair of the second semiconductor chip. Doing so would increase total current capacity, reduce power dissipation, and improve thermal management.
Regarding claim 20, Hiyoshi discloses the semiconductor device according to claim 11, wherein each semiconductor chip in the plurality of semiconductor chips connected in parallel has an identical structure (paragraph 53, Fig. 1).
Claims 2, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1) and Sato (US 20120018741 A1).
Regarding claim 2, Hiyoshi discloses a semiconductor device (1) comprising:
a conductive pattern (132) provided on an insulating substrate (130, Fig.2); and
a plurality of semiconductor chips (140a-e, Fig. 2) that is mounted on the conductive pattern and electrically connected in parallel to each other (paragraph 22) and that includes a first semiconductor chip and two or more second semiconductor chips (Fig. 2),
However, Hiyoshi does not disclose wherein the first semiconductor chip is more likely to be affected by thermal interference than the two or more second semiconductor chips, and a thickness of the conductive pattern immediately below the first semiconductor chip is smaller than a thickness of the conductive pattern immediately below each of the two or more second semiconductor chips.
On the other hand, Sato disclose first semiconductor chip is more likely to be affected by thermal interference than the two or more second semiconductor chips (paragraph 21).
On the other hand, Danno et al. disclose a thickness of the conductive pattern immediately below the semiconductor chip (DP1) is smaller than a thickness of the conductive pattern immediately below the other semiconductor chip (DP2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyoshi in view of Danno and Sato such that the conductive pattern is smaller below one of the semiconductor chips than a second or more semiconductor chip. Doing so would improve thermal management and enable high-power handling.
Regarding claim 16, Hiyoshi discloses the semiconductor device according to claim 2, wherein each semiconductor chip in the plurality of semiconductor chips connected in parallel has an identical structure (paragraph 53, Fig. 1).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1) and Sato (US 20120018741 A1) as applied to claim 2 above, in further view of Hamaguchi et al (US 20220173043 A1).
Regarding claim 5, Hiyoshi, Danno, and Sato are discussed above. None of these references disclose the semiconductor device according to claim 2, wherein each of the plurality of semiconductor chips connected in parallel is a power semiconductor chip including a switching element.
However, Hamaguchi et al. disclose each of the plurality of semiconductor chips (10-1, 10-2) connected in parallel (Fig. 1) is a power semiconductor chip including a switching element (paragraph 72).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyoshi, Danno, and Sato in view of Hamaguchi such that each of the semiconductor chip connected in parallel is a power semiconductor chip including a switching element. Doing so would increase the total current-carrying capacity and power handling of the module while reducing conduction losses.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1) and Sato (US 20120018741 A1) as applied to claim 2 above, in further view of Yano (US 20210098428 A1).
Regarding claim 8, Hiyoshi, Danno, and Sato are discussed above. None of these references disclose the semiconductor device, wherein the plurality of semiconductor chips connected in parallel includes three semiconductor chips including the first semiconductor chip and a pair of the second semiconductor chips.
However, Yano discloses the plurality of semiconductor chips connected in parallel includes three semiconductor chips (17, 19, 21, Fig.2) including the first semiconductor chip (32) and a pair of the second semiconductor chips (17, 19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyoshi, Danno, and Sato in view of Yano such that he plurality of semiconductor chips are connected in parallel. Doing so would maximize performance, increase power efficiency, and improve manufacturing yield.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1) and Sato (US 20120018741 A1) as applied to claim 2 above, in further view of Kitajima et al. (US 20190109116 A1).
Regarding claim 12, Hiyoshi, Danno, and Sato are discussed above. None of these references disclose the semiconductor device, wherein the plurality of semiconductor chips connected in parallel includes four semiconductor chips including a pair of the first semiconductor chips and a pair of the second semiconductor chips.
However, Kitajima et al. disclose the plurality of semiconductor chips connected in parallel includes four semiconductor chips (Fig. 5A) including a pair of the first semiconductor chips (100a) and a pair of the second semiconductor chips (100b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the prior references in view of Kitajima such that the four semiconductor chips are connected in parallel including a pair of the first semiconductor chip and a pair of the second semiconductor chip. Doing so would increase total current capacity, reduce power dissipation, and improve thermal management.
Claims 3, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1).
Regarding claim 3, Hiyoshi discloses a semiconductor device (1) comprising: a conductive pattern (132) provided on an insulating substrate (130, Fig. 2); and a plurality of semiconductor chips (140a-e, Fig. 2) that is mounted on the conductive pattern and electrically connected in parallel to each other (paragraph 22) and that includes a first semiconductor chip and two or more second semiconductor chips (Fig. 2), wherein the first semiconductor chip (140c) is placed between the two or more second semiconductor chips (140a-b, d-e) in a plan view (Fig. 1).
However, Hiyoshi does not disclose a thickness of the conductive pattern immediately below the first semiconductor chip is different from a thickness of the conductive pattern immediately below each of the two or more second semiconductor chips.
On the other hand, Danno et al. disclose a thickness of the conductive pattern immediately below the first semiconductor chip (DP2) is different from a thickness of the conductive pattern immediately below each of the two or more second semiconductor chips (DP1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyoshi in view of Danno such that the conductive pattern is thicker below one of the semiconductor chips than a second semiconductor chip. Doing so would improve thermal management and enable high-power handling.
Regarding claim 17, Hiyoshi discloses the semiconductor device according to claim 3, wherein each semiconductor chip in the plurality of semiconductor chips connected in parallel has an identical structure (paragraph 53, Fig. 1).
Claim 6 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1) as applied to claim 3 above, in further view of Hamaguchi et al (US 20220173043 A1).
Regarding claim 6, Hiyoshi and Danno are discussed above. None of these references disclose the semiconductor device, wherein each of the plurality of semiconductor chips connected in parallel is a power semiconductor chip including a switching element.
However, Hamaguchi et al. disclose each of the plurality of semiconductor chips (10-1, 10-2) connected in parallel (Fig. 1) is a power semiconductor chip including a switching element (paragraph 72).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyoshi and Danno in view of Hamaguchi such that each of the semiconductor chip connected in parallel is a power semiconductor chip including a switching element. Doing so would increase the total current-carrying capacity and power handling of the module while reducing conduction losses.
Claim 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1) as applied to claim 3 above, in further view of Yano (US 20210098428 A1).
Regarding claim 9, Hiyoshi and Danno are discussed above. None of these references disclose the semiconductor device according to claim 3, wherein the plurality of semiconductor chips connected in parallel includes three semiconductor chips including the first semiconductor chip and a pair of the second semiconductor chips.
However, Yano discloses the plurality of semiconductor chips connected in parallel includes three semiconductor chips (17, 19, 21, Fig.2) including the first semiconductor chip (32) and a pair of the second semiconductor chips (17, 19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyoshi and Danno in view of Yano such that he plurality of semiconductor chips are connected in parallel. Doing so would maximize performance, increase power efficiency, and improve manufacturing yield.
Claims 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20240413090 A1) in view of Danno et al. (US 20170077069 A1) as applied to claim 3 above, in further view of Kitajima et al. (US 20190109116 A1).
Regarding claim 13, Hiyoshi and Danno are discussed above. None of these references disclose the semiconductor device, wherein the plurality of semiconductor chips connected in parallel includes four semiconductor chips including a pair of the first semiconductor chips and a pair of the second semiconductor chips.
However, Kitajima et al. disclose the plurality of semiconductor chips connected in parallel includes four semiconductor chips (Fig. 5A) including a pair of the first semiconductor chips (100a) and a pair of the second semiconductor chips (100b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the prior references in view of Kitajima such that the four semiconductor chips are connected in parallel including a pair of the first semiconductor chip and a pair of the second semiconductor chip. Doing so would increase total current capacity, reduce power dissipation, and improve thermal management.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVE PHAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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