DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Claims 1 and 19-20 are amended.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1-13, 15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2024/0282783), hereinafter referred to as Wu, in view of Wang (US 2023/0154935), hereinafter referred to as Wang, in further view of Yang (US 2022/0140277), hereinafter referred to as Yang.
8. Regarding claim 1, Wu discloses a display panel, comprising: an array layer, wherein, along a thickness direction of the display panel, the array layer comprises at least a first conductive layer and a second conductive layer, and at least an insulating layer is located between the first conductive layer and the second conductive layer (fig. 2-3, paragraph 82 wherein the second gate insulating layer is further included between the active layer and the second gate. In the above-described step, the entire insulating layer may be first formed between the active layer and the conductive layer);
and at least one first through-hole, wherein the first conductive layer and the second conductive layer are connected to each other through the at least one first through-hole, and at least one of the at least one first through-hole is reused as an alignment connection hole (paragraphs 84-85 wherein the first gate is used as a mask to form the second gate and the second gate insulating layer, so that the self-alignment of the first gate and the second gate is realized, and wherein the source is connected to the source region of the active layer through the first via hole in the interlayer dielectric layer).
However, Wu is silent in regards to disclosing a light-emitting element located at a side of the array layer facing a light-exiting surface of the display panel; and, along the thickness direction of the display panel, orthographic projections of at least two of the at least one first through-hole onto a plane of the light-exiting surface of the display panel have different shapes.
Wang discloses a light-emitting element located at a side of the array layer facing a light-exiting surface of the display panel (paragraph 50-52 wherein in the display substrate provided in this embodiment, the conductive connection portion may include conductive structures in a plurality of layers, wherein the pixel electrode is the light-emitting element).
Wang provides motivation to combine the references wherein improvements to this invention will result in a greater loss of electrical signals and therefore a larger voltage difference between the common electrodes thereby affecting the uniformity of the display panel and reducing the quality of the displayed picture (paragraph 4). Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine the teachings of Wu with the display array of Wang in order to keep a higher uniformity of display without reducing the quality of the displayed picture (paragraph 4).
However, Wu and Wang are silent in regards to disclosing and along the thickness direction of the display panel, orthographic projections of at least two of the at least one first through-hole onto a plane of the light-exiting surface of the display panel have different shapes such that the first through-hole that has a relatively different shape in terms of the orthographic projection is reused as an alignment connection hole.
Yang discloses and along the thickness direction of the display panel, orthographic projections of at least two of the at least one first through-hole onto a plane of the light-exiting surface of the display panel have different shapes such that the first through-hole that has a relatively different shape in terms of the orthographic projection is reused as an alignment connection hole (paragraphs 60-61 and 93 wherein the specific edge is the edge closest to the orthographic projection of the connection via hole on the second primary reflecting electrode. In this way, on the premise of reducing the poor connection of the connection via hole caused by etching alignment offset, the connection via hole is close to the edge of the second primary reflecting electrode as much as possible, and wherein the shape of the first primary reflecting electrode may be circular, square, triangular, hexagonal, or other shapes).
Yang provides motivation to combine the references wherein a light-emitting device layer on a side of the first insulating layer away from the driving circuit layer and comprising a second reflecting electrode layer (paragraph 9). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wu and Wang with the display of Yang (paragraph 9).
9. Regarding claim 2, Wang discloses the display panel according to claim 1, wherein the array layer further comprises a connection electrode electrically connected to the light-emitting element, and the connection electrode reuses the first conductive layer (paragraph 46 wherein the base includes a plurality of pixel units distributed thereon in an array, each of which includes a pixel electrode and a thin-film transistor);
and wherein the first conductive layer is located at a side of the second conductive layer facing the light-emitting element (paragraph 50-52 wherein in the display substrate provided in this embodiment, the conductive connection portion may include conductive structures in a plurality of layers, wherein the pixel electrode is the light-emitting element).
10. Regarding claim 3, Wu discloses the display panel according to claim 1, wherein the array layer further comprises a capacitor, and one electrode plate of the capacitor reuses the first conductive layer (paragraph 63-64 wherein a driving backplane, and a display panel to alleviate a technical problem of a large parasitic capacitance existing in an existing driving backplane having a transistor with a double-gate structure).
Wang discloses wherein the first conductive layer is located at a side of the second conductive layer facing the light-emitting element (paragraph 50-52 wherein in the display substrate provided in this embodiment, the conductive connection portion may include conductive structures in a plurality of layers, wherein the pixel electrode is the light-emitting element).
11. Regarding claim 4, Wang discloses the display panel according to claim 1, wherein the array layer further comprises a first transistor, and a source-drain layer of the first transistor reuses the first conductive layer (paragraph 50 wherein the pixel electrode is connected to the drain electrode of the thin-film transistor through a first via disposed in the interlayer insulation layer);
and wherein the first conductive layer is located at a side of the second conductive layer facing the light-emitting element (paragraph 71 wherein a specific layer structure of the conductive connection portion on the right side).
12. Regarding claim 5, Wu discloses the display panel according to claim 1, wherein the array layer further comprises capacitors; wherein, along the thickness direction of the display panel, at least one of the capacitors comprises a first electrode plate and a second electrode plate that are opposite to each other, and the first electrode plate is located at a side of the second electrode plate facing the light-emitting element (fig. 2-3, paragraph 82-83 and 87 wherein the second gate insulating layer is further included between the active layer and the second gate. In the above-described step, the entire insulating layer may be first formed between the active layer and the conductive layer, and wherein the first gate overlaps the source region and/or the drain region in the vertical direction to generate a parasitic capacitance, and wherein the driving backplane of the present disclosure may be used to drive the light-emitting device);
wherein the first electrode plate reuses the first conductive layer (paragraph 75 wherein a metal layer of the source electrode/the drain electrode and a transparent conductive layer of the pixel electrode are formed).
Wang discloses wherein the first conductive layer is located at a side of the second conductive layer facing the light-emitting element (paragraph 50-52 wherein in the display substrate provided in this embodiment, the conductive connection portion may include conductive structures in a plurality of layers, wherein the pixel electrode is the light-emitting element).
13. Regarding claim 6, Wu discloses the display panel according to claim 5, wherein the array layer further comprises a first active layer, and, along the thickness direction of the display panel, the first active layer is located at a side of the second conductive layer away from the first conductive layer (paragraph 79 wherein when dual self-alignment is realized, the active layer, a conductive layer, and a photoresist layer which are stacked are first prepared on the side of the first gate away from the substrate 101, and each of the conductive layer and the photoresist layer is prepared as whole).
Wang discloses wherein the array layer further comprises a second transistor, wherein a source-drain layer of the second transistor is arranged in the first conductive layer, an active layer of the second transistor is arranged in the first active layer, and the second electrode plate is arranged in the second conductive layer (paragraph 50 wherein the pixel electrode is connected to the drain electrode of the thin-film transistor through a first via disposed in the interlayer insulation layer).
14. Regarding claim 7. Wu discloses the display panel according to claim 5, wherein the array layer further comprises a capacitor intermediate layer located between the first electrode plate and the second electrode plate (fig. 2-3, paragraph 82-83 and 87 wherein the second gate insulating layer is further included between the active layer and the second gate. In the above-described step, the entire insulating layer may be first formed between the active layer and the conductive layer, and wherein the first gate overlaps the source region and/or the drain region in the vertical direction to generate a parasitic capacitance, and wherein the driving backplane of the present disclosure may be used to drive the light-emitting device);
wherein, along the thickness direction of the display panel, the capacitor intermediate layer at least partially overlaps with the first electrode plate, and the capacitor intermediate layer at least partially overlaps with the second electrode plate (fig. 2-3, paragraph 82-83 and 87 wherein the second gate insulating layer is further included between the active layer and the second gate. In the above-described step, the entire insulating layer may be first formed between the active layer and the conductive layer, and wherein the first gate overlaps the source region and/or the drain region in the vertical direction to generate a parasitic capacitance, and wherein the driving backplane of the present disclosure may be used to drive the light-emitting device);
and wherein the display panel further comprises at least one second through-hole, the first electrode plate and the capacitor intermediate layer are connected to each other through the at least one second through-hole, and at least one of the at least one second through-hole is reused as the alignment connection hole (paragraphs 84-85 wherein the first gate is used as a mask to form the second gate and the second gate insulating layer, so that the self-alignment of the first gate and the second gate is realized, and wherein the source is connected to the source region of the active layer through the first via hole in the interlayer dielectric layer).
15. Regarding claim 8, Wu discloses the display panel according to claim 1, wherein the array layer further comprises a third conductive layer, and along the thickness direction of the display panel, the first conductive layer is located at a side of the second conductive layer facing the light-emitting element, and the third conductive layer is located at a side of the first conductive layer away from the second conductive layer (paragraph 79 wherein when dual self-alignment is realized, the active layer, a conductive layer, and a photoresist layer which are stacked are first prepared on the side of the first gate away from the substrate, and each of the conductive layer and the photoresist layer is prepared as whole);
and wherein the display panel further comprises at least one second through-hole, wherein the first conductive layer and the third conductive layer are connected to each other through the at least one second through-hole, and at least one of the at least one second through-hole is reused as the alignment connection hole (paragraphs 84-85 wherein the first gate is used as a mask to form the second gate and the second gate insulating layer, so that the self-alignment of the first gate and the second gate is realized, and wherein the source is connected to the source region of the active layer through the first via hole in the interlayer dielectric layer).
16. Regarding claim 9, Wang discloses the display panel according to claim 7, wherein along the thickness direction of the display panel, an orthographic projection of at least one of the at least one first through-hole onto the plane of the light-exiting surface of the display panel and an orthographic projection of at least one of the at least one second through-hole onto the plane of the light-exiting surface of the display panel have a same shape (paragraph 59 wherein an orthographic projection of the strip-shaped sub-electrode of the common electrode on the base overlaps with an orthographic projection of the corresponding slit of the pixel electrode on the base).
17. Regarding claim 10, Wang discloses the display panel according to claim 1, wherein the array layer further comprises at least one second through-hole, and along the thickness direction of the display panel, the at least one second through-hole is located at a side of the at least one first through-hole away from the light-emitting element (paragraph 59 wherein an orthographic projection of the strip-shaped sub-electrode of the common electrode on the base overlaps with an orthographic projection of the corresponding slit of the pixel electrode on the base).
Wu discloses wherein, along the thickness direction of the display panel, the at least one second through-hole does not overlap with the alignment connection hole (fig. 2-3, paragraph 82-83 and 87 wherein the second gate insulating layer is further included between the active layer and the second gate. In the above-described step, the entire insulating layer may be first formed between the active layer and the conductive layer, and wherein the first gate overlaps the source region and/or the drain region in the vertical direction to generate a parasitic capacitance, and wherein the driving backplane of the present disclosure may be used to drive the light-emitting device).
18. Regarding claim 11, Wang discloses the display panel according to claim 1, wherein the light-emitting element comprises at least a first color light-emitting element (paragraph 58 wherein the common electrode and the pixel electrode may be disposed on a color film substrate and an array substrate);
wherein the array layer further comprises a first connection electrode electrically connected to the first color light-emitting element, and the first connection electrode reuses the first conductive layer (paragraph 54 wherein a metal layer of the source electrode/the drain electrode and a transparent conductive layer of the pixel electrode are formed);
and/or wherein the array layer further comprises a first capacitor corresponding to the first color light-emitting element, and one electrode plate of the first capacitor reuses the first conductive layer (paragraph 69 wherein the first gate line sub-portion having a smaller width of the gate line overlaps with the corresponding data line 8 and the main body of the conductive connection portion, so that a coupling capacitance between the gate line and the data line can be reduced);
and/or wherein the array layer further comprises a third transistor corresponding to the first color light-emitting element, and a source-drain layer of the third transistor reuses the first conductive layer (paragraph 50 wherein the pixel electrode is connected to the drain electrode of the thin-film transistor through a first via disposed in the interlayer insulation layer);
wherein the first color light-emitting element does not comprise a green color light-emitting element (paragraph 79 wherein each pixel unit may include a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit);
and wherein the first conductive layer is located at a side of the second conductive layer facing the light-emitting element (paragraph 50-52 wherein in the display substrate provided in this embodiment, the conductive connection portion may include conductive structures in a plurality of layers, wherein the pixel electrode is the light-emitting element).
19. Regarding claim 12, Wu discloses the display panel according to claim 1, further comprising: at least one first connection hole (paragraphs 84-85 wherein the first gate is used as a mask to form the second gate and the second gate insulating layer, so that the self-alignment of the first gate and the second gate is realized, and wherein the source is connected to the source region of the active layer through the first via hole in the interlayer dielectric layer);
wherein the first through-hole of the at least one first through-hole that is not reused as the alignment connection hole is the first connection hole (paragraphs 84-85 wherein the first gate is used as a mask to form the second gate and the second gate insulating layer, so that the self-alignment of the first gate and the second gate is realized, and wherein the source is connected to the source region of the active layer through the first via hole in the interlayer dielectric layer).
Wang discloses wherein, along the thickness direction of the display panel, for orthographic projections of the at least one first through-hole onto the plane of the light-exiting surface of the display panel, at least one first connection hole is located between two alignment connection holes along the direction of the plane of the light-exiting surface of the display panel (paragraph 59 wherein an orthographic projection of the strip-shaped sub-electrode of the common electrode on the base overlaps with an orthographic projection of the corresponding slit of the pixel electrode on the base).
20. Regarding claim 13, Wu discloses the display panel according to claim 1, wherein the display panel comprises a light shielding member (paragraph 4 wherein the light-shielding layer serves as a first gate, and the source-drain layer further includes a double-gate connection line connected to the second gate through a third via hole and to the light shielding layer through a fourth via hole);
and wherein, along the thickness direction of the display panel, the light shielding member is located at a side of the first conductive layer away from the second conductive layer, and a side of the alignment connection hole facing the light-exiting surface of the display panel does not overlap with the light shielding member (paragraph 81 wherein non-shielded regions of the active layer are conductorized to form the source region and the drain region, and a shielded region of the active layer is formed as the channel region, so that the self-alignment of the second gate, and the source region and the drain region is realized).
21. Regarding claim 15, Wu discloses the display panel according to claim 1, further comprising: a display region and a non-display region at least partially surrounding the display region, wherein the display region comprises a first display region and a second display region surrounding the first display region, and the alignment connection hole is located within the second display region (paragraph 133 wherein a display panel including a driving backplane and a light-emitting structure connected to the driving backplane, the driving backplane is the driving backplane described in any one of the above embodiments, the light-emitting structure may be a Mini LED, a Micro LED, an OLED, a liquid crystal layer, or the like).
22. Regarding claim 18, Wu discloses the display panel according to claim 1, wherein, along the thickness direction of the display panel, the alignment connection hole is cross-shaped (fig. 7C, paragraph 79 wherein when dual self-alignment is realized, the active layer, a conductive layer, and a photoresist layer which are stacked are first prepared on the side of the first gate away from the substrate, and each of the conductive layer and the photoresist layer is prepared as whole.).
23. Regarding claim 19, Wu discloses a display device, comprising a display panel comprising: an array layer, wherein, along a thickness direction of the display panel, the array layer comprises at least a first conductive layer and a second conductive layer, and at least an insulating layer is located between the first conductive layer and the second conductive layer (fig. 2-3, paragraph 82 wherein the second gate insulating layer is further included between the active layer and the second gate. In the above-described step, the entire insulating layer may be first formed between the active layer and the conductive layer);
and at least one first through-hole, wherein the first conductive layer and the second conductive layer are connected to each other through the at least one first through-hole, and at least one of the at least one first through-hole is reused as an alignment connection hole (paragraphs 84-85 wherein the first gate is used as a mask to form the second gate and the second gate insulating layer, so that the self-alignment of the first gate and the second gate is realized, and wherein the source is connected to the source region of the active layer through the first via hole in the interlayer dielectric layer).
However, Wu is silent in regards to disclosing a light-emitting element located at a side of the array layer facing a light-exiting surface of the display panel; and/or, along the thickness direction of the display panel, orthographic projections of at least two of the at least one first through-hole onto a plane of the light-exiting surface of the display panel have different shapes.
Wang discloses a light-emitting element located at a side of the array layer facing a light-exiting surface of the display panel (paragraph 50-52 wherein in the display substrate provided in this embodiment, the conductive connection portion may include conductive structures in a plurality of layers, wherein the pixel electrode is the light-emitting element).
Wang provides motivation to combine the references wherein improvements to this invention will result in a greater loss of electrical signals and therefore a larger voltage difference between the common electrodes thereby affecting the uniformity of the display panel and reducing the quality of the displayed picture (paragraph 4). Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine the teachings of Wu with the display array of Wang in order to keep a higher uniformity of display without reducing the quality of the displayed picture (paragraph 4).
However, Wu and Wang are silent in regards to disclosing and along the thickness direction of the display panel, orthographic projections of at least two of the at least one first through-hole onto a plane of the light-exiting surface of the display panel have different shapes such that the first through-hole that has a relatively different shape in terms of the orthographic projection is reused as an alignment connection hole.
Yang discloses and along the thickness direction of the display panel, orthographic projections of at least two of the at least one first through-hole onto a plane of the light-exiting surface of the display panel have different shapes such that the first through-hole that has a relatively different shape in terms of the orthographic projection is reused as an alignment connection hole (paragraphs 60-61 and 93 wherein the specific edge is the edge closest to the orthographic projection of the connection via hole on the second primary reflecting electrode. In this way, on the premise of reducing the poor connection of the connection via hole caused by etching alignment offset, the connection via hole is close to the edge of the second primary reflecting electrode as much as possible, and wherein the shape of the first primary reflecting electrode may be circular, square, triangular, hexagonal, or other shapes).
Yang provides motivation to combine the references wherein a light-emitting device layer on a side of the first insulating layer away from the driving circuit layer and comprising a second reflecting electrode layer (paragraph 9). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wu and Wang with the display of Yang (paragraph 9).
24. Regarding claim 20, Wu discloses a detection device for a display panel, wherein the detection device comprises a recognition device, and the display panel comprises: an array layer, wherein, along a thickness direction of the display panel, the array layer comprises at least a first conductive layer and a second conductive layer, and at least an insulating layer is located between the first conductive layer and the second conductive layer (fig. 2-3, paragraph 82 wherein the second gate insulating layer is further included between the active layer and the second gate. In the above-described step, the entire insulating layer may be first formed between the active layer and the conductive layer);
and at least one first through-hole, wherein the first conductive layer and the second conductive layer are connected to each other through the at least one first through-hole, and at least one of the at least one first through-hole is reused as an alignment connection hole (paragraphs 84-85 wherein the first gate is used as a mask to form the second gate and the second gate insulating layer, so that the self-alignment of the first gate and the second gate is realized, and wherein the source is connected to the source region of the active layer through the first via hole in the interlayer dielectric layer).
However, Wu is silent in regards to disclosing a light-emitting element located at a side of the array layer facing a light-exiting surface of the display panel; and/or, along the thickness direction of the display panel, orthographic projections of at least two of the at least one first through-hole onto a plane of the light-exiting surface of the display panel have different shapes, and wherein the recognition device is located at a side of the light-exiting surface of the display panel, and the recognition device is configured to photograph the display panel to recognize the alignment connection hole in the display panel.
Wang discloses a light-emitting element located at a side of the array layer facing a light-exiting surface of the display panel (paragraph 50-52 wherein in the display substrate provided in this embodiment, the conductive connection portion may include conductive structures in a plurality of layers, wherein the pixel electrode is the light-emitting element).
Wang provides motivation to combine the references wherein improvements to this invention will result in a greater loss of electrical signals and therefore a larger voltage difference between the common electrodes thereby affecting the uniformity of the display panel and reducing the quality of the displayed picture (paragraph 4). Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine the teachings of Wu with the display array of Wang in order to keep a higher uniformity of display without reducing the quality of the displayed picture (paragraph 4).
However, Wu and Wang are silent in regards to disclosing and along the thickness direction of the display panel, orthographic projections of at least two of the at least one first through-hole onto a plane of the light-exiting surface of the display panel have different shapes such that the first through-hole that has a relatively different shape in terms of the orthographic projection is reused as an alignment connection hole.
Yang discloses and along the thickness direction of the display panel, orthographic projections of at least two of the at least one first through-hole onto a plane of the light-exiting surface of the display panel have different shapes such that the first through-hole that has a relatively different shape in terms of the orthographic projection is reused as an alignment connection hole (paragraphs 60-61 and 93 wherein the specific edge is the edge closest to the orthographic projection of the connection via hole on the second primary reflecting electrode. In this way, on the premise of reducing the poor connection of the connection via hole caused by etching alignment offset, the connection via hole is close to the edge of the second primary reflecting electrode as much as possible, and wherein the shape of the first primary reflecting electrode may be circular, square, triangular, hexagonal, or other shapes).
Yang provides motivation to combine the references wherein a light-emitting device layer on a side of the first insulating layer away from the driving circuit layer and comprising a second reflecting electrode layer (paragraph 9). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wu and Wang with the display of Yang (paragraph 9).
25. Claims 14 and16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Wu, in view of Wang, in further view of Yang, in further in view of Li (2020/0185597), hereinafter referred to as Li.
26. Regarding claim 14, Wu, Wang and Yang are silent in regards to disclosing the display panel according to claim 1, further comprising at least two alignment connection holes, wherein the light-exiting surface of the display panel is in an axisymmetric shape, wherein the axisymmetric shape comprises at least one first symmetry axis located in the plane of the light-exiting surface of the display panel, and the at least two alignment connection holes are symmetrically arranged about the first symmetry axis
However, Li discloses the display panel according to claim 1, further comprising at least two alignment connection holes, wherein the light-exiting surface of the display panel is in an axisymmetric shape, wherein the axisymmetric shape comprises at least one first symmetry axis located in the plane of the light-exiting surface of the display panel, and the at least two alignment connection holes are symmetrically arranged about the first symmetry axis (paragraphs 19 and 21 wherein the connection hole is disposed on the interconnection structure and penetrates the first dielectric layer and the second dielectric layer within the memory cell region).
Lu provides motivation to combine the references wherein alignment marks may be used to assist the alignment in the exposure process and to monitor overlay results for reducing the influence of process variations on the production yield (paragraph 2). Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine the teachings of Wu, Wang and Yang with the display of Li (paragraph 2).
27. Regarding claim 16, Li discloses the display panel according to claim 1, wherein, along the thickness direction of the display panel, the at least one first through-hole is formed by a recess from the first conductive layer towards the second conductive layer (paragraph 15 wherein after the conductive via plugs are formed within the memory cell region, a plurality of alignment mark trenches TR are then formed within the alignment mark region).
28. Regarding claim 17, Li discloses the display panel according to claim 1, wherein at least one of the second conductive layer or the first conductive layer comprises a metal material (paragraph 18 wherein the bottom electrode may include metallic materials, such as titanium, titanium nitride, tantalum, tantalum nitride, platinum (Pt), ruthenium (Ru)).
Conclusion
29. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHARLES N HICKS/ Examiner, Art Unit 2424
/NASSER M GOODARZI/ Supervisory Patent Examiner, Art Unit 2426
/