DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/27/2026 has been entered.
Response to Amendments
Applicant's response of 08/27/2026 has been acknowledged. Claims 14, 26 and 31 have been amended. No new matter has been added.
This office action considers claims 1-33 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant's arguments of 08/27/2026 with respect to the rejections of claims have
been fully considered, and are persuasive. Therefore, the rejection of claims 26-31 have been withdrawn.
Applicant's arguments with respect to claims 26-31 have been fully considered
but are moot in view of the new grounds of rejection.
Claims 26-30 are rejected under 35 U.S.C. 103 as being unpatentable over Gang et al. (US 20180033850 A1 – hereinafter Gang) in view of Lee et al. (US 20210202659 A1 - hereinafter Lee), Jin et al. (US 20130256723 A1 – hereinafter Jin), and Kim et al. (US 20210132424 A1 – hereinafter Kim-424).
Regarding independent claim 26, Gang teaches
(Currently Amended) A display panel (150 – Fig. 1 – [0035] – “display
panel 150 displays”) comprising:
a substrate (SUB – Fig. 6 – [0060] – “substrate SUB”);
a bank (BNK – Fig. 6 – [0088] – “bank layer BNK defining pixels is positioned on
the substrate SUB”) on the substrate (SUB), the bank (BNK) including an opening (Fig. 6 annotated, see below, hereinafter ‘OP’);
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a subpixel (SP – Fig. 1 – [0035] – “subpixels SP”) on the substrate (SUB), the
subpixel (SP) including a thin film transistor (DR – Fig. 6 – [0067] – “driving transistor DR”) and a light emitting element (OLED – Fig. 6 – [0068] – “organic light emitting diode OLED”) connected to the thin film transistor (DR – Fig. 6 shows this), the light emitting element (OLED) in the opening (OP – Fig. 7 annotated, see below, shows this) of the bank (BNK) and including an anode electrode (ANO – Fig. 7 – [0058] – “first electrode ANO”), a light emitting layer (EML – Fig. 7 – [0068] – “emission layer EML”) on the anode electrode (ANO), and a cathode electrode (CAT – Fig. 7 – [0069] – “organic light emitting diode OLED includes a second electrode CAT on the emission layer EML”) on the light emitting layer (EML);
a first signal line configured to supply a first signal to the subpixel ; and
a first active pattern comprising a first cutting area that disconnects the first
signal line and the subpixel, the first cutting area overlapping the light emitting element,
wherein the active pattern comprises a material having oxide, and
wherein the first active pattern is disposed on a layer lower than a layer on which a drain electrode of the thin film transistor is disposed,
wherein the substrate (SUB – Fig. 6 – [0060] – “substrate SUB”) comprises a plurality of pixels (SP – Fig. 1 – [0035] – “subpixels SP” – this is interpreted the sub-pixels are smaller pixels ),
wherein each of the plurality of pixels (SP) comprises at least three subpixels including a first subpixel (SPn1 – Fig. 5 – [0051] – “subpixel SPn1 may be a red subpixel R”), a second subpixel (SPN3 – Fig. 5 – [0051] – “subpixel SPn3 may be a blue subpixel B”), and a third subpixel (SPN3 – Fig. 5 – [0051] – “subpixel SPn2 may be a green subpixel G”), wherein a first active pattern included in the first subpixel comprises a first cutting area, and the first cutting area is disposed in a non-emission area,
wherein a second active pattern included in the second subpixel comprises a second cutting area, and the second cutting area extends from an emission area to a non-emission area, and
wherein a third active pattern included in the third subpixel comprises a third cutting area, and the third cutting area is disposed in a non-emission area.
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Gang does not expressly disclose the other limitations of claim 26.
However, in an analogous art, Lee teaches
a thin film ([0057] – “driving thin film transistor TFT” – hereinafter ‘DR’) transistor,
a first signal line (RL – Fig. – [0244] – “branch line RBL includes a long line
portion RBL-1 in a first direction x and a branch portion RBL-2 which is bent from the line portion RBL-1 in a second direction y intersecting the first direction x and is connected to a pixel circuit. The line portion RBL-1 is connected to a reference voltage line RL and intersects data lines DL1 and DL2”) configured to supply a first signal to the subpixel (SP1 – Fig. 22 – [0157] – “first subpixel SP1”); and
a first active pattern (RBL-2 – Fig. 22 – [0247] – “RBL-2 have a multi-layered
structure in which a semiconductor layer SEM and a third metal layer ML3 are stacked”) comprising a first cutting area (Fig. 22 – [0243] – “cutting line I-I′ in FIG. 22” – hereinafter ‘CTA’) that disconnects the first signal line (RL) and the subpixel (SP1),
wherein the active pattern (SEM) comprises a material having oxide (SEM – Fig. 11A – [0132] – “semiconductor material is deposited on a buffer layer BUF to form a semiconductor layer SEM on the buffer layer BUF. An oxide semiconductor, for example, indium-gallium-zinc oxide (IGZO), can be selected as the semiconductor material”),
wherein a first active pattern (ACT – Fig. 18 – [0231] – “[0231] – “active layer ACT of a transistor TFT” – each sub-pixel has a transistor with an active layer) included in the first subpixel (SP1 – Fig. 3 – [0076] – “pixel P includes subpixels SP1 to SP4”) comprises a first cutting area (Fig. 14 annotated, see below – [0213] – “power line VDDH can be melted to disconnect the horizontal power line VDDH without changing the wavelength of the laser beam” – hereinafter ‘CTA1’”), and the first cutting area (ACT – Fig. 18 – [0231] – “[0231] – “active layer ACT of a transistor TFT”) is disposed in a non-emission area ([0127] – “emission region is substantially the same as an opening APT” – Fig. 8 shows element APT, the cutting areas shown in Fig. 14 are outside the emission area, outside this area is a non-emission area, hereinafter ‘NEA’),
wherein a second active pattern (ACT – Fig. 18 – [0231] – “[0231] – “active layer ACT of a transistor TFT” – each sub-pixel has a transistor with an active layer) included in the second subpixel (SP2 – Fig. 3 – [0076] – “pixel P includes subpixels SP1 to SP4”) comprises a second cutting area (Fig. 14 annotated, see below – [0213] – “power line VDDH can be melted to disconnect the horizontal power line VDDH without changing the wavelength of the laser beam” – hereinafter ‘CTA2’”), and the second cutting area (Fig. 14 annotated, see below – [0213] – “power line VDDH can be melted to disconnect the horizontal power line VDDH without changing the wavelength of the laser beam” – hereinafter ‘CTA2’”) extends from an emission area (EA – Fig. 8 – [0076] – “each pixel P includes subpixels SP1 to SP4 each including an emission part EA and a circuit part CA”) to a non-emission area (NEA) , and
wherein a third active pattern (ACT – Fig. 18 – [0231] – “[0231] – “active layer ACT of a transistor TFT” – each sub-pixel has a transistor with an active layer) included in the third subpixel (SP3 – Fig. 3 – [0076] – “pixel P includes subpixels SP1 to SP4”) comprises a third cutting area ([0210] – “examples of darkening a defective subpixel through laser cutting in a repair process” – other subpixels can be defective so the cutting areas would apply to SP3 and SP4 of Fig. 3 since the circuit layout is symmetrical around element RL), and the third cutting area is disposed in a non-emission area (lee (NEA).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the signal line and active pattern structure as taught by Lee into Gang.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result [0006] - "to providing a display panel in which an aperture ratio of pixels is increased. The present disclosure is directed to providing a repair method of darkening a defective pixel of the display panel."
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Gang and Lee do not expressly disclose the other limitations of claim 26.
However, in an analogous art, Jin teaches
the first cutting area (CL – Fig. 3 – [0050] – “structure of the pixel PE cut by the laser according to the cutting line CL of the OLED display”) overlapping (Fig. 3 shows this) the light emitting element (70 – Fig. 3 – [0041] – “organic light emitting diode 70”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the cutting area structure as taught by Jin into Gang and Lee.
An ordinary artisan would have been motivated to use the known technique of Jin in the manner set forth above to produce the predictable result of performing a laser cut
line overlapping a light emitting element.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Gang, Lee, and Jin do not expressly disclose the other limitations of claim 26.
However, in an analogous art, Kim-424 teaches
wherein the first active pattern (CH – Fig. 2 – [0058] – “active pattern AP including a channel layer CH”) is disposed on a layer lower than a layer ([0058] – “switching element may include an active pattern AP including a channel layer CH, a gate electrode GE overlapping the active pattern AP” – Fig. 2 shows this) on which a drain electrode (DE – Fig. 2 – [0058] – “drain electrode DE”) of the thin film transistor ([0058] – “switching element may include an active pattern AP including a channel layer CH, a gate electrode GE overlapping the active pattern AP” – this is a thin film transistor) is disposed.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the active pattern structure as taught by Kim-424 into Gang, Lee, and Jin.
An ordinary artisan would have been motivated to use the known technique of Kim-424 in the manner set forth above to produce the predictable result of [0059] – “the active pattern AP may include ohmic contact layers OC1 and OC2 for reducing a contact resistance with the source/drain electrodes SE and DE.”
Regarding claim 27, Gang, as modified by Lee, Jin, and Kim-424, teaches claim 26 from which claim 27 depends. Gang, Jin, and Kim-424 do not expressly disclose the limitations of claim 27.
However, in an analogous art, Lee teaches
(Original) The display panel of claim 26, further comprising:
a second signal line (VDDH – Fig. 13 – [0213] – “power line VDDH”)
configured to supply a second signal (VDDH – Fig. 13 – [0213] – “power line VDDH, which supply power (Vref or EVDD) to a pixel circuit”) to the subpixel (SP1);
and
a second active pattern (ML3 – Fig. 23 – [0231] – “active layer ACT of a transistor TFT can have a multi-layered structure in which a semiconductor layer SEML and a third metal layer ML3 are stacked”) overlapping the light emitting element (OLED – [0078] – “light-emitting element OLED” – Fig. 23 shows this) and comprising a second cutting area (Fig. 13 annotated, see below – [0213] – “power line VDDH can be melted to disconnect the horizontal power line VDDH without changing the wavelength of the laser beam” – hereinafter ‘CTA2’”) that disconnects the second signal line (VDDH) and the subpixel (SP1), the second cutting area (CTA2) overlapping the bank (BNK – [0080 – “bank BNK” – Fig. 18 shows BNK overlapping the data line DL and CTA2 is near DL therefore CTA2 overlaps BNK),
wherein the second active pattern (ML3) comprises the material having oxide (RBL – Fig. 17 – [0151] – “A multi-layer portion of the branch line RBL, in which the semiconductor layer and the third metal layer are stacked (hereinafter, referred to as a “branch line having a multi-layered structure”)” – RBL contains ACT and SEM, SEM if formed of IGZO, ACT if formed of ML3, therefor ML3 includes IGZO).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the signal line and active pattern structure as taught by Lee into Gang.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result as stated above in claim 26.
Regarding claim 28, Gang, as modified by Lee, Jin, and Kim-424, teaches claim 27 from which claim 28 depends. Gang, Jin, and Kim-424 do not expressly disclose the limitations of claim 28.
However, in an analogous art, Lee teaches
(Original) The display panel of claim 27, wherein the second active pattern
(ML3) overlaps a light emitting element (OLED) of another subpixel ([0231] – “active layer ACT of a transistor TFT can have a multi-layered structure in which a semiconductor layer SEML and a third metal layer ML3 are stacked” – each subpixel has a transistor therefor ML3 also overlaps OLED of another subpixel).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second active pattern structure as taught by Lee into Gang.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result as stated above in claim 26.
Regarding claim 29, Gang, as modified by Lee, Jin, and Kim-424, teaches claim 26 from which claim 29 depends. Gang, Jin, and Kim-424 do not expressly disclose the limitations of claim 29.
However, in an analogous art, Lee teaches
(Original) The display panel of claim 26, further comprising:
a color filter (CF – Fig. 23 – [0093] – “color filter CF”) between the first active
pattern (SEM) and the light emitting element (OLED – Fig. 23 shows this), and
the color filter (CF) overlapping the first active pattern (SEM) and the light emitting element (OLED – Fig. 23 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the signal line and active pattern structure as taught by Lee into Gang.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result as stated above in claim 26.
Regarding claim 30, Gang, as modified by Lee, Jin, and Kim-424, teaches claim 26 from which claim 30 depends. Gang, Jin, and Kim-424 do not expressly disclose the limitations of claim 30.
However, in an analogous art, Lee teaches
(Original) The display panel of claim 26, wherein the first active pattern
(ACT – Fig. 18 – [0231] – “[0231] – “active layer ACT of a transistor TFT”) comprises a
first layer (SEML – Fig. 23 – [0231] – “active layer ACT of a transistor TFT can have a multi-layered structure in which a semiconductor layer SEML and a third metal layer ML3 are stacked”) and a second layer (ML3 – Fig. 23 – [0231] – “active layer ACT of a transistor TFT can have a multi-layered structure in which a semiconductor layer SEML and a third metal layer ML3 are stacked”) on the first layer (SEML), the first layer (SEML) including oxide semiconductor ({SEML – Fig. 15 – [0219] – “semiconductor layer SEML includes an active layer ACT”}, {SEM – Fig. 11A – [0132] – “semiconductor material is deposited on a buffer layer BUF to form a semiconductor layer SEM on the buffer layer BUF. An oxide semiconductor, for example, indium-gallium-zinc oxide (IGZO), can be selected as the semiconductor material”} – therefore SEML is an oxide semiconductor), and the second layer (ML3) including transparent conductive oxide (RBL – Fig. 17 – [0151] – “A multi-layer portion of the branch line RBL, in which the semiconductor layer and the third metal layer are stacked (hereinafter, referred to as a “branch line having a multi-layered structure”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the active pattern structure as taught by Lee into Gang.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result as stated above in claim 26.
Regarding independent claim 31, Gang teaches
(Currently Amended) A display panel (150 – Fig. 1 – [0035] – “display
panel 150 displays”) comprising:
a substrate;
a bank (BNK – Fig. 6 – [0088] – “bank layer BNK defining pixels is positioned on
the substrate SUB”) on the substrate (SUB), the bank (BNK) including an opening (Fig. 6 annotated, see below, hereinafter ‘OP’);
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a subpixel (SP – Fig. 1 – [0035] – “subpixels SP”) on the substrate (SUB), the
subpixel (SP) including a thin transistor (DR – Fig. 6 – [0067] – “driving transistor DR”) and a light emitting element (OLED – Fig. 6 – [0068] – “organic light emitting diode OLED”) connected to the thin film transistor (DR – Fig. 6 shows this), the light emitting element (OLED) in the opening (OP – Fig. 7 annotated, see below, shows this) of the bank (BNK) and including an anode electrode (ANO – Fig. 7 – [0058] – “first electrode ANO”), a light emitting layer (EML – Fig. 7 – [0068] – “emission layer EML”) on the anode electrode (ANO), and a cathode electrode (CAT – Fig. 7 – [0069] – “organic light emitting diode OLED includes a second electrode CAT on the emission layer EML”) on the light emitting layer (EML);
a signal line configured to supply a signal to the subpixel; and
an active pattern comprising a cutting area that disconnects the signal line and the subpixel, the cutting area overlapping the bank and non-overlapping the light emitting element,
wherein the active pattern comprises a material having oxide, and
wherein the first active pattern is disposed on a layer lower than a layer on which a drain electrode of the thin film transistor is disposed, wherein a first active pattern included in the first subpixel comprises a first cutting area, and the first cutting area is disposed in a non-emission area,
wherein a second active pattern included in the second subpixel comprises a second cutting area, and the second cutting area extends from an emission area to a non-emission area, and
wherein a third active pattern included in the third subpixel comprises a third cutting area, and the third cutting area is disposed in a non-emission area.
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Gang does not expressly disclose the other limitations of claim 31.
However, in an analogous art, Lee teaches
thin film ([0057] – “driving thin film transistor TFT” – hereinafter ‘DR’) transistor,
a signal line (RL – Fig. – [0244] – “branch line RBL includes a long line portion RBL-1 in a first direction x and a branch portion RBL-2 which is bent from the line portion RBL-1 in a second direction y intersecting the first direction x and is connected to a pixel circuit. The line portion RBL-1 is connected to a reference voltage line RL and intersects data lines DL1 and DL2”) configured to supply a signal to the subpixel (lee (SP1 – Fig. 22 – [0157] – “first subpixel SP1”); and
an active pattern comprising a cutting area (Fig. 22 – [0243] – “cutting line I-I′ in FIG. 22” – hereinafter ‘CTA’) that disconnects the signal line (RL) and the subpixel (SP1 – Fig. 2 shows this), the cutting area (CTA) overlapping the bank (BNK) and non-overlapping the light emitting element (OLED – [0078] – “light-emitting element OLED” – Fig. 23 shows this),
wherein the active pattern (SEM) comprises a material having oxide (SEM – Fig. 11A – [0132] – “semiconductor material is deposited on a buffer layer BUF to form a semiconductor layer SEM on the buffer layer BUF. An oxide semiconductor, for example, indium-gallium-zinc oxide (IGZO), can be selected as the semiconductor material”),
wherein a first active pattern (ACT – Fig. 18 – [0231] – “[0231] – “active layer ACT of a transistor TFT” – each sub-pixel has a transistor with an active layer) included in the first subpixel (SP1 – Fig. 3 – [0076] – “pixel P includes subpixels SP1 to SP4”) comprises a first cutting area (Fig. 14 annotated, see below – [0213] – “power line VDDH can be melted to disconnect the horizontal power line VDDH without changing the wavelength of the laser beam” – hereinafter ‘CTA1’”), and the first cutting area (ACT – Fig. 18 – [0231] – “[0231] – “active layer ACT of a transistor TFT”) is disposed in a non-emission area ([0127] – “emission region is substantially the same as an opening APT” – Fig. 8 shows element APT, the cutting areas shown in Fig. 14 are outside the emission area, outside this area is a non-emission area, hereinafter ‘NEA’),
wherein a second active pattern (ACT – Fig. 18 – [0231] – “[0231] – “active layer ACT of a transistor TFT” – each sub-pixel has a transistor with an active layer) included in the second subpixel (SP2 – Fig. 3 – [0076] – “pixel P includes subpixels SP1 to SP4”) comprises a second cutting area (Fig. 14 annotated, see below – [0213] – “power line VDDH can be melted to disconnect the horizontal power line VDDH without changing the wavelength of the laser beam” – hereinafter ‘CTA2’”), and the second cutting area (Fig. 14 annotated, see below – [0213] – “power line VDDH can be melted to disconnect the horizontal power line VDDH without changing the wavelength of the laser beam” – hereinafter ‘CTA2’”) extends from an emission area (EA – Fig. 8 – [0076] – “each pixel P includes subpixels SP1 to SP4 each including an emission part EA and a circuit part CA”) to a non-emission area (NEA) , and
wherein a third active pattern (ACT – Fig. 18 – [0231] – “[0231] – “active layer ACT of a transistor TFT” – each sub-pixel has a transistor with an active layer) included in the third subpixel (SP3 – Fig. 3 – [0076] – “pixel P includes subpixels SP1 to SP4”) comprises a third cutting area ([0210] – “examples of darkening a defective subpixel through laser cutting in a repair process” – other subpixels can be defective so the cutting areas would apply to SP3 and SP4 of Fig. 3 since the circuit layout is symmetrical around element RL), and the third cutting area is disposed in a non-emission area (lee (NEA).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the signal line and active pattern structure as taught by Lee into Gang.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result as stated above in claim 26.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Gang and Lee do not expressly disclose the other limitations of claim 31.
However, in an analogous art, Kim-424 teaches
wherein the first active pattern (CH – Fig. 2 – [0058] – “active pattern AP including a channel layer CH”) is disposed on a layer lower than a layer ([0058] – “switching element may include an active pattern AP including a channel layer CH, a gate electrode GE overlapping the active pattern AP” – Fig. 2 shows this) on which a drain electrode (DE – Fig. 2 – [0058] – “drain electrode DE”) of the thin film transistor ([0058] – “switching element may include an active pattern AP including a channel layer CH, a gate electrode GE overlapping the active pattern AP” – this is a thin film transistor) is disposed.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the active pattern structure as taught by Kim-424 into Gang and Lee.
An ordinary artisan would have been motivated to use the known technique of Kim-424 in the manner set forth above to produce the predictable result as stated above in claim 26.
Regarding claim 32, Gang, as modified by Lee and Kim-424, teaches claim 31 from which claim 32 depends. Gang and Kim-424 do not expressly disclose the limitations of claim 32.
However, in an analogous art, Lee teaches
(Previously Presented) The display panel of claim 31, wherein the first
active pattern (ACT – Fig. 18 – [0231] – “[0231] – “active layer ACT of a transistor TFT”) comprises a first layer (SEML – Fig. 23 – [0231] – “active layer ACT of a transistor TFT can have a multi-layered structure in which a semiconductor layer SEML and a third metal layer ML3 are stacked”) and a second layer (ML3 – Fig. 23 – [0231] – “active layer ACT of a transistor TFT can have a multi-layered structure in which a semiconductor layer SEML and a third metal layer ML3 are stacked”) on the first layer (SEML), the first layer (SEML) including oxide semiconductor ({SEML – Fig. 15 – [0219] – “semiconductor layer SEML includes an active layer ACT”}, {SEM – Fig. 11A – [0132] – “semiconductor material is deposited on a buffer layer BUF to form a semiconductor layer SEM on the buffer layer BUF. An oxide semiconductor, for example, indium-gallium-zinc oxide (IGZO), can be selected as the semiconductor material”} – therefore SEML is an oxide semiconductor), and the second (ML3) layer including transparent conductive oxide (RBL – Fig. 17 – [0151] – “A multi-layer portion of the branch line RBL, in which the semiconductor layer and the third metal layer are stacked (hereinafter, referred to as a “branch line having a multi-layered structure”)” – RBL contains ACT and SEM, SEM if formed of IGZO, ACT if formed of ML3, therefor ML3 includes IGZO).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the active pattern structure as taught by Lee into Gang and Kim-424.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result as stated above in claim 26.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Gang in
view of Lee, Kim-424, and Kim (US 20200075699 A1 - hereinafter Kim).
Regarding claim 33, Gang as modified by Lee, and Kim-424, teaches claim 31 from which claim 33 depends. Gang, Lee, and Kim-424 do not expressly disclose the limitations of claim 33.
However, in an analogous art, Kim teaches
(Original) The display panel of claim 31, wherein the bank comprises black material ([0065] - "the first bank 114 can be formed of a black material").
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the black material structure
as taught by Kim into Gang, Lee, and Kim-424.
An ordinary artisan would have been motivated to use the known technique of
Kim in the manner set forth above to produce the predictable result of [0008] - "when
the light emitting device is formed to be uneven, there is a problem in that scattering
reflectance in an off-state of the light emitting display apparatus is increased so that a
visual feel in an off-state, that is, a black luminance can be degraded and thus not only
the outdoor visibility, but also the contrast ratio can be degraded. [0009] Therefore, the inventor of the present disclosure invented a light emitting display apparatus having a new structure which improves an outdoor visibility."
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Allowable Subject Matter
Claim 1 is allowed.
The following is an examiner's statement of reasons for allowance:
In reference to claim 1, the prior art of record to the examiner's knowledge does
not teach or render obvious, at least to one skilled in the art, the instant invention
regarding wherein cutting areas of the first active pattern and the second active
pattern in the first subpixel and the second subpixel overlap the emission area
in combination with the other recited limitations.
Claims 2-25 depend on claim 1 and are therefore allowable.
Any comments considered necessary by applicant must be submitted no later
than the payment of the issue fee and, to avoid processing delays, should preferably
accompany the issue fee. Such submissions should be clearly labeled "Comments on
Statement of Reasons for Allowance."
Pertinent Art
For the benefits of the Applicant, US 11917870 B2 is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the cut lines.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GRA/
Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
