DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) filed on 11/03/2023, 09/20/2024 and 04/15/2026 have been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Mizutani et al. (hereinafter Mizutani), Japanese Patent JP2000286608A, in view of Oran et al., (hereinafter Oran), U.S. Patent 11,201,602.
Regarding Claim 1, Mizutani teaches (except where italicized), a multilayer electronic component (Figs. 6 and 7) comprising:
a plurality of resonators (30a-30c, 200a-200c, 32a-32c); and
a stack (S1-S18, “dielectric substrate 12” [0035]) for integrating the plurality of resonators, the stack including a plurality of dielectric layers (S1-S18) stacked together, wherein
each of the plurality of resonators includes a first through hole line (90a-90c), a second through hole line (38a-38c), and a conductor layer portion (30a-30c, 32a-32c) connecting the first through hole line and the second through hole line,
each of the first through hole line and the second through hole line is constituted by two or more through holes (S14-S18) being connected in series,
the second through hole line is provided between the conductor layer portion and ground (20) in a circuit configuration (Fig. 5),
the stack includes a first region (30a-30c) and a second region (32a-32c) in each of which at least one element is arranged, and
the first region and the second region are divided by a plurality of the second through hole lines. (Mizutani: Figs. 1, 2 and 5-7, machine translation, para. [0035], [0041], [0042], [0044], [0058], [0059]).
Mizutani does not explicitly teach, the first region and the second region are divided by a plurality of the second through hole lines.
However, Oran teaches (Fig. 4B), the first region (region for inductor 120a) and the second region (region for inductor 120b) are divided by a plurality of the second through hole lines (152) that are grounded (“the pillars 152 are grounded” col. 9, lines 37-39). (Oran: Figs. 4B, 7A, 7B and 8A, col. 9, lines 21-39).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the laminated shared device of Mizutani to include the first and second region being divided by a plurality of the second through hole lines that are connected to ground of Oran, the motivation being for “providing shielding between the first multi-turn inductor 120a and the second multi-turn inductor 120b”. (Oran: Figs. 4B, 7A, 7B and 8A, col. 9, lines 35-37). Therefore, the limitation of Claim 1 would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding Claim 2, the combination of Mizutani in view of Oran further teaches, wherein the plurality of resonators (30a-30c, 200a-200c, 202a-202c) are connected in parallel with each other. (Mizutani: Figs. 1, 2 and 5-7, machine translation, para. [0035], [0041], [0042], [0044], [0058], [0059]).
Regarding Claim 3 and similarly claim 4, the combination of Mizutani in view of Oran further teaches, further comprising: a first circuit portion (30a-30c, Fig. 7) including at least one first element (30a-30c) arranged in the first region; and a second circuit portion (32a-32c, Fig. 7) including at least one second element (32a-32c) arranged in the second region. (Mizutani: Figs. 1, 2 and 5-7, machine translation, para. [0035], [0041], [0042], [0044], [0058], [0059]).
Regarding Claim 5 and similarly claim 6, the combination of Mizutani in view of Oran further teaches, wherein the first region (region for inductor 120a) and the second region (region for inductor 120b) are arranged in a longitudinal direction of a planar shape of the stack when seen from a stacking direction of the plurality of dielectric layers, the motivation being that a longitudinal direction is provided for “providing shielding between the first multi-turn inductor 120a and the second multi-turn inductor 120b”. (Oran: Figs. 4B, 7A, 7B and 8A, col. 9, lines 35-37).
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamashita et al. (JP2005244711A),Hayashi (JP2004128799A) and Ashida et al. (US 20190007018).
Conclusion
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/MALCOLM BARNES/
Primary Examiner, Art Unit 2837
7/15/2026
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