axrDETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Madrid (US 20100148327 A1).
Regarding claim 1, Madrid teaches:
A locking system for facilitating the assembly of at least one a semiconductor device [100, paragraph [0028-0029], Fig. 1-5] the locking system comprising:
an assembly of a composite clip frame [63, paragraph [0051-0052], Fig. 7] and a lead frame [700, paragraph [0050], Fig. 6], wherein the lead frame [700, Fig. 6] comprises a first lead frame surface [700 (lower), Fig. 6] and a second lead frame surface [700 (upper), Fig. 6] opposite the first lead frame surface [700 (lower), Fig. 6] and a plurality of die attach paddles [22, paragraph [0050], Fig. 6, 12] arranged in a matrix form [Fig. 6, 10], wherein the composite clip frame [63, Fig. 7] comprises a plurality of die clip sets arranged in a matrix corresponding with the matrix of the plurality of die attach paddles [22, Fig. 6, 12], wherein each clip set comprises a locking clip [63, Fig. 7] and at least one clip for an associated semiconductor die [33, paragraph [0045], Fig. 5] to be mounted in a respective die attach paddle [22, Fig. 5], and wherein the locking clip [63, Fig. 7] comprises a first locking clip surface [63 (lower), Fig. 7] and a second locking clip surface [63 (upper), Fig. 7] opposite the first locking clip surface [63 (lower), Fig. 7];
wherein the locking clip [63, Fig. 7] comprises a first locking means [63(a), paragraph [0053], Fig. 7-10] and wherein the lead frame [700, Fig. 6] comprises a second locking means [69, paragraph [0050], [0053], Fig. 6, 8-10],
wherein the first locking means [63(a), Fig. 7-10] of the locking clip [63, Fig. 7] is structured to align with the second locking means [69, Fig. 8-10] of the lead frame [700, Fig. 6], so that a movement of the locking clip [63, Fig. 7-10] relative to the lead frame [700, Fig. 6-10] is possible in only one direction perpendicular to the plane formed by the lead frame [700, Fig. 6-10], and wherein the locking clip [63, Fig. 7-10] is placed on the lead frame [700, Fig. 6-10] so that the first locking clip surface [63 (lower), Fig. 7] of the locking clip [63, Fig. 7] is in contact with the second lead frame surface [700 (upper), Fig. 6-10] of the lead frame [700, Fig. 6];
wherein one of the first locking means [63(a), Fig. 7-10] or the second locking means [69, Fig. 8-10] is formed as at least one protrusion or pillar [69 “folding tabs”, Fig. 8-10], and the other one of the first locking means [63(a), Fig. 7-10] or the second locking means [69, Fig. 6-10] is formed as a corresponding slot or socket receiver [63(a), Fig. 7-10]; and
wherein the pillars [69 “folding tabs”, Fig. 6-10] are bended approximately 90° towards the corresponding socket receiver [63(a), Fig. 7-10], while the other clip ends [21/25, paragraph [0033-0034], Fig. 4] are bended towards the end of the semiconductor device [100, Fig. 1-5] after singulation.
Regarding claim 2, Madrid teaches:
The locking mechanism according to claim 1, wherein the slot [63(a), Fig. 6-10] is located on an outer edge of the locking clip [63, Fig. 8-10] or the lead frame [700, Fig. 6-10].
Regarding claim 3, Madrid teaches:
A semiconductor device [100, Fig. 1-5] comprising:
a locking system according to claim 1,
a semiconductor die [33, paragraph [0045], Fig. 3-5] comprising a first semiconductor die surface [33 (lower), Fig. 3-5] and a second semiconductor die surface [33 (upper), Fig. 3-5] opposite the first semiconductor die surface [33 (lower), Fig. 3-5, 8];
a mold compound [11, paragraph [0028-0030], Fig. 1-5, 11];
wherein the first semiconductor die surface [33 (lower), paragraph [0052], Fig. 3-5] of the semiconductor die [33, Fig. 3-5] is connected to the second lead frame surface [700 (upper), Fig. 8], and wherein the first clip surface [63 (lower), Fig. 8] of the at least one clip [63, Fig. 8] is connected to the second semiconductor die surface [33, (upper), Fig. 8] of the semiconductor die [33, Fig. 3-5, 8]; and
wherein the mold compound [11, paragraph [0028], Fig. 1-5, 11] encapsulates the semiconductor die [33, Fig. 5] so that the mold compound [11, Fig. 1-5, 11] forms an outer surface of the semiconductor device [100, Fig. 5] with the second locking clip surface [63 (upper), Fig. 8] of the locking clip [63, Fig. 8], the second clip surface [63 (upper), Fig. 8] of the at least one clip [63, Fig. 8], and the first lead frame surface [700 (lower), Fig. 8] of the lead frame [700, Fig. 8].
Regarding claim 4, Madrid teaches:
A semiconductor device [100, Fig. 1-5] comprising:
a locking system according to claim 2,
a semiconductor die [33, Fig. 3-5] comprising a first semiconductor die surface [33 (lower), Fig. 3-5] and a second semiconductor die surface [33 (upper), Fig. 3-5] opposite the first semiconductor die surface [33 (lower), Fig. 3-5];
a mold compound [11, Fig. 1-5, 11];
wherein the first semiconductor die surface [33 (lower), paragraph [0052], Fig. 3-5, 8] of the semiconductor die [33, Fig. 3-5] is connected to the second lead frame surface [700 (upper), Fig. 8], and wherein the first clip surface [63 (lower), Fig. 8] of the at least one clip [63, Fig. 8] is connected to the second semiconductor die surface [33 (upper), Fig. 8] of the semiconductor die [33, Fig. 3-5, 8]; and
wherein the mold compound [11, Fig. 1-5, 11] encapsulates the semiconductor die [33, Fig. 5] so that the mold compound [11, Fig. 1-5, 11] forms an outer surface of the semiconductor device [100, Fig. 1-5] with the second locking clip surface [63 (upper), Fig. 8] of the locking clip [63, Fig. 8], the second clip surface [63 (upper), Fig. 8] of the at least one clip [63, Fig. 8], and the first lead frame surface [700 (lower), Fig. 8] of the lead frame [700, Fig. 8].
Regarding claim 6, Madrid teaches:
A semiconductor device [100, Fig. 1-5] comprising:
a locking system according to claim 3,
a semiconductor die [33, Fig. 3-5, 8] comprising a first semiconductor die surface [33 (lower), Fig. 3-5] and a second semiconductor die surface [33 (upper), Fig. 3-5] opposite the first semiconductor die surface [33 (lower), Fig. 3-5];
a mold compound [11, Fig. 1-5, 11];
wherein the first semiconductor die surface [33 (lower), paragraph [0052], Fig. 3-5, 8] of the semiconductor die [33, Fig. 3-5, 8] is connected to the second lead frame surface [700 (upper), Fig. 8], and wherein the first clip surface [63(lower), Fig. 8] of the at least one clip [63, Fig. 8] is connected to the second semiconductor die surface [33 (upper), Fig. 3-5, 8] of the semiconductor die [33, Fig. 3-5, 8]; and
wherein the mold compound [11, paragraph [0028], Fig. 1-5, 11] encapsulates the semiconductor die [33, Fig. 3-5] so that the mold compound [11, Fig. 1-5, 11] forms an outer surface of the semiconductor device [100, Fig. 5] with the second locking clip surface [63 (upper), Fig. 8] of the locking clip [63, Fig. 8], the second clip surface [63 (upper), Fig. 8] of the at least one clip [63, Fig. 8], and the first lead frame surface [700(lower), Fig. 8] of the lead frame [700, Fig. 8].
Regarding claim 7, Madrid teaches:
The semiconductor device [100, Fig. 1-5, 8] according to claim 3, wherein either the first semiconductor die surface [33 (lower), Fig. 1-5] of the semiconductor die [33, Fig. 1-5] and the second lead frame surface [700 (upper), Fig. 8] and/or the at least one clip [63, Fig. 7-10] and the second semiconductor die surface [33 (upper), Fig. 8] of the semiconductor die [33, Fig. 8] are soldered [56/59, paragraph [0045], [0052], Fig. 5] to each other.
Regarding claim 8, Madrid teaches:
A method of manufacturing a semiconductor device [100, Fig. 1-5, 8] according to claim 3, comprising the steps of:
i) providing a composite lead frame [700, paragraph [0050], Fig. 6] comprising a first lead frame surface [700 (lower), Fig. 6] and a second lead frame surface [700 (upper), Fig. 6] opposite the first lead frame surface [700 (lower), Fig. 6], wherein the composite lead frame [700, Fig. 6] comprises a plurality of die attach paddles [22, paragraph [0050], Fig. 6] arranged in a matrix [Fig. 6, 10] and provided with one of a first locking means [63(a), Fig. 7-10] or a second locking means [69, Fig. 6-10];
ii) mounting, in each die attach paddle [22, paragraph [0045], Fig. 5-6, 8], a semiconductor die [33, Fig. 3-5, 8] comprising a first semiconductor die surface [33 (lower), Fig. 3-5, 8] and a second semiconductor die surface [33 (upper), Fig. 3-5, 8] opposite the first semiconductor die surface [33 (lower), Fig. 3-5, 8], so that the first semiconductor die surface [33 (lower), Fig. 3-5, 8] of the semiconductor die [33, Fig. 3-5, 8] is connected to the second lead frame surface [700 (upper), Fig. 8];
iii) providing a composite clip frame [63, Fig. 7] comprises a plurality of die clip sets arranged in a matrix corresponding with the matrix of the plurality of die attach paddles [22, Fig. 5-6, 8] and provided with the other of the first locking means [63(a), Fig. 7-10] or the second locking means [69, Fig. 6-10];
iv) mounting the composite clip frame [63, Fig. 8] on the composite lead frame [700, Fig. 8] and the matrix of semiconductor dies [33, Fig. 8], so that the first locking means [63(a), paragraph [0053], Fig. 7-10] engage with the second locking means [69, Fig. 6-10] and that movement is only possible in only one direction, wherein each die clip set comprises a locking clip [63, Fig. 7-10] and at least one clip [63, Fig. 7-10], wherein upon mounting the at least one clip [63, paragraph [0052], Fig. 7-10] is connected to the second semiconductor die surface [33 (upper), Fig. 8] of the semiconductor die [33, Fig. 8], and wherein the locking clip [63, Fig. 7-10] comprises the first locking means [63(a), Fig. 7-10] or second locking means [69, Fig. 6-10] and engages the second lead frame surface [700 (upper), Fig. 8] of the lead frame [700, Fig. 6-10];
v) encapsulating the composite lead frame [700, Fig. 6-11] and the matrix of the plurality of semiconductor dies [33, Fig. 5, 8-11] and the composite clip frame [63, Fig. 7-11] with a mold compound [11, paragraph [0056], Fig. 11];
vi) singulating a semiconductor device [100, paragraph [0058], Fig. 10-11] from the encapsulated matrix of semiconductor dies [33, Fig. 8-11]; and
vii) removing the frame of the clip frame [(during singulation)]
Regarding claim 9, Madrid teaches:
A method of manufacturing a semiconductor device [100, Fig. 1-5, 8] according to claim 7, comprising the steps of:
i) providing a composite lead frame [700, paragraph [0050], Fig. 6] comprising a first lead frame surface [700 (lower), Fig. 6] and a second lead frame surface [700 (upper), Fig. 6] opposite the first lead frame surface [700 (lower), Fig. 6], wherein the composite lead frame [700, Fig. 6] comprises a plurality of die attach paddles [22, Fig. 6] arranged in a matrix and provided with one of a first locking means [63(a), Fig. 7-10] or a second locking means [69, Fig. 6-10];
ii) mounting, in each die attach paddle [22, paragraph [0045], Fig. 6], a semiconductor die [33, Fig. 3-5, 8] comprising a first semiconductor die surface [33 (lower), Fig. 3-5, 8] and a second semiconductor die surface [33 (upper), Fig. 3-5, 8] opposite the first semiconductor die surface [33 (lower), Fig. 3-5, 8], so that the first semiconductor die surface [33 (lower), Fig. 3-5, 8] of the semiconductor die [33, Fig. 3-5, 8] is connected to the second lead frame surface [700 (upper), Fig. 6-10];
iii) providing a composite clip frame [63, Fig. 7] composed of a plurality of die clip sets arranged in a matrix corresponding with the matrix of the plurality of die attach paddles [22, Fig. 5-6, 8] and provided with the other of the first locking means [63(a), Fig. 7-10] or the second locking means [69, Fig. 6-10];
iv) mounting the composite clip frame [63, Fig. 8] on the composite lead frame [700, Fig. 8] and the matrix of semiconductor dies [33, Fig. 8], so that the first locking means [63(a), paragraph [0053], Fig. 7-10] engage with the second locking means [69, Fig. 6-10] and that movement is only possible in only one direction, wherein each die clip set comprises a locking clip [63, Fig. 7-10] and at least one clip [63, Fig. 7-10], wherein, upon mounting, the at least one clip [63, Fig. 7-10] is connected to the second semiconductor die surface [33 (upper), Fig. 8] of the semiconductor die [33, Fig. 3-5, 8], and wherein the locking clip [63, Fig. 7-10] comprises the first locking means [63(a), Fig.7-10] or second locking means [69, Fig. 6-10] and engages the second lead frame surface [700 (upper), Fig. 8] of the lead frame [700, Fig. 6-10];
v) encapsulating the composite lead frame [700, Fig. 6-11] and the matrix of the plurality of semiconductor dies [33, Fig. 5, 8-11] and the composite clip frame [63, Fig. 7-11] with a mold compound [11, paragraph [0056], Fig. 11;
vi) singulating a semiconductor device [100, paragraph [0058], Fig. 10-11] from the encapsulated matrix of semiconductor dies [33, Fig. 8-11]; and
vii) removing the frame of the clip frame [(during singulation)]
Regarding claim 10, Madrid teaches:
The method according to claim 9, wherein the encapsulating step v) is followed by
v-1) a polishing step so that the locking clip [12, paragraph [0029], [0044], Fig. 1-5, 11] and the at least one clip [27, paragraph [0033], Fig. 2, 4] are exposed forming an outer surface of the semiconductor device [100, Fig. 1-5, 10-11], and the mold compound [11, Fig. 1-5, 10-11] and the exposed locking clip [12, Fig. 1-5, 11] and the at least one exposed clip [27, Fig. 2, 4] form a single planar surface.
Regarding claim 11, Madrid teaches:
The method according to claim 9, wherein the connecting steps ii) and iv) further comprise the sub-steps of:
viii-1) applying a solder paste [59/56, paragraph [0045], [0052], Fig. 5] between the first semiconductor die surface [33 (lower), Fig. 3-5, 8] of the semiconductor die [33, Fig. 3-5, 8] and the second lead frame surface [700 (upper), Fig. 5] and/or the at least one clip [63, Fig. 7-10] and the second semiconductor die surface [33 (upper), Fig. 5] of the semiconductor die [33, Fig. 5], and
viii-2) performing soldering.
Regarding claim 12, Madrid teaches:
The method according to claim 10, wherein the connecting steps ii) and iv) further comprise the sub-steps of:
viii-1) applying a solder paste [59, paragraph [0045], [0052], Fig. 5] between the first semiconductor die surface [33 (lower), Fig. 5, 8] of the semiconductor die [33, Fig. 5, 8] and the second lead frame surface [700 (upper), Fig. 6-10] and/or the at least one clip [63, Fig. 7-10] and the second semiconductor die surface [33 (upper), Fig. 5] of the semiconductor die [33, Fig. 5], and
viii-2) performing soldering.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Madrid (US 20100148327 A1) as applied to claim 2 above, and further in view of Xiaochun et al. (US 20060214290 A1).
Regarding claim 5, Madrid teaches the locking mechanism according to claim 2.
Madrid does not teach:
wherein the socket receiver is formed as a groove.
Xiaochun et al. teaches:
wherein the socket receiver [112, paragraph [0024], [0026], Fig. 1-6] is formed as a groove.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Xiaochun et al. into the teachings of Madrid to include wherein the socket receiver is formed as a groove. The ordinary artisan would have been motivated to modify Madrid in the above manner for the purpose of restricting the motion of the clip, and improving connections.
Conclusion
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/D.M.H./Examiner, Art Unit 2815 1/8/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815