DETAILED ACTION
The Examiner acknowledges the applicant's submission of the response dated 1/30/2026.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement, dated 1/30/2026, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
DOUBLE PATENTING
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1, 2, and 12 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over US 11,868,661. Although the conflicting claims are not identical, they are not patentably distinct from each other.
Instant Application
US 11,868,661
1. A device, comprising:
rows of memory cells, wherein a row of the rows of memory cells has a row address;
a counter configured to count activation commands applied to sub-addresses in the row address of the row;
a logic circuit configured to generate, using the counter, an alert about row hammering attack.
2. The device of claim 1, wherein each activation command applied to the row address is to cause an increase in more than one counter among a plurality of counters.
12. A system, comprising: rows of memory cells addressable via row addresses; counters corresponding to sub-addresses in row address segments,
wherein each respective counter in the counters is configured to count activation commands applied to row addresses having a sub-address corresponding to the respective counter, wherein the sub-address refers to only a subset of a given row of the rows; and
a processing device configured to perform risk mitigation operations based on values in the counters.
1. A method, comprising:
counting, for sub-addresses in a plurality of row address segments using counters corresponding to the sub-addresses respectively, activation commands applied to row addresses containing the sub-addresses in accessing rows of memory cells in a memory device; increasing, in response to an activation command applied to a row address having first sub-addresses in the plurality of row address segments respectively, counts stored in a portion of the counters corresponding to the first sub-addresses; determining, for each respective segment in the plurality of row address segments, whether at least one first sub-address in the respective segment have been applied a count of activation commands that is more than a threshold according to a counter corresponding to the first sub-address among the counters; determining whether each of the plurality of row address segments has at least one sub-address having been applied more activation commands than the threshold; and generating an alert in response to a determination that each of the plurality of row address segments has at least one sub-address having been applied more activation commands than the threshold.
[From Claim 1]
increasing, in response to an activation command applied to a row address having first sub-addresses in the plurality of row address segments respectively, counts stored in a portion of the counters corresponding to the first sub-addresses;
11. A memory device, comprising: rows of memory cells addressable via row addresses, each having a plurality of segments; counters corresponding to sub-addresses in the plurality of segments, wherein the counters are configured to count activation commands applied to row addresses having the sub-addresses corresponding to the counters; a logic circuit configured to: determine, for each respective segment in the plurality of segments, whether at least one first sub-address in the respective segment have been applied a count of activation commands that is more than a threshold according to a counter corresponding to the first sub-address among the counters; determine whether each of the plurality of row address segments has at least one sub-address having been applied more activation commands than the threshold; and generate an alert in response to a determination that each of the plurality of row address segments has at least one sub-address having been applied more activation commands than the threshold.
It would have been obvious to modify the claims of US 11,868,861 for the benefit of obtaining the invention as specified in claim 1, 2, and 12 of the instant application, as all limitations of claims 1, 2, and 12 are present in the claims of US 11,868,861.
Claims 3 contains the limitation of “wherein the counters include a subset of first counters; and sub-addresses pre-associated with the first counters correspond to a first row address,” which is not found in nor rendered obvious by the claims of US 11,868,861. Therefore, no double patenting rejection has been made for claim 3 or its dependent claims. Claim 15 contains a similar limitation.
Claim 13 contains the limitation of “determine, for each respective segment in a plurality of segments, whether at least one first sub-address in the respective segment have been applied a count of activation commands that is more than a threshold according to a counter corresponding to the first sub-address among the counters; determine whether each of the plurality of row address segments has at least one sub-address having been applied more activation commands than the threshold; and generate an alert in response to a determination that each of the plurality of row address segments has at least one sub-address having been applied more activation commands than the threshold which is not found in nor rendered obvious by the claims of US 11,868,861. Therefore, no double patenting rejection has been made for claim 13 or dependent claim 14.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 15 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ayyapureddi et al (US 2021/0020223).
Regarding Claim 15, the cited prior art teaches a method, comprising: counting, using a plurality of counters that are pre-associated with sub-addresses of row addresses of memory cells, activation commands applied to sub-addresses (sub-addresses corresponding to “a particular value of a subset of the row address XADD,” Paragraph 0055, and each of these sub-addresses may have “a counter value,” Paragraphs 0036-0037, and the counters are shown as C_Portion0, C_SubPortion0 etc, of Fig. 2, Paragraphs 0040-0043, and the counters are increased when a word line/row is accessed/activated at step 602 of Fig. 6, Paragraph 0079), wherein the sub-addresses refer to a subset of a given row associated with the row addresses (the sub-address refer to a given subset of bits of any given row, Paragraph 0056); and generating, based on values in the counters, an alert about row hammering attack (step 610 of Fig. 6, the alert corresponding to addresses that may be subject to a row hammering attack, Paragraph 0080).
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ayyapureddi et al in view of Devaux et al (US 2021/0398584).
Regarding Claim 16, the cited prior art teaches the method of claim 15, but does not explicitly teach wherein each activation command applied to a row address is to cause an increase in more than one counter among the counters.
Devaux teaches wherein each activation command applied to a row address is to cause an increase in more than one counter among the counters (“each activation of a row of a given sub-bank of the memory device, the step of incrementing the activation counter associated with the given sub-bank also increments the activations counters of all other sub-banks having at least a row likely to be hammered by the activation,” Paragraph 0038).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the increase in more than one counter (as in Devaux) in the cited prior art in order to track which rows may be subject to hammering.
Regarding Claim 17, the cited prior art teaches the method of claim 16, further comprising: performing, in response to the alert, a risk mitigation operation (the risk mitigation corresponding to a “refresh” operation, Paragraphs 0011-0012).
Regarding Claim 18, the cited prior art teaches the method of claim 17, wherein the risk mitigation operation includes: starting a memory refresh operation (“refresh” operation, Paragraphs 0011-0012); adjusting a frequency of memory refresh operations; throttling memory access towards row addresses related to sub-addresses having been applied excessive activation commands; reloading data; or starting multiple redundant threads of computation based on redundant copies of data in the memory cells; or any combination thereof.
Regarding Claim 19, the cited prior art teaches the method of claim 18, wherein sub-addresses pre-associated with the counters are configured to have a same number of bits (sub-addresses corresponding to “a particular value of a subset of the row address XADD,” which has a same number of bits, Paragraph 0055).
Regarding Claim 20, the cited prior art teaches the method of claim 19, further comprising: resetting the counters periodically in absence of an alert, or in response to a refresh command (at step 610 of Fig. 6, a refresh is started, and the counters are reset, Paragraph 0081).
ARGUMENTS CONCERNING NON-PRIOR ART REJECTIONS/OBJECTIONS
Double Patenting
On page 1 of the submitted remarks, applicant argues claim 1 of the cited prior art is not obvious in view of the claims of US 11,868,661 because claim 1 of the instant application recites "a counter configured to count activation commands applied to sub-addresses in the row address of the row" while device claim 11 of the '661 patent recites multiple counters configured to count activation commands applied to row addresses having the sub-addresses corresponding to the counters.
This argument has been considered but is not persuasive.
The “multiple counters configured to count activation commands applied to row addresses having the sub-addresses corresponding to the counters” of claim 11 of the ‘661 patent requires there to be at least one “counter configured to count activation commands applied to sub-addresses in the row address of the row” as recited in claim 1 of the instant application.
Applicant further argues claim 1 of the cited prior art is not obvious in view of the claims of US 11,868,661 because claim 1 of the instant application recites "a logic circuit configured to generate, using the counter, an alert about a row hammering attack" while device claim 11 of the '661 patent recites a "logic circuit configured to generate an alert in response to a determination that each of the plurality of row address segments has at least one sub-address having been applied more activation commands than the threshold."
This argument has been considered but is not persuasive.
Both sets of claims teach using a counter to generate an alert. Though the ‘661 claims do not specify the alert is about a row hammering attack, it would be obvious to a person having ordinary skill in the art that the alert is about a row hammering attack, as the alert is generated due to an activation count for a row of memory.
For the above reasons, the double patenting rejections have been maintained.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
On pages 1-2 of the submitted remarks, applicant argues claim 15 is allowable over the prior art of record because Claim 15 recites at least some similar subject matter as allowable claim 1.
This argument has been considered but is not persuasive.
Though some elements of claim 15 may be similar to claim 1, the examiner maintains the scope of claim 15 is different than that of claim 1. For example, claim 15 does not require a single counter to count activation commands applied to (multiple) sub-addresses in the row address of the row. Therefore, the prior art rejection of claim 15 has been maintained.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Nale et al (US 2022/0121398) teaches PERFECT ROW HAMMER TRACKING WITH MULTIPLE COUNT INCREMENTS.
CLOSING COMMENTS
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
SUBJECT MATTER CONSIDERED ALLOWABLE
Claims 1-14 contain allowable subject matter as noted in the Non-Final Rejection mailed 10/29/2025, Pages 9-10. The examiner notes a double patenting rejection has been made for claims 1, 2, and 12 as noted above.
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1,2 ,12, and 15-20 have been rejected in the application.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:00- 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135