DETAILED ACTION
This action is in response to the Request to Continued Examination (RCE) 04/24/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 04/24/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 22 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Pub. No. 2016/0268900; (hereinafter Miyazaki)
Regarding claim 1, Miyazaki [e.g. Figs. 3 and 5; Fig. 3 corresponds to the dead time producing circuit 12 of Fig. 5] discloses a power converter, comprising: a first transistor [e.g. Fig. 5; 21] having a control input [e.g. gate] and first and second terminals [e.g. upper and lower terminals, respectively]; a second transistor [e.g. Fig. 5; 31] having a control input [e.g. gate] and first and second terminals [e.g. upper and lower terminals, respectively], the first terminal of the second transistor coupled to the second terminal of the first transistor at a switch terminal [e.g. VLX (4)]; a third transistor [e.g. Fig. 5; 22] having a control input [e.g. gate] and first and second terminals [e.g. upper and lower terminals, respectively], the second terminal of the third transistor coupled to the switch terminal [e.g. VLX as shown]; a logic circuit [e.g. Fig. 3; 126-128 and 130-132] having a first input [e.g. at lower input of 130], first output [e.g. PP2], and a second output [e.g. PN1], the first input of the logic circuit coupled to the switch terminal [e.g. Fig. 3; via DLY2b (134) and Dead Time Control Circuit 40, see Fig. 5 and paragraph 042], the first output coupled to the control input of the third transistor [e.g. Fig. 5; gate of 22], and the second output coupled to the control input of the second transistor [e.g. Fig. 5; gate of 31]; and a delay circuit [e.g. Fig. 3; DLY1a(123), DLY1b (124) and DLY2a (133)] having a first input [e.g. Fig. 5; input from dead time control circuit 40; paragraph 042], and a first output [e.g. PP1], the first input of the delay circuit coupled to the switch terminal [e.g. Fig. 5; VLX (4) via dead time control circuit 40], the first output of the delay circuit [e.g. PP1] coupled to the control input of the first transistor [e.g. Fig. 5; 21].
Regarding claim 22, Miyazaki [e.g. Fig. 5] discloses wherein the first terminal of the first transistor is coupled to a voltage input terminal [e.g. Vin].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claims 21 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki in view of US Pub. No. 2017/0237332; (hereinafter Takahashi)
Regarding claim 21, Miyazaki [e.g. Fig. 5] discloses further comprising: a first inductor [e.g. 6] having a first terminal and a second terminal, the first terminal of the first inductor coupled to the switch terminal [e.g. left terminal connected to VLX].
Miyazaki fails to disclose a second inductor having a first terminal and a second terminal, the first terminal of the second inductor coupled to the first terminal of the third transistor, and the second terminal of the second inductor coupled to the second terminal of the first inductor.
Takahashi [e.g. Fig. 1] teaches a second inductor [e.g. L2] having a first terminal [e.g. left side terminal] and a second terminal [e.g. right side terminal], the first terminal of the second inductor coupled to the first terminal [e.g. upper terminal] of the third transistor [e.g. S3], and the second terminal of the second inductor coupled to the second terminal of the first inductor [e.g. via Ds].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Miyazaki by a second inductor having a first terminal and a second terminal, the first terminal of the second inductor coupled to the first terminal of the third transistor, and the second terminal of the second inductor coupled to the second terminal of the first inductor as taught by Takahashi in order of being able to reduce switching losses by enabling zero voltage switching by providing a resonant circuit.
Regarding claim 27, Miyazaki fails to disclose wherein the first, second, and third transistors are n- channel field effect transistors (NFETs).
Takahashi [e.g. Fig. 1] teaches wherein the first [e.g. S1], second [e.g. S2], and third [e.g. S3] transistors are n-channel field effect transistors (NFETs) [e.g. see transistor symbol with the source terminal arrow pointing IN; paragraphs 065 and 077].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Miyazaki by wherein the first, second, and third transistors are n- channel field effect transistors (NFETs) as taught by Takahashi in order of being able to reduce switching losses.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 2 – 9 and 23 – 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 2 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the delay circuit has a second input and a second output and comprises: a counter having a control input and a counter output; and a delay element having a signal input, a delay control input, and a delay output, the signal input coupled to the second input, the delay control input coupled to the counter output, and the delay output coupled to the second output of the delay circuit”.
The primary reason for the indication of the allowability of claim 23 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the logic circuit and the delay circuit are configurable to: turn on the second transistor; turn on the third transistor for a configurable delay period while the second transistor is in an on state; turn off the second transistor upon expiration of the configurable delay period; and after the second transistor is turned off, turn on the first transistor and update the configurable delay period based on a comparison of a voltage proportional to a voltage at the switch terminal to a voltage proportional to a voltage at the voltage input terminal”.
Claims 3 – 9 and 24 – 26 are objected to because inherent dependency on claims 2 and 23, respectively.
Conclusion
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/ALEX TORRES-RIVERA/ Primary Examiner, Art Unit 2838
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