DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 06/08/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 06/08/2026 in reply to the non-final rejection mailed on 03/09/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 7, 8, 9, 10, 12-14, & 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20210111090) in view of Yeh (US 20230402402) and further in view of Yu (US 20210327866).
Regarding Claim 1, Tsai (see, e.g., fig. 7, para.0039-0041) shows a substrate package, comprising:
a substrate 100 (see, e.g., para.0058);
a package device 101 (comprising 101a &101b, see, e.g., para.0061) mounted on the substrate,
wherein the package device 101 comprises a function die 101a,
wherein the function die 101a has an active front side (bottommost surface) facing downwardly to the substrate,
and an exposed, passive rear side 101as opposite to the active front side,
wherein the package device further comprises an encapsulant 102 (see, e.g., para.0053) covering peripheral sidewalls of the function die 101a (see, e.g., fig. 7);
an underfill material UF (see, e.g., para.0058) filling into a space between the package device 101 and the substrate 100 (space vertically between 101 & 100);
a stiffener ring 260 (see, e.g., para.0057) disposed on a top surface of the substrate 100 along perimeter of the substrate 100 (ring-shaped, similar to fig. 1 top view);
and a gap fill material 200 (see, e.g., para.0058) disposed in a gap (gap is defined by the space 200 takes up, see, e.g., annotated figure 1) between the stiffener ring 260 and the package device 101
wherein the gap fill material 200 is in direct contact with a sidewall of the encapsulant 102 (see, e.g., fig. 7) and a sidewall of the stiffener ring 260 (“it is understood that the ring-shaped stiffener 260 may be in direct contact with the multi-layer laminate epoxy sheet 200” see, e.g., annotated figure 1, para.0051).
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Tsai, however, fails to show
the substrate package is a coreless substrate package
the substrate 100 is a coreless substrate
the function die 101a is a function silicon die
Yeh (see, e.g., fig. 9c, para.0029-0030), in a similar device to Tsai, teaches a coreless substrate would provide proper structural and electrical support for package device 50 and function dies 50a & 50b.
It would have been obvious at the time of filing the invention to use the coreless substrate of Yeh in the device of Tsai to provide proper structural and electrical support for package device and the function die.
Tsai, in view of Yeh, however, fails to show
the function die 101a is a function silicon die
Yu (see, e.g., fig. 1a, para.0021), in a similar device to Tsai, in view of Yeh, teaches a function silicon die 200 comprising silicon as a substrate 202 would provide a proper semiconductor structure for die function and integration in a semiconductor package.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the die comprising silicon as a substrate of Yu in the device of Tsai, in view of Yeh, to provide a proper semiconductor structure for die function and integration in a semiconductor package.
Regarding Claim 3, in view of Yeh and further in view of Yu, shows the coreless substrate package according to claim 1,
Tsai, in view of Yu, however, fails to show
wherein a distance between an inner sidewall surface of the stiffener ring and a sidewall surface of the package device is not less than 10 mm.
However, ranges of distance will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Yeh (see, e.g., figs. 4a-b, para.0022) shows a distance D4 between an inner sidewall surface of the stiffener ring 58 and a sidewall surface of the package device 50a can be between 1.5 mm and 20 mm, overlapping the claimed range, see MPEP 2144.05 (I). Since the applicant has not established the criticality (see next paragraph below) of the claimed range, and similar ranges have been used in the art, it would have been obvious to one of ordinary skill in the art to use the ranges of distances shown in Yeh in the device of Tsai, in view of Yeh and further in view of Yu.
Criticality
The specification contains no disclosure of either the critical nature of the claimed temperature and pressure ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 4, Tsai, in view of Yeh (see, e.g., fig. 9a & 9c, para.0029-0030) and further in view of Yu, shows the coreless substrate package according to claim 1,
wherein the coreless substrate 100 (100 of Tsai modified to include the configuration of 72 shown in Yeh) comprises at least one insulating layer (74, 78, 82, & 86, see, e.g., para.0030) and conductive layers (metal lines & vias 76, 80, & 84, see, e.g., para.0030) in the at least one insulating layer (see, e.g., fig. 9a).
Regarding Claim 7, Tsai, in view of Yeh (see, e.g., fig. 9a & 9c, para.0031-0032) and further in view of Yu, shows the coreless substrate package according to claim 4,
wherein the conductive layers comprise connection pads 88 (see, e.g., fig. 9a, para.0031) exposed from the top surface of the coreless substrate and ball grid array (BGA) ball pads 96 (see, e.g., fig. 9a, para.0032) disposed at a bottom surface of the coreless substrate (see, e.g., annotated figure 2).
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Regarding Claim 8 Tsai (see, e.g., fig. 7, para.0047-0048), in view of Yeh and further in view of Yu, shows the coreless substrate package according to claim 7,
wherein the package device 101 is mounted on the top surface of the coreless substrate in a flip-chip fashion and is electrically connected to the connection pads 88 through a plurality of C4 bumps BC (see, e.g., annotated figure 2, para.0047-0048).
Regarding Claim 9, Tsai, in view of Yeh (see, e.g., para.0032-0033) and further in view of Yu, shows the coreless substrate package according to claim 7,
wherein BGA balls 94 (also present as BS of Tsai, see, e.g., para.0032-0033) are disposed on the BGA ball pads 96, respectively (see, e.g., annotated figure 2).
Regarding Claim 10, Tsai, in view of Yeh (see, e.g., para.0029-0030) and further in view of Yu, shows the coreless substrate package according to claim 1,
wherein the coreless substrate 100 does not include a permanent core structure (coreless substrate does not have a permanent core structure, see, e.g., para.0029-0030).
Regarding Claim 12, Tsai (see, e.g., para.0048-0049), in view of Yeh (see, e.g., para.0033) and further in view of Yu, shows the coreless substrate package according to claim 1,
wherein the gap fill material 200 comprises a molding compound (epoxy is a molding compound, see, e.g., para.0048-0049).
Regarding Claim 13, Tsai (see, e.g., para.0058), in view of Yeh and further in view of Yu, shows the coreless substrate package according to claim 1,
wherein the gap fill material 200 and the underfill material UF have different compositions (see, e.g., para.0058).
Regarding Claim 14, Tsai (see, e.g., fig. 7, para.0047, para.0054), in view of Yeh and further in view of Yu, shows the coreless substrate package according to claim 1,
wherein the gap fill material 200 and the encapsulant 102 have different compositions (see, e.g., para.0047, para.0054).
Regarding Claim 16, Tsai (see, e.g., para.0047), in view of Yeh and further in view of Yu, shows the coreless substrate package according to claim 1,
wherein the package device 10 comprises a Chip-on-Wafer package or a fan-out package (see, e.g., para.0047).
Regarding Claim 17, Tsai (see, e.g., para.0047), in view of Yeh and further in view of Yu, shows the coreless substrate package according to claim 1,
wherein the function silicon die 10 comprises a System on Chip (SoC) die, an RF die, or an application processor (AP) die (see, e.g., para.0047).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20210111090) in view of Yeh (US 20230402402) & Yu (US 20210327866) and further in view of Sain (US 20210296241).
Regarding Claim 2, Tsai, in view of Yeh &Yu, shows the coreless substrate package according to claim 1,
Tsai, in view of Yeh &Yu, however, fails to show
wherein the coreless substrate has a dimension of greater than 45mm × 45mm.
However, ranges of substrate dimension will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Sain (see, e.g., fig. 1, para.0024), in a similar device to Tsai, in view of Yeh &Yu, shows a coreless substrate with dimension of 60mm × 60mm. Since the applicant has not established the criticality (see next paragraph below) of the claimed range, and similar ranges have been used in the art, it would have been obvious to one of ordinary skill in the art to use the ranges of the coreless substrate of Sain in the device of Tsai, in view of Yeh &Yu. See paragraph 16 for criticality statement.
Claims 5 & 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20210111090) in view of Yeh (US 20230402402) & Yu (US 20210327866) and further in view of Natan (US 20240175772).
Regarding Claim 5, Tsai, in view of Yeh & Yu, show the coreless substrate package according to claim 4,
Tsai, in view of Yeh & Yu, however, fails to show
wherein the at least one insulating layer comprises Ajinomoto Build-up Film (ABF), polyimide, or prepreg.
Natan (see, e.g., fig. 2a, para.0051-0052), in a similar device to Tsai, in view of Yeh & Yu, teaches that Ajinomoto Build-up Film (ABF), polyimide, or prepreg can be the insulating layers of a coreless substrate and would provide proper insulation for the substrate and support for the conductive layers of the substrate.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the Ajinomoto Build-up Film (ABF), polyimide, or prepreg of Natan in the device of Tsai, in view of Yeh & Yu, to provide proper insulation for the substrate and support for the conductive layers of the substrate.
Regarding Claim 6, Tsai, in view of Yeh & Yu, shows the coreless substrate package according to claim 4,
Tsai, in view of Yeh & Yu, however, fails to show
wherein the conductive layers comprise copper.
Natan (see, e.g., fig. 2a, para.0051), in a similar device to Tsai, in view of Yeh & Yu, teaches that copper can be the material for the conductive layers of a coreless substrate and would allow for electrical connections through and extending from the coreless substrate.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the copper of Natan in the device of Tsai, in view of Yeh & Yu, to allow for electrical connections through and extending from the coreless substrate.
Claims 11 & 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20210111090) in view of Yeh (US 20230402402) & Yu (US 20210327866) and further in view of Chang (EP 3671831).
Regarding Claim 11, Tsai (see, e.g., fig. 7, para.0051), in view of Yeh and further in view of Yu, shows the coreless substrate package according to claim 1,
wherein the stiffener ring 260 is affixed onto the top surface of the coreless substrate 100 by using an adhesive layer 262 (see, e.g., para.0051).
Tsai, in view of Yeh & Yu, however, fails to show
wherein the stiffener ring is coplanar with the package device
Chang (see, e.g., fig. 6, para.0060), in a similar device to Tsai, in view of Yeh & Yu, teaches a configuration
wherein the stiffener ring 113 is coplanar with the package device 115a-b (top surfaces are coplanar)
Chang states the configuration would provide better adhesion, insulation, and warpage control of the gap filling material and encapsulant between the stiffener ring and package device which would also allow for additional thermal dissipating elements to be provided.
The configuration of Chang is incorporated into the device of Tsai, in view of Yeh & Yu.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Chang in the device of Tsai, in view of Yeh & Yu, to provide better adhesion, insulation, and warpage control of the gap filling material and encapsulant between the stiffener ring and package device which would also allow for additional thermal dissipating elements to be provided
Regarding Claim 15, Tsai (see, e.g., para.0050), in view of Yeh & Yu, shows the coreless substrate package according to claim 1,
wherein the gap fill material 200 has a top surface that is flush with a top surface of the encapsulant 102, and the passive rear side 101as of the function silicon die 101a (see, e.g., para.0050).
Tsai, in view of Yeh & Yu, however, fails to show
wherein the gap fill material has a top surface that is flush with a top surface of the stiffener ring
Chang (see, e.g., fig. 6, para.0060), in a similar device to Tsai, in view of Yeh & Yu, teaches a configuration
wherein the gap fill material 150 has a top surface that is flush with a top surface of the stiffener ring 113, a top surface of the encapsulant 117, and the passive rear side (top surface) of a die 115a
Chang states the configuration would provide better adhesion, insulation, and warpage control of the overall device and allow for additional thermal dissipating elements to be provided.
The configuration of Chang is incorporated into the device of Tsai, in view of Yeh & Yu.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Chang in the device of Tsai, in view of Yeh & Yu, to provide better adhesion, insulation, and warpage control of the overall device and allow for additional thermal dissipating elements to be provided.
Response to Arguments
The amended limitation “wherein the gap fill material is in direct contact with a sidewall of the encapsulant and a sidewall of the stiffener ring” does not overcome the prior art of record. Tsai (US 20230005808) states in para.0051 “However, it is understood that the ring-shaped stiffener 260 may be in direct contact with the multi-layer laminate epoxy sheet 200 in some embodiments.” Therefore Tsai teaches the amended limitation as the gap fill material 200 is in direct contact with a sidewall of the encapsulant 103 and a sidewall of the stiffener ring 260. The prior art of record of this Office action includes an earlier reference of Tsai (US 20210111090) which also anticipates the limitation, see annotated figure 1 and paragraphs 4-5 above.
Response to Arguments
Applicant’s arguments, see page 7, filed 06/08/2026, with respect to the objection of claim 1 have been fully considered and are persuasive. The objection of claim 1 has been withdrawn.
Applicant's arguments filed 06/08/2026, with respect to the prior art rejections of claims 1-17 have been fully considered but they are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
