DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06 November 2023 and 20 March 2025 were filed prior to the mailing date of this office correspondence. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of Invention I, claims 1-19 in the reply filed on 19 August 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim.
Claim Objections
Claim 1 is objected to because of the following informalities:
In claim 1, line 13: “a second seed layer” should read: -- the second seed layer --
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishioka (US 20170303394).
Regarding claim 1, Nishioka teaches, a printed wiring board, comprising:
a conductor layer including a pad (first conductor layer 12, pad 26P, see annotated Fig. 5C below, para. [0035-0036]);
a first resin insulating layer (first insulating layer 21, interlayer insulating layers can each be formed of an insulating resin composition, para. [0042]) laminated on the conductor layer (12);
a first conductor layer (second conductor layer 23, Fig. 5C) formed on the first resin insulating layer and comprising a first seed layer (second seed layer23a, the second conductor layer 23…includes a second seed layer 23a and a second electrolytic plating layer 23b, para. [0043]) and a first electrolytic plating layer (second electrolytic plating layer 23b) formed on the first seed layer;
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Annotated Fig. 5C, Nishioka.
a second resin insulating layer (second insulating layer 24) laminated on the first resin insulating layer such that the second resin insulating layer is covering the first conductor layer (23, see Fig. 5C); and
a second conductor layer (third conductor 26) formed on the second resin insulating layer and comprising a second seed layer (third seed layer 26a, third conductor layer 26 can be formed of a third seed layer 26a and a third electrolytic plating layer 26b, para. [0043]) and a second electrolytic plating layer (third electrolytic plating layer 26b) formed on the second seed layer,
wherein the first conductor layer is formed such that the first seed layer is an electroless plating layer (seed layers are each a base layer for forming an electrolytic plating layer on a surface of each of the interlayer insulating layers 21, 24, are an electroless plating layer, para. [0043]) and the first electrolytic plating layer formed on the first seed layer (para. [0043]), and the second conductor layer is formed such that a second seed layer is a sputtering layer (seed layers are each a base layer for forming an electrolytic plating layer on a surface of each of the interlayer insulating layers 21, 24, are…a metal layer formed by sputtering, para. [0043]) and the second electrolytic plating layer formed on the second seed layer (para. [0043]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 alternatively, and claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 20180166372) in view of Nishioka.
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Annotated Fig. 23, Shimizu.
Regarding claim 1, Shimizu teaches, a printed wiring board, comprising:
a conductor layer including a pad (wiring layer 50, pad P1, see annotate Fig. 23);
a first resin insulating layer (insulating layer 61, Fig. 23, photosensitive insulative resin,…a polyimide-based resin,…as the material of the insulating layers 61, para. [0045]) laminated on the conductor layer (Fig. 23);
a first conductor layer (wiring layer 70) formed on the first resin insulating layer and comprising a first seed layer (seed layer 71, wiring layer 70 includes a seed layer 71 and a metal layer 74, para. [0059]) and a first electrolytic plating layer (metal layer 74, Fig. 23, the metal layer 74 (electrolytic copper plating layer), para. [0111]) formed on the first seed layer;
a second resin insulating layer (insulating layer 63, Fig. 23) laminated on the first resin insulating layer such that the second resin insulating layer is covering the first conductor layer (see Fig. 23); and
a second conductor layer (wiring layer 80) formed on the second resin insulating layer and comprising a second seed layer (seed layer 81, wiring layer 80 includes a seed layer 81 and a metal layer 84, para. [0065]) and a second electrolytic plating layer (metal layer 84, Fig. 23, the metal layer 84 (electrolytic copper plating layer), para. [0113]) formed on the second seed layer,
wherein the first conductor layer is formed such that the first electrolytic plating layer formed on the first seed layer (para. [0111]), and the second conductor layer is formed such that a second seed layer is a sputtering layer (seed layer 51 can be formed, for example, through a sputtering process, para. [0097]) and the second electrolytic plating layer formed on the second seed layer (para. [0113]).
Shimizu does not teach, the first seed layer is an electroless plating layer. However, Nishioka teaches, a printed wiring board including the first seed layer is an electroless plating layer (seed layers are each a base layer for forming an electrolytic plating layer on a surface of each of the interlayer insulating layers 21, 24, are an electroless plating layer, para. [0043]). Therefore, in view of the teachings of Nishioka, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the printed wiring board of Shimizu and to replace the first seed layer 71 of Shimizu with an electroless plating layer as Nishoka taught in Fig. 5C so that it enables forming the electrolytic copper metal layers.
Regarding claim 14, Shimizu in view of Nishioka teaches the recited limitations. Shimizu further teaches, the printed wiring board according to claim 1, further comprising: a plurality of resin insulating layers formed on the second resin insulating layer; and a plurality of conductor layers formed such that the resin insulating layers and the conductor layers are alternately laminated and that one of the resin insulating layers is covering the second conductor layer formed on the second resin insulating layer (build-up process stacks wiring layers and insulating layers on the upper and lower surfaces of the core substrate, para. [0003, 0046]).
Regarding claim 15, Shimizu in view of Nishioka teaches the recited limitations. Shimizu further teaches, the printed wiring board according to claim 1, wherein each side of the printed wiring board has a length of 50 mm or more (para. [0032], unless otherwise defined, the selection of a specific length is a design choice).
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nishioka as applied to claim 1 above, and further in view of Adachi (US 20190124766).
Regarding claim 6, Nishioka does not teach, the recited limitations. However, Adachi teaches, a printed wiring board, comprising: a conductor layer (34F) including a pad; a first resin insulating layer (50F) laminated on the conductor layer; a first conductor layer (58F) formed on the first resin insulating layer (50F) and comprising a first seed layer (42ts,) and a first electrolytic plating layer (44ts) formed on the first seed layer; a second resin insulating layer (150F) laminated on the first resin insulating layer such that the second resin insulating layer is covering the first conductor layer; and a second conductor layer (158F) formed on the second resin insulating layer and comprising a second seed layer (42gf) and a second electrolytic plating layer (44gf) formed on the second seed layer, wherein the first conductor layer is formed such that the first seed layer is an electroless plating layer (para. [0103]) and the first electrolytic plating layer formed on the first seed layer, in which,
the printed wiring board according to claim 1, wherein the first conductor layer has a first conductor circuit having a first width such that the first width is a smallest width in the first conductor layer (the first conductor circuit widths (Ltf) include a minimum first conductor circuit width (minimum wiring width) (Ltfm), para. [0070]), the second conductor layer has a second conductor circuit having a second width such that the second width is a smallest width in the second conductor layer (the second conductor circuit widths (Lts) include a minimum second conductor circuit width (minimum wiring width) (Ltsm), para. [0071]) and that the first width of the first conductor circuit in the first conductor layer is larger than the second width of the second conductor circuit in the second conductor layer (the claimed width is a design choice). Therefore, in view of the teachings of Adachi, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the printed wiring board of Nishioka and to select the first width and the second width as Adachi taught in para. [0070-0071] so that it enables a wiring board having reduces size and thickness as Adachi disclosed in para. [0091-0098]. An arbitrary selection between alternatives that perform the same function in substantially the same way, and the applicant has not demonstrated any unexpected results or functional advantages associated with the claimed design.
Allowable Subject Matter
Claims 2-5, 7-13, 16-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for indicating allowable subject matter:
Claim 2 would be allowable for disclosing a printed wiring board, wherein the first conductor layer has voids in at least one of the first seed layer and a boundary portion between the first seed layer and the first electrolytic plating layer, and the second conductor layer does not have voids in the second seed layer and in a boundary portion between the second seed layer and the second electrolytic plating layer. Claims 3 and 17-19 are allowable by virtue of its dependency.
Claim 4 would be allowable for disclosing a printed wiring board, wherein the first via conductor is formed such that voids exist in a connecting portion between the pad and the first via conductor and that the voids in the connecting portion exist in at least one of the first seed layer, a boundary portion between the first seed layer and the first electrolytic plating layer in the connecting portion, and a boundary portion between the first seed layer and the pad, and the second conductor layer does not have voids in the second seed layer and in a boundary portion between the second seed layer and the second electrolytic plating layer. Claims 5 and 16 are allowable by virtue of its dependency.
Claim 7 would be allowable for disclosing a printed wiring board, wherein the third conductor layer is formed such that the third seed layer is an electroless plating layer and that the third conductor layer has voids in at least one of the third seed layer and a boundary portion between the third seed layer and the third electrolytic plating layer.
Claim 8 would be allowable for disclosing a printed wiring board, wherein the second resin insulating layer includes a resin and inorganic particles such that the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin, that each of the first inorganic particles has a first portion protruding from the resin and a second portion embedded in the resin, and that the second resin insulating layer has a surface including a surface of the resin and exposed surfaces of the first portions exposed from the surface of the resin. Claims 9-13 are allowable by virtue of its dependency.
Though, prior art of records Shimizu and Adachi teach, a printed wiring board comprising: a first via conductor formed in a first opening formed in the first resin insulating layer and comprising the first seed layer and the first electrolytic plating layer such that the first via conductor is connecting the first conductor layer and the pad in the conductor layer; and a third resin insulating layer formed on the second resin insulating layer such that the third resin insulating layer is covering the second conductor layer; and a third conductor layer formed on the third resin insulating layer and comprising a third seed layer and a third electrolytic plating layer formed on the third seed layer; Shimizu and Adachi fail to teach, the first conductor layer has voids in at least one of the first seed layer and a boundary portion between the first seed layer and the first electrolytic plating layer, and the second conductor layer does not have voids in the second seed layer and in a boundary portion between the second seed layer and the second electrolytic plating layer; or resin insulating layer includes a resin and inorganic particles such that the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin, that each of the first inorganic particles has a first portion protruding from the resin and a second portion embedded in the resin, and that the second resin insulating layer has a surface including a surface of the resin and exposed surfaces of the first portions exposed from the surface of the resin.
Prior art of record Nishioka does not teach, the first conductor layer has voids in at least one of the first seed layer and a boundary portion between the first seed layer and the first electrolytic plating layer, and the second conductor layer does not have voids in the second seed layer and in a boundary portion between the second seed layer and the second electrolytic plating layer; or resin insulating layer includes a resin and inorganic particles such that the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin, that each of the first inorganic particles has a first portion protruding from the resin and a second portion embedded in the resin, and that the second resin insulating layer has a surface including a surface of the resin and exposed surfaces of the first portions exposed from the surface of the resin.
Therefore, claims 2, 4 and 7-8 would be allowable. Claims 3, 5, 9-13 and 16-19 would be allowable by virtue of its dependency.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Prior art Kajihara (US 20170033036) teaches, a printed wiring board, comprising: a conductor layer including a pad; a first resin insulating layer laminated on the conductor layer; a first conductor layer comprising a first seed layer and a first electrolytic plating layer; a second resin insulating layer; and a second conductor layer formed on the second resin insulating layer and comprising a second seed layer and a second electrolytic plating layer formed on the second seed layer, wherein the first conductor layer is formed such that the first seed layer is an electroless plating layer and the first electrolytic plating layer formed on the first seed layer, and the second conductor layer is formed such that a second seed layer is a sputtering layer and the second electrolytic plating layer formed on the second seed layer.
Prior art Sciriha (US 20200286982) teaches, a printed wiring board, including a conductor layer including a pad; a first resin insulating layer; a first conductor layer comprising a first seed layer and a first electrolytic plating layer; a second resin insulating layer; and a second conductor layer formed on the second resin insulating layer and comprising a second seed layer and a second electrolytic plating layer formed on the second seed layer, an electroless plating layer and a sputtering layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSE K ABRAHAM/Examiner, Art Unit 3729
