DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-10 in the “Response To Restriction Requirement” filed on March 12, 2026 (hereinafter the “Restriction Response”) is acknowledged. Applicant’s Restriction Response did not indicate whether the election of Group I, claims 1-10 was without traverse or with traverse, as required by paragraph seven (7) of the Restriction Requirement dated January 12, 2026 (hereinafter the “Restriction Requirement”). Also, Applicant’s Restriction Response did not distinctly and specifically point out any supposed errors in the Restriction Requirement. Accordingly, the election has been treated as an election without traverse. Please see, MPEP § 818.01(a). Claims 11-20 are hereby withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions (Group II, claims 11-17 and Group III, claims 18-20), as detailed in the Restriction Requirement.
Information Disclosure Statement
Except as noted, the Information Disclosure Statements (IDSs) submitted on November 6, 2023 and January 5, 2026 are in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the references cited in the IDSs are being considered by the Examiner, except for the Office Action dated December 16, 2025 issued in the corresponding Korean Patent Application No. 10-2022-01733450 which is not in the English language and does not comply with 37 C.F.R. 1.98(a)(3). Please see, MPEP 609.04(a)(III).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0075596 A1 (Shin) in view of US 2020/0105909 A1 (Wu) and further in view of US 2018/0151556 A1 (Choi).
Regarding claim 1, Shin discloses, A semiconductor device (semiconductor device (100); FIG. 2; [0019]) comprising:
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a substrate (substrate (110); FIG. 2; [0020]);
an active pattern (active pattern (ACT1); FIG. 2; [0023]) disposed on the substrate (110) and extending in a first direction (first direction (X); annotated FIG. 2, above; [0023]);
a plurality of gate electrodes (plurality of gate electrodes (GL); FIG. 2; [0025]) covering the active pattern (ACT1) and extending in a second direction (first direction (Y); FIG. 1), the second direction (Y) intersecting the first direction (X);
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a gate spacer (gate spacer (128); FIG. 2; [0025]) disposed on a sidewall (annotated FIG. 2, above) of each of the plurality of gate electrodes (GL);
a source/drain pattern (source/drain pattern (132); FIG. 2; [0031]) disposed between adjacent ones of the plurality of gate electrodes (GL);
an etch stop film ([0038]);
an interlayer insulating film (interlayer insulating film (144); FIG. 2; [0039]) disposed between the adjacent ones of the plurality of gate electrodes (GL), wherein a contact trench (FIG. 10 and annotated FIG. 11, below) exposing the source/drain pattern (132) is defined in the interlayer insulating film (144);
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a liner film (liner film (166B); FIGs 2 and 12; [0050]) disposed on an outer sidewall (annotated FIG. 11, above) of the contact trench (annotated FIG. 11, above); and
a source/drain contact (source/drain contact (160); FIG. 2; [0048]) disposed on the liner film (166B) and filling the contact trench (annotated FIG. 11, above), wherein the source/drain contact (160) is connected (FIG. 2) to the source/drain pattern (132).
But, Shin does not appear to explicitly disclose,
the etch stop film disposed along a sidewall of the gate spacer and a profile of the source/drain pattern,
wherein at least a portion of the liner film is disposed in the source/drain pattern.
However, in analogous art, Wu discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor device (semiconductor device (10); FIG. 1; [0015]) may include an etch stop film (etch stop film (58); FIG. 1; [0016]) disposed along a sidewall (annotated FIG. 1, below) of a gate spacer (gate spacer (52); FIG. 1; [0016]) and a profile (annotated FIG. 1, below) of a source/drain pattern (source/drain pattern (54); FIG. 1; [0016]).
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Wu also discloses that during fabrication of semiconductor device (10), etch stop film (58) is not significantly etched during etching such that air gaps (air gaps (60d); FIG. 1; [0018]) are formed ([0065]). Wu additionally discloses, that air gaps (60d) function as an air spacer and reduce parasitic capacitance between replacement gates and later formed source/drain contacts, hence improving performance of semiconductor device (10).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention having the teachings of Shin and Wu before him/her that etch stop film ([0038] of Shin) of Shin be disposed along a sidewall of the gate spacer (128) and a profile of the source/drain pattern (132) thereof, as taught by Wu, to form air gaps that function as an air spacer and reduce parasitic capacitance between gate electrodes (GL) and source/drain contacts (160) of Shin, as also taught by Wu, thereby improving performance of semiconductor device (100) of Shin, as additionally taught by Wu. See also, MPEP 2144(IV)—Rational Different From Applicant’s Is Permissible—The reason or motivation to modify the reference may often suggest what the inventor has done, but for a different purpose or to solve a different problem. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant.
But, Applicant may argue that Shin in view of Wu does not appear to explicitly disclose,
wherein at least a portion of the liner film is disposed in the source/drain pattern.
However, in analogous art, Choi discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor device (FIG. 2) may be predicably fabricated to include a liner film (liner film (410); FIG. 2; [0058]) having a portion disposed in a source/drain pattern (source/drain pattern (300); FIG. 2; [0028]). Choi additionally discloses that a thickness of liner film (410) can be used to control a width of a metal resistor (metal resistor (400); FIG. 2; [0028]), thereby tuning a resistance value of metal resistor (400) ([0066]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention having the teachings of Shin , Wu, and Choi before him/her that at least a portion of the liner film (166B) of Shin in view of Wu is disposed in the source/drain pattern (132) of Shin in view of Wu, as taught by Choi, to control a resistance vale of source/drain contact (160), as also taught by Choi. See also, MPEP 2144(IV), above.
Regarding claim 2, Shin in view of Wu and Choi discloses, The semiconductor device (100) of claim 1, further comprising a gate capping film (gate capping film (126); FIG. 2; [0025], all of Shin) disposed on the each of the plurality of gate electrodes (GL),
wherein at least a portion of the liner film (166B) is in contact with the gate capping film (126) (166B contacts 126 via interlayer insulating layer (144) of Shin; claim 2 does not require direct contact between 166B and 126).
Regarding claim 3, Shin in view of Wu and Choi discloses, The semiconductor device (100) of claim 2, wherein the etch stop film ([0038] of Shin) is not disposed on a sidewall of the gate capping film (126) ([0038] of Shin—an etch stop layer (not shown) may be further formed on the side walls of source/drain pattern 132, side walls of the second source/drain region 134, and the top surface of the isolation layer 112).
Regarding claim 4, Shin in view of Wu and Choi discloses, The semiconductor device (100) of claim 1, wherein the liner film (166B) includes a first portion (the width of liner film (166B)) extending in the first direction (X), and a second portion (annotated FIG. 2 of Shin, above) disposed on the first portion (the width of liner film (166B)) and extending in a third direction (third direction (Z); annotated FIG. 2 of Shin, above), with the third direction (Z) intersecting the first direction (X) and the second direction (Y).
Regarding claim 5, Applicant may argue that Shin in view of Wu and Choi does not explicitly disclose, wherein a vertical level of a bottom surface of the source/drain contact based on an upper surface of the substrate is lower than a vertical level of a bottom surface of the liner film based on the upper surface of the substrate.
However, one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Shin, Wu, and Choi before him/her would have recognized that there are a finite number of predicable solutions regarding a vertical level of a bottom surface of the source/drain contact (160) of Shin in view of Wu and Choi based on an upper surface (upper surface (110F1); FIG. 2; [0023], all of Shin) of the substrate (110) thereof relative to a vertical level of a bottom surface of the liner film (166B) of Shin in view of Wu and Choi based on the upper surface (110F1) of the substrate (110) thereof—i.e., the vertical level of the bottom surface of the source/drain contact (160) based on an upper surface (110F1) of the substrate (110) can be: (i) the same as the vertical level of a bottom surface of the liner film (166B) based on the upper surface (110F1) of the substrate (110), (ii) higher than the vertical level of a bottom surface of the liner film (166B) based on the upper surface (110F1) of the substrate (110), or (iii) lower than the vertical level of a bottom surface of the liner film (166B) based on the upper surface (110F1) of the substrate (110)—and, absent unexpected results, it would have been obvious to try each of these three possibilities one of which is wherein a vertical level of a bottom surface of the source/drain contact (160) based on an upper surface (110F1) of the substrate (110) is lower than a vertical level of a bottom surface of the liner film (166B) based on the upper surface (110F1) of the substrate (110), as recited in dependent claim 5. Please see, MPEP 2143(E)—“Obvious To Try”—Choosing From A Finite Number Of Identified, Predicable Solutions, With A Reasonable Expectation Of Success.
Regarding claim 6, Shin in view of Wu and Choi discloses, The semiconductor device (100) of claim 1, wherein the active pattern (ACT1) includes a lower pattern (annotated FIG. 2 of Shin, above), and at least one sheet pattern (sheet pattern (FA1); FIG. 2; [0023]) disposed on the lower pattern (annotated FIG. 2 of Shin, above), wherein the at least one sheet pattern (FA1) is in contact (FIG. 2) with the source/drain pattern (132).
Regarding claim 7, Shin in view of Wu and Choi discloses, The semiconductor device (100) of claim 1, further comprising a gate contact (gate contact (150); FIG. 2; [0040]) connected (FIG. 2) to the each of the plurality of gate electrodes (GL), wherein an upper surface (annotated FIG. 2 of Shin, above) of the gate contact (150) is coplanar with an upper surface (annotated FIG. 2 of Shin, above) of the source/drain contact (160).
Regarding claim 8, Shin in view of Wu and Choi discloses, The semiconductor device (100) of claim 1, wherein a thickness of the liner film (166B) is constant (FIG. 2 of Shin shows the thickness of liner film (166B) is constant).
Regarding claim 9, Shin in view of Wu and Choi discloses, The semiconductor device (100) of claim 1, wherein the etch stop film ([0038 of Shin]) includes a nitride-based insulating material ([0038 of Shin]).
Regarding claim 10, Shin in view of Wu and Choi discloses, The semiconductor device (100) of claim 1, wherein the liner film (166B) includes an oxide-based insulating material ([0111] of Shin).
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
US 2023/0197716A1 (Bomberger)—Discloses that it was well-known to one of ordinary skill in the art before the effective date of the claimed invention that a semiconductor device may include source/drain liners (215) in source/drain trenches (217) to increase contact area between a metal contact and source/drain material, reduce contact resistance, and increase current at operating voltage, thereby improving overall performance of the semiconductor device ([0016]).
US 2017/0213905 A1 (Lee)—Discloses a semiconductor device having a substrate (110), an active pattern (FA), and a plurality of gate electrodes (140). Also discloses, a gate spacer (144) disposed on a sidewall of each of the plurality of gate electrodes (140), an interlayer insulating film (120) between adjacent ones of the plurality of gate electrodes (140), and source drain patterns (162) disposed between adjacent ones of the plurality of gate electrodes (140).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights