DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: VERTICAL MEMORY DEVICE COMPRISING DISCHARGE STRUCTURE
Claim Objections
Claim 2 is objected to because of the following informalities: “the active region is includes” should be changed to “the active region includes”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, and 8-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwak et al. (US 2020/0373321 A1; hereinafter “Kwak”).
Regarding claim 1, referring to Fig. 5 and related text, Kwak teaches a semiconductor device, comprising: a lower substrate (10) (paragraphs 70-71); an active region (TRSD of 21) on the lower substrate (paragraphs 70-72); a common source plate (11) spaced apart from an upper surface of the lower substrate (an upper surface of 10) in a vertical direction (TD), and the common source plate at least partly overlapping the upper surface of the lower substrate (paragraphs 37 and 55-58); a discharge structure (DP and 30) directly connecting the common source plate and the active region in the vertical direction, the discharge structure having a structure in which a plurality of discharge contact plugs (either 24 or 23A-23C) and a plurality of discharge conductive patterns (either 23A-23C or 24) are alternately stacked (paragraphs 66-70, 74, and 83); and a cell array structure (110) on the common source plate (paragraphs 58-62), wherein the discharge contact plugs extend parallel to the upper surface of the lower substrate (Fig. 5), and the conductive patterns extend parallel to the upper surface of the lower substrate (Fig. 5).
Regarding claim 3, Kwak teaches wherein the discharge contact plugs and the discharge conductive patterns independently include at least one of a metal or polysilicon (paragraph 75).
Regarding claim 4, Kwak teaches wherein the discharge contact plugs and the conductive patterns extend in the same direction, and each of the discharge conductive patterns covers an upper surface of a discharge contact plug thereunder (Fig. 5).
Regarding claim 5, Kwak teaches wherein a length of each of the discharge contact plugs (23A-23C of DP is considered as “the discharge contact plugs” and a length of 23A-23C in a direction FD) extending direction is greater than a width of each of the discharge conductive patterns (24 of DP is considered as “the discharge conductive patterns” and a width of 24 in the direction FD) contacting the discharge contact plugs (Fig. 5).
Regarding claim 8, Kwak teaches wherein the discharge contact plugs and the conductive patterns extend in directions perpendicular to each other (for example, 24 extend in SD and 23A-23C extend in FD), and the discharge contact plugs and the discharge conductive patterns cross each other (Fig. 5).
Regarding claim 9, Kwak teaches wherein the discharge structure includes a plurality of discharge structures (a plurality of DPs), and the plurality of discharge structures are disposed to be spaced apart from each other (Fig. 7).
Regarding claim 10, Kwak teaches wherein the cell array structure includes: a gate stack (40 and 42) on the common source plate, the gate stack including a plurality of gate patterns (40) spaced apart from each other in the vertical direction and an insulation layer (42) interposed between the gate patterns (Fig. 5 and paragraphs 58-60); and a plurality of channel structures (CH) passing through the gate stack in the vertical direction, and the plurality of channel structures contacting an upper portion of the common source plate (an upper portion of 11) (Fig. 5 and paragraph 61).
Regarding claim 11, Kwak teaches further comprising: a peripheral circuit (TRXDEC) on the lower substrate, wherein the peripheral circuit is spaced apart from the discharge structure, and includes a peripheral circuit pattern (a TRXDEC pattern) and a multilayer wiring structure (23A-23C and 24 electrically connected to TRXDEC) (Fig. 5 and paragraph 72).
Regarding claim 12, Kwak teaches wherein the multilayer wiring structure has a structure in which a plurality of lower contact plugs (24 electrically connected to TRXDEC) and a plurality of lower conductive patterns (23A-23C electrically connected to TRXDEC) are alternately stacked (Fig. 5 and paragraphs 70-72), each of the lower contact plugs and each of the discharge contact plug positioned at a first same level (Fig. 5), and each of the lower conductive patterns and each of the discharge conductive patterns positioned at a second same level (Fig. 5).
Regarding claim 13, referring to Fig. 5 and related text, Kwak teaches a semiconductor device, comprising: a lower substrate (10) (paragraphs 70-71); an active region (TRSD of 21) on the lower substrate (paragraphs 70-72); a common source plate (11) spaced apart from an upper surface of the lower substrate (an upper surface of 10) in a vertical direction (TD), the common source plate at least partly overlapping the upper surface of the lower substrate (paragraphs 37 and 55-58); a discharge structure (DP and 30) directly connecting the common source plate and the active region in the vertical direction, the discharge structure having a wall shape (a wall shape of 30) extending in a first direction (FD) parallel to the upper surface of the lower substrate (paragraphs 37, 66-70, 74, and 83); and a cell array structure (110) on the common source plate (paragraphs 58-62), wherein a length of the discharge structure (a length of 30) in the first direction is greater than a width of the discharge structure (a width of DP including a plug formation) in a second direction (SD) parallel to the upper surface of the lower substrate and perpendicular to the first direction (Figs. 3 and 5).
Regarding claim 14, Kwak teaches wherein the discharge structure has a structure in which a plurality of discharge contact plugs (24) and a plurality of discharge conductive patterns (23A-23C) are alternately stacked (Fig. 5 and paragraphs 66-70, 74, and 83).
Regarding claim 15, Kwak teaches wherein a long axis direction of the discharge contact plugs (a direction of 24 in FD) and a long axis direction of the discharge conductive patterns (a direction of 23A-23C in FD) are in the first direction (Fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak.
Regarding claim 2, Kwak does not explicitly teach that the lower substrate includes P-type impurities, and the active region includes N-type impurities, such that the lower substrate and the active region correspond to a Zener diode. Nevertheless, after reviewing Kwak teaching that the lower substrate include silicon substrate (Fig. 5 and paragraph 71) and the transistors including source and drain regions as the active region formed on the substrate (Fig. 5 and paragraph 72), it would have been obvious to one of ordinary skill in the art to provide the peripheral circuits (logic circuits 21) including NMOS transistors with n-type source and drain regions formed in the substrate having p-type wells by ion implantation processes as a well-known transistor formation processing on the substrate for providing predictable peripheral circuit transistors on the semiconductor substrate, wherein the P-N junction created is capable of forming a Zener diode characteristics in a reverse bias condition.
Regarding claim 18, referring to Fig. 5 and related text, Kwak teaches a semiconductor device, comprising: a lower substrate (10) (paragraphs 70-71); a peripheral circuit (TRXDEC of 21) including a peripheral circuit pattern (a TRXDEC pattern) and a multilayer wiring structure (23A-23C and 24 electrically connected to TRXDEC) on the lower substrate (paragraphs 70-72); an active region (TRSD of 21) on the lower substrate (paragraphs 70-72); a common source plate (11) spaced apart from an upper surface of the lower substrate (an upper surface of 11) in a vertical direction (TD), the common source plate at least partly overlapping the upper surface of the lower substrate (Fig. 5 and paragraphs 37 and 55-58); a discharge structure (DP and 30) directly connecting the common source plate and the active region in the vertical direction, the discharge structure including a plurality of discharge contact plugs (23A-23C) and a plurality of discharge conductive patterns (24) are alternately stacked (Fig. 5 and paragraphs 66-70, 74, and 83); a gate stack (40 and 42) on the common source plate, the gate stack including a plurality of gate patterns (40) spaced apart from each other in the vertical direction and an insulation layer (42) interposed between the gate patterns (paragraphs 58-60); and a channel structure (CH) passing through the gate stack in the vertical direction, the channel structure contacting an upper portion of the common source plate (an upper portion of 11) (paragraph 61), wherein the discharge conductive patterns and the discharge contact plugs extend in a first direction (FD) parallel to the upper surface of the lower substrate such that the first direction is a long axis direction of each of discharge conductive patterns and the discharge contact plugs (a direction of 23A-23C and 24 in FD) (Fig. 5), and a length of each of the discharge contact plugs in the first direction (a length of 23A-23C in a direction FD) is greater than a width of each of the discharge conductive patterns (a width of 24 in the direction FD) contacting each discharge contact plugs (Fig. 5).
Kwak does not explicitly teach that the active region including N-type impurities. Nevertheless, after reviewing Kwak teaching that the lower substrate include silicon substrate (Fig. 5 and paragraph 71) and the transistors including source and drain regions as the active region formed on the substrate (Fig. 5 and paragraph 72), it would have been obvious to one of ordinary skill in the art to provide the peripheral circuits (logic circuits 21) including NMOS transistors with n-type source and drain regions formed in the substrate for providing predictable peripheral circuit transistors on the semiconductor substrate.
Regarding claim 19, Kwak teaches wherein the discharge structure has a wall shape (a wall shape of 30) extending in the first direction (FD) (Fig. 5).
Regarding claim 20, Kwak teaches wherein the multilayer wiring structure has a structure in which a plurality of lower contact plugs (23A-23C electrically connected to TRXDEC) and a plurality of lower conductive patterns (24 electrically connected to TRXDEC) are alternately stacked (Fig. 5).
Allowable Subject Matter
Claims 6-7 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nishikawa et al. (US 2019/0371800 A1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893