DETAILED ACTION
Claim Objections
Claim 10 is objected to because of the following informalities: “a gate stack” in line 3 should be changed to “the gate stack”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 8-15, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2021/0343342 A1; hereinafter “Lee”).
Regarding claim 1, referring to Fig. 4-5A and 6, Lee teaches a semiconductor device, comprising: a lower substrate (52) (paragraphs 78-79); an active region (AC including 42) on the lower substrate (paragraphs 79 and 85-89); a common source plate (110) spaced apart from an upper surface of the lower substrate (an upper surface of 52) in a vertical direction (a z-direction), and the common source plate at least partly overlapping the upper surface of the lower substrate (Fig. 6 and paragraphs 50-56); a discharge structure (P280 directly connecting 110 and AC including 42) directly connecting the common source plate and the active region in the vertical direction, the discharge structure having a structure in which a plurality of discharge contact plugs (either MC60-MC62 with 46 or ML60-ML62) and a plurality of discharge conductive patterns (either ML60-ML62 or MC60-MC62 with 46) are alternately stacked (Fig. 6 and paragraphs 82-89 and 92-93); and a cell array structure (CAS) on the common source plate, the cell array structure including a gate stack (GS) (Figs. 4 and 6 and paragraphs 50-54), wherein the plurality of discharge contact plugs extend parallel to the upper surface of the lower substrate (for example, MC60-MC62 with 46 extend parallel to the upper surface of 52) (Fig. 6), the plurality of discharge conductive patterns extend parallel to the upper surface of the lower substrate (for example, ML60-ML62 extend parallel to the upper surface of 52) (Fig. 6), and an extending direction of the gate stack is perpendicular to an extending direction of each of the plurality of discharge contact plugs (for example, an extending direction of GS in an x-direction as shown in Fig. 4 is perpendicular to an extending direction of MC60-MC62 and 46 in a y-direction as shown in Fig. 6) (Figs. 4 and 6).
Regarding claim 3, Lee teaches wherein the plurality of discharge contact plugs and the plurality of discharge conductive patterns independently include at least one of a metal or polysilicon (paragraph 90).
Regarding claim 4, Lee teaches wherein the plurality of discharge contact plugs and the plurality of conductive patterns extend in a same direction (the y-direction), and each of the plurality of discharge conductive patterns covers an upper surface of a discharge contact plug thereunder (Fig. 6).
Regarding claim 5, Lee teaches wherein a length of each of the plurality of discharge contact plugs in an extending direction (for example, a length of ML60-ML62 in the y-direction) is greater than a width of each of the plurality of discharge conductive patterns (a width of MC60-MC62 with 46 in the y-direction) contacting the plurality of discharge contact plugs (Fig. 6).
Regarding claim 8, Lee teaches wherein the plurality of discharge contact plugs and the plurality of conductive patterns extend in directions perpendicular to each other (for example, MC60-MC62 with 46 extend in the y-direction and ML60-ML62 extend in the x-direction), and the plurality of discharge contact plugs and the plurality of discharge conductive patterns cross each other (Fig. 6).
Regarding claim 9, Lee teaches wherein the discharge structure includes a plurality of discharge structures, and the plurality of discharge structures are disposed to be spaced apart from each other (P280 shown in Fig. 6 is repeated in TA as shown in Fig. 5A for forming a plurality of P280) (Figs. 5A and 6).
Regarding claim 10, Lee teaches wherein the cell array structure includes: a gate stack (GS) on the common source plate, the gate stack including a plurality of gate patterns (130) spaced apart from each other in the vertical direction and an insulation layer (134) interposed between the plurality of gate patterns (Fig. 6 and paragraphs 65-66); and a plurality of channel structures (160) passing through the gate stack in the vertical direction, and the plurality of channel structures contacting an upper portion of the common source plate (an upper portion of 110) (Fig. 6 and paragraph 70).
Regarding claim 11, Lee teaches further comprising: a peripheral circuit (PCS) on the lower substrate, wherein the peripheral circuit is spaced apart from the discharge structure, and includes a peripheral circuit pattern (TR of PCS) and a multilayer wiring structure (MC60-MC62 and ML60-ML62 of PCS) (Fig. 6 and paragraphs 52 and 61).
Regarding claim 12, Lee teaches wherein the multilayer wiring structure has a structure in which a plurality of lower contact plugs (MC60-MC62) and a plurality of lower conductive patterns (ML60-ML62) are alternately stacked (Fig. 6), each of the plurality of lower contact plugs and each of the plurality of discharge contact plug are positioned at a first same level (Fig. 6), and each of the plurality of lower conductive patterns and each of the plurality of discharge conductive patterns are positioned at a second same level (Fig. 6).
Regarding claim 13, referring to Fig. 4-5A and 6, Lee teaches a semiconductor device, comprising: a lower substrate (52) (paragraphs 78-79); an active region (AC including 42) on the lower substrate (paragraphs 79 and 85-89); a common source plate (110) spaced apart from an upper surface of the lower substrate (an upper surface of 52) in a vertical direction (a z-direction), the common source plate at least partly overlapping the upper surface of the lower substrate (Fig. 6 and paragraphs 50-56); a discharge structure (P280 directly connecting 110 and AC including 42) directly connecting the common source plate and the active region in the vertical direction, the discharge structure having a wall shape (a wall shape of P280) extending in a first direction (a y-direction) parallel to the upper surface of the lower substrate (Fig. 6 and paragraphs 82-89 and 92-93); and a cell array structure (CAS) on the common source plate, the cell array structure including a gate stack (GS) (Figs. 4 and 6 and paragraphs 50-54), (paragraphs 58-62), wherein a length of the discharge structure in the first direction (a length of P280 having ML60-ML62 in the y-direction) is greater than a width of the discharge structure in a second direction (a width of P280 having MC60-MC62 as a plug structure in a x-direction) parallel to the upper surface of the lower substrate and perpendicular to the first direction (Fig. 6); and the gate stack extends in the second direction (GS extends in the x-direction as shown in Fig. 4) (Fig. 4).
Regarding claim 14, Lee teaches wherein the discharge structure has a structure in which a plurality of discharge contact plugs (MC60-MC62 with 46) and a plurality of discharge conductive patterns (ML60-ML62) are alternately stacked (Fig. 6 and paragraphs 82-89 and 92-93).
Regarding claim 15, Lee teaches wherein a long axis direction of the plurality of discharge contact plugs (a direction of MC60-MC62 with 46 in the y-rection) and a long axis direction of the plurality of discharge conductive patterns (a direction of ML60-ML62 in the y-rection) are in the first direction (Fig. 6).
Regarding claim 18, referring to Fig. 4-5A and 6, Lee teaches a semiconductor device, comprising: a lower substrate (52) (paragraphs 78-79); a peripheral circuit (PCS) including a peripheral circuit pattern (PCS including TR) and a multilayer wiring structure (MC60-MC62 and ML60-ML62) on the lower substrate (paragraphs 52 and 78-82); an active region (AC including 42) on the lower substrate, the active region including N-type impurities (for example, 42 having an n-type conductivity) (paragraphs 79 and 85-89); a common source plate (110) spaced apart from an upper surface of the lower substrate (an upper surface of 52) in a vertical direction (a z-direction), the common source plate at least partly overlapping the upper surface of the lower substrate (Fig. 6 and paragraphs 50-56); a discharge structure (P280 directly connecting 110 and AC including 42) directly connecting the common source plate and the active region in the vertical direction, the discharge structure including a plurality of discharge contact plugs (ML60-ML62) and a plurality of discharge conductive patterns (MC60-MC62 with 46) are alternately stacked (Fig. 6 and paragraphs 82-89 and 92-93); a gate stack (GS) on the common source plate, the gate stack including a plurality of gate patterns (130) spaced apart from each other in the vertical direction and an insulation layer (134) interposed between the plurality of gate patterns (Fig. 6 and paragraphs 65-66); and a channel structure (160) passing through the gate stack in the vertical direction, the channel structure contacting an upper portion of the common source plate (an upper portion of 110) (Fig. 6 and paragraph 70), wherein the plurality of discharge conductive patterns and the plurality of discharge contact plugs extend in a first direction (a y-direction) parallel to the upper surface of the lower substrate such that the first direction is a long axis direction of each of the plurality of discharge conductive patterns and the plurality of discharge contact plugs (a direction of ML60-ML62 and MC60-MC62 with 46 in the y-direction as a long axis direction) (Fig. 6), and a length of each of the plurality of discharge contact plugs in the first direction (a length of ML60-ML62 in the y-direction) is greater than a width of each of the plurality of discharge conductive patterns (a width of MC60-MC62 with 46 in the y-direction) contacting each discharge contact plugs (Fig. 6), and the gate stack extends in a second direction perpendicular to the first direction (GS extends in a x-direction, which is perpendicular to the y-direction, as shown in Fig. 4) (Figs. 4 and 6).
Regarding claim 19, Lee teaches wherein the discharge structure has a wall shape (a wall shape of P280) extending in the first direction (Fig. 6).
Regarding claim 20, Lee teaches wherein the multilayer wiring structure has a structure in which a plurality of lower contact plugs (MC60-MC62) and a plurality of lower conductive patterns (ML60-ML62) are alternately stacked (Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding claim 2, Lee teaches wherein the lower substrate includes P-type impurities, and the active region includes N-type impurities (paragraph 85). While Lee does not explicitly teach that the lower substrate and the active region having such PN diode correspond to a Zener diode, it would have been obvious to one of ordinary skill in the art would recognize that such PN diode of the lower substrate and the active region is capable of functioning as the Zener diode characteristics in a reverse bias condition.
Allowable Subject Matter
Claims 6-7 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot in view of new grounds of rejections as set forth above in this Office Action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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