Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/13/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuji (US 2022/0300207) in view of Gibb (US 2022/0197704).
As per claim 1, Tsuji discloses a device, comprising:
a network interface configured to provide storage services over a computer network (Paragraph 68 “The host 10 and the CS 30 can be connected to each other through the CS I/F circuit 16, a connection line, and the host I/F circuit 52.”);
a plurality of processors (Paragraph 42 “one or more processor(s) “);
a random-access memory configured to host a plurality of queues, shared among the plurality of processors and the apparatus, in providing the storage services (Paragraph 68 “a command queue 20”).
Tsuji does not expressly disclose but Gibb discloses
to multiple remote host systems (Paragraph 95 “In some examples, additional hosts or additional CSPs, or both, may be connected to the bridge of one or both of the CSP-1 400 and CSP-2 430. In the example shown in FIG. 4, the bridge 420 of CSP-1 400 is connected to a third host, HOST-3 460, and the bridge 450 of CSP-2 430 is connected to a third CSP, CSP-3 470. The bridge 420 may be connected to the HOST-3 460 by any suitable wired or wireless connection, and may form part of, for example, a dedicated PCIe connection, a LAN, or a WAN. Similarly, the bridge 450 may be connected to CSP-3 470 by any suitable wired or wireless connection, and may form part of, for example, a dedicated PCIe connection, a LAN, or a WAN.”);
a connector (Fig. 1, IFC 2) connectable to an apparatus (Fig. 1, CSF 2) outside of the device (Paragraph 16 “In an example embodiment, the first one of the plurality of CQ is a CQ that is accessed by the host connected to the CSP, and the second one of the plurality of CQ is a CQ that is not accessed by the host of the CSP.”) without connecting to the connector, wherein the connector is different from the network interface (Fig. 1 shows that the IFC 2 is not the PCIe 104).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because the bandwidth required by such memory reads and writes degrade CSP performance, or is addressed by utilizing high bandwidth memory, which is expensive and therefore significantly increases the overall cost of the CSP (Gibb, paragraph 4). In this way, the combination benefits by allowing direct signaling with the CSP so as to avoid the bottlenecks described in Gibb.
As per claim 2, Tsuji further discloses wherein the device has a storage capacity and is manufactured as a storage product (Fig. 1, host 10).
As per claim 3, Tsuji further discloses wherein the plurality of processors include a processing device coupled to the network interface to generate storage access messages responsive to communications received in the network interface (Paragraph 36 “In general, according to one embodiment, a computational storage device comprises a nonvolatile memory and a controller configured to control a data process including a first process and a second process. The first process writes data, designated by a first command received from an external device, to the nonvolatile memory. The second process reads data, designated by a second command received from the external device, from the nonvolatile memory and transmits read data to the external device. The controller comprises a processor configured to determine whether to perform the data process in accordance with information included in the first or second command.”).
As per claim 4, Tsuji further discloses wherein the plurality of processors further include a computational storage processor (Paragraphs 41-50).
As per claim 5, Tsuji further discloses wherein the plurality of queues include:
a first set of queues shared between the processing device and the apparatus outside of the device (Paragraph 68 “The command queue 20 is implemented by a memory provided in one of the host 10 and CS 30. In accordance with the Non-Volatile Memory Express (NVMe)™ that is the SSD standard, the command queue 20 includes a plurality of io queues 22 and an admin (administrator) queue 24. As one example, two io queues 22 are shown in FIG.).
As per claim 6, Tsuji further discloses wherein the plurality of queues further include:
a second set of queues shared between the processing device and the computational storage processor (Paragraph 68 “The command queue 20 is implemented by a memory provided in one of the host 10 and CS 30. In accordance with the Non-Volatile Memory Express (NVMe)™ that is the SSD standard, the command queue 20 includes a plurality of io queues 22 and an admin (administrator) queue 24. As one example, two io queues 22 are shown in FIG.).
As per claim 7, Tsuji further discloses wherein the plurality of queues further include:
a third set of queues shared between the processing device and a storage (Paragraph 68 “The command queue 20 is implemented by a memory provided in one of the host 10 and CS 30. In accordance with the Non-Volatile Memory Express (NVMe)™ that is the SSD standard, the command queue 20 includes a plurality of io queues 22 and an admin (administrator) queue 24. As one example, two io queues 22 are shown in FIG.).
As per claim 8, Tsuji further discloses wherein the plurality of queues further include:
a fourth set of queues shared between the storage and the apparatus located outside of the device; and a fifth set of queues shared between the storage and the computational storage processor (Paragraph 68 “The command queue 20 is implemented by a memory provided in one of the host 10 and CS 30. In accordance with the Non-Volatile Memory Express (NVMe)™ that is the SSD standard, the command queue 20 includes a plurality of io queues 22 and an admin (administrator) queue 24. As one example, two io queues 22 are shown in FIG.).
As per claims 9-15, they are method claims having similar limitations as cited in claims 1-8 and are rejected under the same rationale.
As per claims 16-20, they are apparatus claims having similar limitations as cited in claims 1-8 and are rejected under the same rationale.
Response to Arguments
Applicant’s arguments with respect to claim 1-20 have been considered but are not persuasive. The examiner further considered the Gibb reference and cited paragraph 95 which discuses how additional hosts may be connected to the CSPs. In this way, the newly added limitation of to multiple remote host systems is disclosed by Gibb. Thus, the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Beshai (US 8,774,176) discloses a scalable router-switch that grows from a capacity of a few gigabits per second to hundreds of terabits per second is disclosed. In one embodiment, the router-switch comprises a plurality of switch units arranged in a plurality of combinations. Within each combination, each switch unit cyclically connects to each other switch unit to form a contention-free temporal mesh. Each switch unit belongs to a number of combinations and any two combinations have at most one switch unit in common. The router-switch further includes a distributed-control system which comprises an outer controller associated with each of the switch units and an inner controller associated with each combination. The structural simplicity significantly simplifies the operation and control of the router-switch.
Short (US 8,266,266) discloses selectably controlling and customizing source access to a network, where the source is associated with a source computer, and wherein the source computer has transparent access to the network via a gateway device and no configuration software need be installed on the source computer to access the network. A user may be prevented access from a particular destination or site based upon the user's authorization while being permitted to access to other sites that the method and system deems accessible. The method and system can identify a source without that source's knowledge, and can access customizable access rights corresponding to that source in a source profile database. The source profile database can be a remote authentication dial-in user service (RADIUS) or a lightweight directory access protocol (LDAP) database. The method and system use source profiles within the source profile database to dynamically authorize source access to networks and destinations via networks.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY A MUDRICK whose telephone number is (571)270-3374. The examiner can normally be reached 9am-5pm Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571)272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOTHY A MUDRICK/Primary Examiner, Art Unit 2198 4/23/2026
Prosecution Insights