CTNF 18/503,005 CTNF 90815 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This action is responsive to the communication filed 11/6/2023. Claims 1-20 are presented for examination. Examiner Notes Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Priority Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 11/6/2023 and 4/8/2024. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-4, 7-9, 11-13 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20230024350 A1, hereafter Li) in view of Elango (US 20210133591 A1) and Hu et al. (US 20230290134 A1, hereafter Hu) Regarding to claim 1 , Li discloses: An apparatus, comprising: at least one memory; and at least one processor coupled to the at least one memory, the at least one processor configured to (see [0006], [0058], [0062]-[0064]; “an example of a device configured to practice one or more embodiments. Device 600 may be, for example, configured to determine a parallel computing scheme for a neural network” and “Device 600 may be configured to perform method(s) described herein or comprises means for performing method(s) described herein. In one example, the means comprises the at least one processor 602, the at least one memory 604 including program code 606 configured to, when executed by the at least one processor 602, cause the device 600 to perform the method(s)”): receive an operator graph at a first processing block (see Figs. 5, 6, [0006], [0057]; “The device may be configured to receive a computation graph for the neural network”, “a computation graph (G) for a neural network … The computation graph may be also called an operator graph and it may comprise multiple operator nodes, or computation nodes”); receive a computing device topology at the first processing block (see Fig. 5, [0057]; “a device topology graph (D) … each of two CPUs may be connected to two GPUs. The CPUs may be further connected over a network”. Note: claimed “first processing block” and the later claimed “second processing block” are broad terms without strict definitions or differentiations, and thus any corresponding component or stage to perform corresponding step/action can be considered as such processing block(s), such as the combination of component/stage to receive computation graph, component/stage to receive device topology graph and the component/stage to generate distributed parallel scheme can be considered as claimed first processing block); execute an optimization process at the first processing block based on the computing device topology and the operating graph to determine a parallelization solution for executing the operating graph with the computing device topology (see Figs. 5, 6, [0057]-[0058]; “A distributed parallel scheme may comprise a mapping from each operator node of G to a configuration C, where each configuration C describes a parallel implementation of an operator node of G over the multiple devices of the topology D ” and “Device 600 may be, for example, configured to determine a parallel computing scheme for a neural network”); receive the parallelization solution at a second processing block (see [0013]; “This solution enables to verify the determined parallel computing scheme with respect to capabilities of the parallel computing devices”. In order to verify such determined parallel computing scheme, i.e., claimed “parallelization solution”, the system is required to perform step or action of receiving such determined parallel computing scheme). Li does not disclose: compute, at the second processing block, a bottleneck structure; compute, at the second processing block, a cost value of the parallelization solution based on the bottleneck structure; transmit the cost value from the second processing block to the first processing block; and execute the optimization process at the first processing block based on the computing device topology, the operating graph, the cost value, to determine a neighbor parallelization solution. However, Elango discloses: execute an optimization process at the first processing block; compute, at the second processing block, a cost value of the parallelization solution; transmit the cost value from the second processing block to the first processing block; and execute the optimization process at the first processing block based on [the computing device topology,] the operating graph, the cost value, to determine a neighbor parallelization solution (see [0091], [0111]; “automatically finds fast parallelization strategies. It uses a general Markov Chain Monte Carlo (MCMC) search process to explore the search space and iteratively proposes candidate strategies based on the simulated performance of previous candidates … An initial candidate from the search space needs to be provided to MCMC to begin the search process”. Also see [0035]-[0036], [0038]-[0040], [0042], [0047]; “A DNN may be represented as a computation graph G=(V, E)”, “An optimal strategy {circumflex over (ϕ)} is a parallelization strategy that has the minimum cost over all possible strategies for V, under a given cost function ”, “some embodiments focus on the relative ordering of the costs of various strategies rather than absolute costs to ascertain the best strategy”, “The cost of an efficient parallelization strategy for G”. At one of the reasonable embodiments, the system uses MCMC search process, i.e., claimed optimization process, to iteratively proposes optimal parallel strategy based on cost value of each iterative parallel strategy ). It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the generation process of parallel computation scheme from Li by including the generation process of optimal parallelization strategy using Markov Chain Monte Carlo (MCMC) search process based on cost value of candidate strategies from Elango, since it would provide a “framework that automatically finds fast parallelization strategies” (see [0091] from Elango). In addition, Hu discloses: compute, at the second processing block, a bottleneck structure (see [0024]-[0025]; “the disclosed method and system uses a neural network bottleneck architecture to enrich feature representations while maintaining or reducing computational costs versus the known networks. The disclosed bottleneck structure uses neural network blocks each with a flexible multi-kernel arrangement that also performs spatial and channel transformations with per-block spatial and/or channel fractional attention in a neural network that performs accurate and highly efficient MFAR tasks”. Also see [0039]; “to start the bottleneck structure 200 … the end of the MKB bottleneck structure 200 may include a layer 216 of channel concatenation, stacking input and output feature channels of the MKB bottleneck together along the channel dimension”); compute, at the second processing block, a cost value of the execution solution based on the bottleneck structure (see [0043], [0053]; “a bottleneck depthwise convolutional layer performs a convolution with a k×k kernel on each channel of an input feature tensor … a depthwise separable convolutional layer only has the computational cost” “in a harmonious manner with the flexible multi-kernel convolutions to establish an even lower computational cost for the bottleneck block 200 … The overall computational cost becomes ”. Also see [0024]). It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the calculation of cost for executing ML operations from the combination of Li and Elango by including cost calculation of operations based on bottleneck structure from Hu, and thus the combination of Li, Elango and Hu would disclose the missing limitations from Li, since it would provide a mechanism of using “neural network bottleneck architecture to enrich feature representations while maintaining or reducing computational costs versus the known networks” (see [0024] from Hu). Regarding to Claim 2 , the rejection of Claim 1 is incorporated and further the combination of Li, Elango and Hu discloses: in which the optimization process comprises a metaheuristic including a Markov Chain Monte Carlo simulation (see [0091] and [0111] from Elango; “Framework1 is a deep learning framework that automatically finds fast parallelization strategies. It uses a general Markov Chain Monte Carlo (MCMC) search process to explore the search space and iteratively proposes candidate strategies based on the simulated performance of previous candidates. When the search procedure is finished, the framework returns the best strategy it has discovered. As this approach is based on meta-heuristics”). Regarding to Claim 3 , the rejection of Claim 1 is incorporated and further the combination of Li, Elango and Hu discloses: in which the computing device topology comprises at least one of a multicore processor, a system-on-chip, or a network of computing devices (see Fig. 5 and [0057] from Li; “FIG. 5 also illustrates a distributed parallel device topology. For example, each of two CPUs may be connected to two GPUs. The CPUs may be further connected over a network”. A network of CPUs and GPUs, i.e., claimed computing devices. Also see [0050] from Li; “different computing devices such as, for example, CPUs (central processing unit), GPUs (graphic processing unit), or processor cores of a processing unit”. The networks of CPUs and GPUs from [0057] can also be cores of multi-core processors). Regarding to Claim 4 , the rejection of Claim 1 is incorporated and further the combination of Li, Elango and Hu discloses: in which the at least one processor is further configured to execute the operating graph by training a neural network (see [0049] and [0053] from Li; “The parallel computation scheme may be applied, for example, when training the neural network” and “In data parallelism, computing devices may process different groups of samples 210, 212, 214, for example, training data”). Regarding to Claim 7 , Claim 7 is rejected for the same reason set forth in the rejection of Claim 1 above. Regarding to Claim 8 , the rejection of Claim 7 is incorporated and further the combination of Li, Elango and Hu discloses: in which the computing device topology includes a non-fully connected topology (see Fig. 5 and [0057] from Li. According to the particular example of device topology (D) shown by Fig. 5, it is understood that the particular example of topology is a non-fully connected topology since the GPUs from the device topology are not connected to each other). Regarding to Claim 9 , Claim 9 is rejected for the same reason set forth in the rejection of Claim 4 above. Regarding to Claim 11 , Claim 11 is rejected for the same reason set forth in the rejection of Claim 1 above. Regarding to Claim 12 , the rejection of Claim 11 is incorporated and further the combination of Li, Elango and Hu discloses: in which the computing device topology includes a non-fully connected topology (see Fig. 5 and [0057] from Li. According to the particular example of device topology (D) shown by Fig. 5, it is understood that the particular example of topology is a non-fully connected topology since the GPUs from the device topology are not connected to each other). Regarding to Claim 13 , Claim 13 is rejected for the same reason set forth in the rejection of Claim 4 above. Regarding to Claim 15 , Claim 15 is a method claim corresponds to system Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above. Regarding to Claim 16 , Claim 16 is a method claim corresponds to system Claim 2 and is rejected for the same reason set forth in the rejection of Claim 2 above. Regarding to Claim 17 , Claim 17 is a method claim corresponds to system Claim 3 and is rejected for the same reason set forth in the rejection of Claim 3 above. Regarding to Claim 18 , Claim 18 is a method claim corresponds to system Claim 4 and is rejected for the same reason set forth in the rejection of Claim 4 above . 07-21-aia AIA Claim s 5, 10, 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20230024350 A1, hereafter Li) in view of Elango (US 20210133591 A1) and Hu et al. (US 20230290134 A1, hereafter Hu) and further in view of GadelRab et al. (US 20210019652 A1, hereafter GadelRab) . Regarding to Claim 5 , the rejection of Claim 1 is incorporated, the combination of Li, Elango and Hu does not disclose: in which the at least one processor is further configured to execute the operating graph by inferring with a neural network. However, GadelRab discloses: in which the at least one processor is further configured to execute the neural network task by inferring with a neural network (see [0051] and [0054]; “To optimize inference operations performed using a machine learning model while generating an initial inference from a data set within a short amount of time of receiving a request to generate inferences, embodiments described herein provide techniques for concurrently executing inferences and optimizing the operational parameters used by machine learning models to execute inferences” and “concurrently performing inferences using a machine learning model and optimizing operational parameters applied to the machine learning model, according to embodiments described herein. Operations 300 may be performed by a computing device with one or more processors (e.g., CPU, DSP, GPU, etc.) implementing a machine learning mode”). It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the parallelism of training ML model from the combination of Li, Elango and Hu by including the parallelism of inferring ML model from GadelRab, and thus the combination of Li, Elango, Hu and GadelRab would disclose the missing limitations from Li, Elango and Hu, since it would provide inferring ML model is a well-known and understood type of operation or task performed for a machine learning environment. Regarding to Claim 10 , Claim 10 is rejected for the same reason set forth in the rejection of Claim 5 above. Regarding to Claim 14 , Claim 14 is rejected for the same reason set forth in the rejection of Claim 5 above. Regarding to Claim 19 , Claim 19 is a method claim corresponds to system Claim 1 and is rejected for the same reason set forth in the rejection of Claim 5 above . 07-21-aia AIA Claim s 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20230024350 A1, hereafter Li) in view of Elango (US 20210133591 A1) and Hu et al. (US 20230290134 A1, hereafter Hu) and further in view of Zhou (CN 115035465 A-English translation provided by Google Patents-publication date: 9/9/2022) . Regarding to Claim 6 , the rejection of Claim 1 is incorporated, the combination of Li, Elango and Hu does not disclose: calculate, at the first processing block, gradient information with the bottleneck structure corresponding to the computing device topology and the parallelization solution; and bias selection of the neighbor parallelization solution, at the first processing block, based on the gradient information. However, Zhou discloses: calculate gradient information with the bottleneck structure (see [0081]; “use a plurality of bottleneck structures BTK … a cross-stage local (CSP) connection mode is introduced to optimize and calculate repeated gradient information”); and bias selection of operation solution based on the gradient information (see [0081]; “the feature fusion network CSP-PANet is used on the basis of a bottom-up and top-down fusion path of a path enhancement network PANet, a cross-stage local (CSP) connection mode is introduced to optimize and calculate repeated gradient information , and a deep separable convolution DP conv is introduced to reduce operation parameters and operation cost of the network, so that the reasoning operation speed of a network structure is improved by introducing the CSP and the DP conv to meet the real-time requirement ”. Also see [0094]-[0095], [0099]; “wherein the LightGBM is a lightweight Gradient Boosting decision tree algorithm framework, can support high-efficiency parallel training and can obtain higher accuracy” and “selecting a gradient lifting decision tree in a decision tree structure”. Gradient value or information can be used during decision tree operation to select a decision result). It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the parallelization solution selection operation from the combination of Li, Elango and Hu by including decision tree structure with gradient information from Zhou, and thus the combination of Li, Elango, Hu and Zhou would disclose the missing limitations from Li, Elango and Hu, since it would provide a mechanism to “support high-efficiency parallel training and can obtain higher accuracy” (see [0094] from Zhou). Regarding to Claim 20 , Claim 20 is a method claim corresponds to system Claim 6 and is rejected for the same reason set forth in the rejection of Claim 6 above . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Neelakanthappa (US 20170024433 A1) discloses: to reoptimize the optimized query plan can include providing instructions to a SQL optimizer to override a cost comparison for the identified suboptimal query plan (see [0038]). Wang et al. (US 20200067800 A1) discloses: generating, for the first service function chain request, a service graph including first service links between consecutive ones of the first plurality of service functions, receiving first resource information describing capabilities of first physical network resources in a physical network and a topology of the physical network, generating, dependent on the first resource information, a resource graph including first infra links between pairs of connected ones of the first physical network resources, creating, dependent on the service graph and the resource graph, a first plurality of mapping solutions for mapping the service functions specified in the first service function chain request to respective ones of the first physical network resources (see [0004]). Huang et al. (US 20250156715 A1) discloses: These bottleneck structures often have a very good tradeoff between cost and quality (see [0010]). Ben et al. (CN 114677755 A-English translation provided by Google Patents) discloses: the bottleneck structure is used to increase the network depth with the minimum computational cost (see [0007]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHI CHEN whose telephone number is (571)272-0805. The examiner can normally be reached on M-F from 9:30AM to 5:30PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y Blair can be reached on 571-270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from Patent Center and the Private Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from Patent Center or Private PAIR. Status information for unpublished applications is available through Patent Center and Private PAIR to authorized users only. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form. /Zhi Chen/ Patent Examiner, AU2196 /APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196 Application/Control Number: 18/503,005 Page 2 Art Unit: 2196 Application/Control Number: 18/503,005 Page 3 Art Unit: 2196 Application/Control Number: 18/503,005 Page 4 Art Unit: 2196 Application/Control Number: 18/503,005 Page 5 Art Unit: 2196 Application/Control Number: 18/503,005 Page 6 Art Unit: 2196 Application/Control Number: 18/503,005 Page 7 Art Unit: 2196 Application/Control Number: 18/503,005 Page 8 Art Unit: 2196 Application/Control Number: 18/503,005 Page 9 Art Unit: 2196 Application/Control Number: 18/503,005 Page 10 Art Unit: 2196 Application/Control Number: 18/503,005 Page 11 Art Unit: 2196 Application/Control Number: 18/503,005 Page 12 Art Unit: 2196 Application/Control Number: 18/503,005 Page 13 Art Unit: 2196 Application/Control Number: 18/503,005 Page 14 Art Unit: 2196
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