DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The response filed 03/24/2026 is accepted, in which, independent claims 1, 11, and 17 are amended and claim 7 is canceled. Claims 1-6 and 8-20 await an action on the merits as follows.
The objection to the specification is withdrawn in view of the amended title.
Response to Arguments
Applicant’s arguments with respect to claims 1, 11, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over Majhi (US 20230178658 A1), and further in view of Bangsaruntip (US 20140034908 A1).
Regarding claim 1, Majhi teaches an integrated circuit device (400, Fig 4A) comprising:
a fin-type active region (410) on (shown on) a substrate (402, Fig 4B);
a nanosheet (418; nanosheet, [0013]) on (shown on) a fin top surface (402T: top surface of 402) of the fin-type active region (410),
the nanosheet (418) being apart (shown apart) from the fin top surface (402T) of the fin-type active region (410) in a vertical direction (Z);
a gate line (432, Fig 4F) surrounding (shown surrounding) the nanosheet (418) on (shown on) the fin-type active region (410); and
a source/drain region (406/408, Fig 4B) on (shown on) the fin-type active region (410), the source/drain region (406/408) being in contact (shown in contact) with the nanosheet (418),
wherein the nanosheet (418) comprises a multilayered sheet (shown as multilayered sheet) comprising a first outer semiconductor sheet (421_1: layer 421 on the bottom of 418), a core semiconductor sheet (423), and a second outer semiconductor sheet (421_2: layer 421 on top of 418), wherein
the first outer semiconductor sheet (421_1), the core semiconductor sheet (423), and the second outer semiconductor sheet (421_2) are sequentially stacked (shown sequentially stacked) in the vertical direction (Z).
Majhi fails to explicitly teach the source/drain region is in direct contact with each of the first outer semiconductor sheet, the core semiconductor sheet, and the second outer semiconductor sheet.
However, Bangsaruntip teaches wherein the source/drain region is in direct contact (shown in direct contact; Fig16B shows nanowires forming channels between source/drain regions where the nanowire cores 1304 and their epitaxial sidewalls 1400, which are analogous to the claimed core and first/second outer semiconductor sheets, make direct contact with the source/drain regions 1205.) with each of the first outer semiconductor sheet, the core semiconductor sheet, and the second outer semiconductor sheet.
Majhi and Bangsaruntip are considered analogous to the claimed invention because both are from the same field of endeavor of integrated circuit devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Majhi with the features of Bangsaruntip to create a device wherein the source/drain region is in direct contact with each of the first outer semiconductor sheet, the core semiconductor sheet, and the second outer semiconductor sheet which allows the device to be smaller and more efficient by moving the source/drain regions closer together; and increase effective device width (Bangsaruntip, [0002] while mitigating short channel effects (Bangsaruntip, [0043]).
Regarding claim 2, the combination of Majhi and Bangsaruntip discloses the device of claim 1. Majhi goes on to teach each of the first outer semiconductor sheet (421_1, Fig 4B) and the second outer semiconductor sheet (421_2) comprises a doped silicon (Si) layer or an undoped Si layer (Si, [0121]), and
the core semiconductor sheet (423) comprises a doped silicon germanium (SiGe) layer or an undoped SiGe layer (SiGe, [0121]).
Regarding claim 3, the combination of Majhi and Bangsaruntip discloses the device of claim 1. Majhi goes on to teach wherein the core semiconductor sheet (423, Fig 4B) comprises a doped SiGe layer or an undoped SiGe layer (SiGe, [0121]), and
a germanium (Ge) content ratio (10%; can be as high as 100%, [0122]) of the core semiconductor sheet (423) is in a range (within the range) of more than 0 at% and 20 at% or less.
Regarding claim 4, the combination of Majhi and Bangsaruntip discloses the device of claim 1. Majhi goes on to teach wherein a thickness (hb/ht: hb is the thickness of the middle region 480, whereas ht is the thickness of the tip region 482) of the core semiconductor sheet (423, Fig 4C/D/E) in the vertical direction (Z) is about 20% to about 80% (50%; hb shown as 50% H in Fig 4C) of a thickness (H) of the nanosheet (418).
Regarding claim 5, the combination of Majhi and Bangsaruntip discloses the device of claim 1. Majhi goes on to teach wherein a thickness (hb, Fig 4D) of the core semiconductor sheet (423) is less (shown less) than a thickness (hp) of each of the first outer semiconductor sheet (421_1) and the second outer semiconductor sheet (421_2) in the vertical direction (Z).
Regarding claim 6, the combination of Majhi and Bangsaruntip discloses the device of claim 1. Majhi goes on to teach wherein a thickness (hb, Fig 4C) of the core semiconductor sheet (423) is greater (shown greater) than a thickness (hp) of each of the first outer semiconductor sheet (421_1) and the second outer semiconductor sheet (421_2) in the vertical direction (Z).
Regarding claim 7, the combination of Majhi and Bangsaruntip discloses the device of claim 1. Majhi goes on to teach wherein the source/drain region (406/408, Fig 4B) is in contact (shown in contact) with each of the first outer semiconductor sheet (421_1), the core semiconductor sheet (423), and the second outer semiconductor sheet (421_2).
Regarding claim 8, the combination of Majhi and Bangsaruntip discloses the device of claim 1. Majhi goes on to teach wherein the source/drain region (406/408, Fig 4B) comprises a SiGe layer (SiGe; Group IV semiconductors, [0040]) doped with a p-type dopant (p-type, [0083]; appropriately doped, [0040]).
Regarding claim 9, the combination of Majhi and Bangsaruntip discloses the device of claim 1. Majhi goes on to teach wherein the source/drain region (406/408, Fig 4B) comprises a Si layer (Si; group IV semiconductors, [0040]) doped with an n-type dopant (n-type, [0083]; appropriately doped, [0040]) or a silicon carbide (SiC) layer doped with an n-type dopant.
Regarding claim 10, the combination of Majhi and Bangsaruntip discloses the device of claim 1. Majhi goes on to teach further comprising
a gate dielectric film (420, Fig 4F) surrounding (shown surrounding) the nanosheet (418) on (shown on) the fin-type active region (410),
the gate dielectric film (420) being between (shown between) the nanosheet (418) and the gate line (432),
wherein the gate dielectric film (420) is apart (shown apart) from the core semiconductor sheet (423) in the vertical direction (Z).
Regarding claim 11, Majhi teaches an integrated circuit device (400, Fig 4A) comprising:
a fin-type active region (410) extending (shown extending) long in a first lateral direction (X) on (shown on) a substrate (402, Fig 4B);
a nanosheet stack (418a/b/c) apart (shown apart) from a fin top surface (402T: top of 402) of the fin-type active region (410) in a vertical direction (Z),
the nanosheet stack (418a/b/c) facing (shown facing) the fin top surface (402T) of the fin-type active region (410), and
the nanosheet stack (418a/b/c) comprising a plurality of nanosheets (418), wherein
the plurality of nanosheets (418) are at different vertical distances (shown at different heights in Z-direction) from the fin top surface (402T) of the fin-type active region (410);
a gate line (432) extending (shown extending, Fig 4A) long in a second lateral direction (Y) on (shown on) the fin-type active region (410),
the gate line (432) surrounding (shown surrounding, Fig 4F) the plurality of nanosheets (418) on (shown on) the fin-type active region (410), wherein
the second lateral direction (Y) intersects (shown intersecting) with the first lateral direction (X); and
a pair of source/drain regions (406/408, Fig 4B) respectively on both sides (shown on both sides) of the gate line (432) on (shown on) the fin-type active region (410),
each source/drain region (406/408) being in contact (shown in contact) with the plurality of nanosheets (418),
wherein each of the plurality of nanosheets (418) comprises a multilayered sheet (shown comprising a multilayered sheet) comprising a first outer semiconductor sheet (421_1: layer 421 on bottom of 418), a core semiconductor sheet (423), and a second outer semiconductor sheet (421_2: layer 421 on top of 418), which are sequentially stacked (shown sequentially stacked) in the vertical direction (Z).
Majhi fails to explicitly teach each of the pair of the source/drain region is in direct contact with each of the first outer semiconductor sheet, the core semiconductor sheet, and the second outer semiconductor sheet of the plurality of nanosheets.
However, Bangsaruntip teaches wherein each of the pair of the source/drain region is in direct contact (shown in direct contact; Fig16B shows nanowires forming channels between source/drain regions where the nanowire cores 1304 and their epitaxial sidewalls 1400, which are analogous to the claimed core and first/second outer semiconductor sheets, make direct contact with the source/drain regions 1205.) with each of the first outer semiconductor sheet, the core semiconductor sheet, and the second outer semiconductor sheet of the plurality of nanosheets.
Majhi and Bangsaruntip are considered analogous to the claimed invention because both are from the same field of endeavor of integrated circuit devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Majhi with the features of Bangsaruntip to create a device wherein each of the pair of the source/drain region is in direct contact with each of the first outer semiconductor sheet, the core semiconductor sheet, and the second outer semiconductor sheet of the plurality of nanosheets which allows the device to be smaller and more efficient by moving the source/drain regions closer together; and increase effective device width (Bangsaruntip, [0002] while mitigating short channel effects (Bangsaruntip, [0043]).
Regarding claim 12, the combination of Majhi and Bangsaruntip discloses the device of claim 11. Majhi goes on to teach wherein, in each of the plurality of nanosheets (418, Fig 4B),
each of the first outer semiconductor sheet (421_1) and the second outer semiconductor sheet (421_2) comprises a doped silicon (Si) layer or an undoped Si layer (Si, [0121]), and
the core semiconductor sheet (423) comprises a doped silicon germanium (SiGe) layer or an undoped SiGe layer (SiGe, [0121]).
Regarding claim 13, the combination of Majhi and Bangsaruntip discloses the device of claim 11. Majhi goes on to teach wherein, in each of the plurality of nanosheets (418, Fig 4B),
the core semiconductor sheet (423) comprises a SiGe layer (SiGe, [0121]), and
a germanium (Ge) content ratio (10%; can be as high as 100%, [0122]) of the core semiconductor sheet (423) is in a range (within the range) of more than 0 atomic percent (at%) and 20 at% or less.
Regarding claim 14, the combination of Majhi and Bangsaruntip discloses the device of claim 11. Majhi goes on to teach wherein a thickness (hb/ht: hb is the thickness of the middle region 480, whereas ht is the thickness of the tip region 482) of the core semiconductor sheet (423, Fig 4C/D/E) in the vertical direction (Z) is about 20% to about 80% (50%; hb shown as 50% H in Fig 4C) of a thickness (H) of the plurality of nanosheets (418).
Regarding claim 15, the combination of Majhi and Bangsaruntip discloses the device of claim 11. Majhi goes on to teach wherein the pair source/drain region (406/408, Fig 4B) comprises a SiGe layer (SiGe; Group IV semiconductors, [0040]) doped with a p-type dopant (p-type, [0083]; appropriately doped, [0040]).
Regarding claim 16, the combination of Majhi and Bangsaruntip discloses the device of claim 11. Majhi goes on to teach wherein the pair source/drain region (406/408, Fig 4B) comprises a Si layer (Si; group IV semiconductors, [0040]) doped with an n-type dopant (n-type, [0083]; appropriately doped, [0040]) or a silicon carbide (SiC) layer doped with an n-type dopant.
Regarding claim 17, Majhi teaches an integrated circuit device (400, Fig 4A) comprising:
a first transistor (PMOS, [0068]) in a first region (first area, [0068]) of a substrate (402) and
a second transistor (NMOS, [0068]) in a second region (second area, [0068]) of the substrate (402),
wherein the first transistor (PMOS; the basic structure of both transistors would resemble Fig 4) comprises:
a first fin-type active region (410P: 410 in first area for PMOS transistor) on (shown on) the substrate (402);
a first nanosheet stack (418a/b/c_P: 418 stack in first area for PMOS, Fig 4B) on (shown on) the first fin-type active region (410P),
the first nanosheet stack (418a/b/c_P) comprising a first-type nanosheet (418P: 418 in first area for PMOS), the first-type nanosheet (418P) comprising a multilayered sheet (shown as multilayered sheet) comprising a first outer semiconductor sheet (421P_1: layer 421 on bottom of 418P), a core semiconductor sheet (423P: 423 in first area for PMOS), and a second outer semiconductor sheet (421P_2: 421 on top of 418P), wherein
the first outer semiconductor sheet (421P_1), the core semiconductor sheet (423P), and the second outer semiconductor sheet (421P_2) are sequentially stacked (shown sequentially stacked) in a vertical direction (Z);
a first gate line (432P: 432 in first area for PMOS) surrounding (shown surrounding, Fig 4F) the first-type nanosheet (418P) on (shown on) the first fin-type active region (410P); and
a pair of first source/drain regions (406/408P: 406/408 in first area for PMOS) on (shown on) the first fin-type active region (410P),
the pair of first source/drain regions (406/408P) being in contact (shown in contact) with the first-type nanosheet (418P),
wherein the second transistor (NMOS; the basic structure of both transistors would resemble Fig 4) comprises:
a second fin-type active region (410N: 410 in second area for NMOS) on (shown on) the substrate (402);
a second nanosheet stack (418a/b/c_N: 418 stack in second area for NMOS) on (shown on) the second fin-type active region (410N), the second nanosheet stack (418a/b/c_N) comprising a second-type nanosheet (418N: 418 in second area for NMOS) having a different structure (different; peripheral structures are different for the two transistors as seen in Table I) from the first-type nanosheet (418P);
a second gate line (432N: 432 in second area for NMOS) surrounding (shown surrounding, Fig 4F) the second-type nanosheet (418N) on (shown on) the second fin-type active region (410N); and
a pair of second source/drain regions (406/408N: 406/408 in second area for NMOS) on (shown on) the second fin-type active region (410N),
the pair of second source/drain regions (406/408N) being in contact (shown in contact) with the second-type nanosheet (418N).
Majhi fails to explicitly teach each of the pair of the source/drain region is in direct contact with each of the first outer semiconductor sheet, the core semiconductor sheet, and the second outer semiconductor sheet.
However, Bangsaruntip teaches wherein each of the pair of the source/drain region is in direct contact (shown in direct contact; Fig16B shows nanowires forming channels between source/drain regions where the nanowire cores 1304 and their epitaxial sidewalls 1400, which are analogous to the claimed core and first/second outer semiconductor sheets, make direct contact with the source/drain regions 1205.) with each of the first outer semiconductor sheet, the core semiconductor sheet, and the second outer semiconductor sheet.
Majhi and Bangsaruntip are considered analogous to the claimed invention because both are from the same field of endeavor of integrated circuit devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Majhi with the features of Bangsaruntip to create a device wherein each of the pair of the source/drain region is in direct contact with each of the first outer semiconductor sheet, the core semiconductor sheet, and the second outer semiconductor sheet which allows the device to be smaller and more efficient by moving the source/drain regions closer together; and increase effective device width (Bangsaruntip, [0002] while mitigating short channel effects (Bangsaruntip, [0043]).
Regarding claim 18, the combination of Majhi and Bangsaruntip discloses the device of claim 17. Majhi goes on to teach wherein, in the first-type nanosheet (418P, Fig 4B),
each of the first-type nanosheet (418P), the first outer semiconductor sheet (421P_1), and the second outer semiconductor sheet (421P_2) comprises a doped silicon (Si) layer or an undoped Si layer (SI, [0121]), and
the core semiconductor sheet (423P) comprises a doped silicon germanium (SiGe) layer or an undoped SiGe layer (SiGe, [0121]), and
the second-type nanosheet (418N) comprises a single sheet (the core structure can be Si, [0123]; Table 1 does not limit the scope, [0124]; the peripheral structure for the NMOS is comprised of Si, [0121]; the core and the peripheral are both Si, therefore, 418N is a single sheet of Si; NMOS may not have any separate peripheral structure, [0120]) that comprises a doped Si layer or an undoped Si layer (Si) and does not comprise a SiGe layer (does not contain SiGe, as discussed above).
Regarding claim 19, the combination of Majhi and Bangsaruntip discloses the device of claim 17. Majhi goes on to teach wherein
the first-type nanosheet (418P, Fig 4B) comprises a multilayered sheet (shown as a multilayered sheet) comprising a first Si layer (421P_1: 421 on bottom of 418 in first area for PMOS), a first SiGe layer (423P: 423 in first area for PMOS), and a second Si layer (421P_2: 421 on top of 418 in first area for PMOS), wherein
the first Si layer (421P_1), the first SiGe layer (423P), and the second Si layer (421P_2) are sequentially stacked (shown sequentially stacked) in the vertical direction (Z),
the second-type nanosheet (418N) comprises a multilayered sheet (shown as multilayered sheet) comprising a third Si layer (421N_1: 421 on bottom of 418 in second area for NMOS), a second SiGe layer (423N: 423 in second area for NMOS), and a fourth Si layer (421N_2: 421 on top of 418 in second area for NMOS), wherein
the third Si layer (421N_1), the second SiGe layer (423N), and the fourth Si layer (421N_2) are sequentially stacked (shown sequentially stacked) in the vertical direction (Z), and
a germanium (Ge) content ratio (10%; can be as high as 100%, [0122]) of the first SiGe layer (423P) is different (different; numerous channel material configurations and variations are possible, [0069]) from a Ge content ratio (15%; can be as high as 100%, [0122]) of the second SiGe layer (423N).
Regarding claim 20, the combination of Majhi and Bangsaruntip discloses the device of claim 17. Majhi goes on to teach wherein
the first-type nanosheet (418P, Fig 4B) comprises a multilayered sheet (shown as multilayered sheet) comprising a first Si layer (421P_1: 421 on bottom of 418P), a first SiGe layer (423P: 423 of 418P), and a second Si layer (421P_2: 421 on top of 418P), wherein
the first Si layer (421P_1), the first SiGe layer (423P), and the second Si layer (421P_2) are sequentially stacked (shown sequentially stacked) in the vertical direction (Z),
the second-type nanosheet (418N) comprises a multilayered sheet (shown as multilayered sheet) comprising a third Si layer (421N_1: 421 on bottom of 418N), a second SiGe layer (423N: 423 of 418N), and a fourth Si layer (421N_2: 421 on top of 418N), wherein
the third Si layer (421N_1), the second SiGe layer (423N), and the fourth Si layer (421N_2) are sequentially stacked (shown sequentially stacked) in the vertical direction (Z), and
a thickness (hbP: hb of 423P, Fig 4C) of the first SiGe layer (423P) is different (shown different) from a thickness (hbN: hb of 423N, Fig 4E) of the second SiGe layer (423N).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Qin (US 20240170538 A1) - SiGe nanosheet core with Si shell layers
More (US 20200119167 A1) - SiGe/Si nanosheet stack with diffusion gradient layers between them
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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