Prosecution Insights
Last updated: April 19, 2026
Application No. 18/503,044

POWER CONVERTER FOR A DATA CABLE

Non-Final OA §102§103
Filed
Nov 06, 2023
Examiner
KESSIE, DANIEL
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tetra Semiconductors AG
OA Round
1 (Non-Final)
61%
Grant Probability
Moderate
1-2
OA Rounds
3y 1m
To Grant
86%
With Interview

Examiner Intelligence

Grants 61% of resolved cases
61%
Career Allow Rate
418 granted / 685 resolved
-7.0% vs TC avg
Strong +25% interview lift
Without
With
+25.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
75 currently pending
Career history
760
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
53.2%
+13.2% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
17.2%
-22.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 685 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 6, 8, 9, 11, 12, 13, 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Roy et al. (US 2020/0159307) Re Claim 1; Roy discloses A power converter for a data cable: discloses an "intermediary device (ID) 100" (Fig. 1, 18 etc.) which is a power converter that is "inserted on a data connection between the PSE and the PD" (0006). an input for establishing an electrical connection with electrical power wires of the data cable: The ID 100 includes an "input port 102" (0054) for "plugging a data connection cable 105 from the PSE 22 into the input port 102" (0056). The data connection cable carries power over "electrical power wires" (0023). an output: The ID 100 includes an "output port 104" (0054) for "plugging a data connection cable 107 from the PD 24 into the output port 104" (0056). a converter section configured to: receive electrical power having an input voltage from the electrical power wires, and use an inductance of the electrical power wires for converting the electrical power having the input voltage into electrical power having an output voltage: Roy describes the ID as consuming a "particular amount of power supplied by the PSE over the data connection" (0007). It also discloses an "Isolated Buck-Converter 1804" (0045) and an "Isolated Boost-Converter 1814" (0045) that are part of the power management within the device. Additionally, Roy mentions "magnetics 2002" which "decouple the data from the input electrical power" and provides a connection with "electrical power" (0024). The magnetics provide the necessary inductance. The PSE interface includes a "buck-converter for reducing a voltage of the input electrical power from a rail level voltage to provide intermediary electrical power with a digital logic voltage level suitable for use by the processor" (0023). This describes the conversion of power. and to transmit the electrical power having the output voltage to the output: The "PD interface 46 acts like a PSE by supplying unused power to the actual PD 24 via the output port 104" (0056, 62). Re Claim 2: Roy discloses wherein the output voltage is larger than the input voltage. wherein the output voltage is larger than the input voltage: Roy discloses an "Isolated Boost-Converter 1814" (0045). A boost converter is a type of power converter that steps up, or boosts, the input voltage to a higher output voltage. Re Claim 3: Roy discloses wherein the converter section includes switches for short-circuiting the electrical power wires during a first period of time, and for connecting the electrical power wires to the output during a second period of time: Roy discloses a boost converter (0045). The operation described in the claim is the fundamental operating principle of a boost converter circuit, which uses a switch to periodically connect the input voltage source to an inductor (in this case, the inductance of the wires) and then disconnect it, transferring the energy stored in the inductor to the output at a higher voltage. This is implicit in the disclosure of a boost converter. Re Claim 4: Roy discloses further including a control circuit for controlling the switches: Roy discloses an "ID processor 44" that "manages operation of the intermediary device 100" (0063). This processor coordinates the "power management described herein" and is implemented with processing circuitry (0063). The ID processor 44 inherently functions as a control circuit for the switching operations of the converter. Re Claim 6: Roy discloses further comprising a voltage regulator which is configured to receive electrical power having the output voltage from the output and to transmit electrical power having a second output voltage, wherein in particular the second output voltage is smaller than the output voltage: Roy discloses a "power management circuit 122" as part of the "ID processor 44" (0084). This circuit "may convert the received voltage into different values to power multiple components" (0084). This function is that of a voltage regulator, and the converted voltages to power digital logic components are typically lower than the input voltage. Re Claim 8: Roy discloses wherein the converter section and the voltage regulator are arranged on an integrated circuit: Roy states that the ID processor 44, which contains the power management circuit 122 (the voltage regulator), "is be implemented as...an application specific integrated circuit (ASIC)" (0063). It also mentions that the PSE interface processor may be "part of the ID processor 44" (0081). This shows that integrating the functions of the converter and regulator onto a single chip is a contemplated embodiment. Re Claim 9: A data cable comprising: a power converter comprising: an input for establishing an electrical connection with electrical power wires of the data cable, an output, and a converter section configured to: receive electrical power having an input voltage from the electrical power wires, and use an inductance of the electrical power wires for converting the electrical power having the input voltage into electrical power having an output voltage, and to transmit the electrical power having the output voltage to the output. A data cable comprising: a power converter: Roy states that "one or both of the data connection cable 105 and data connection cable 107 may be integrated with the intermediary device 100" (0057). It further explains that "the physical connectivity of the output port 104 may be absent, with the data connection cable of a particular (e.g., short) length projecting directly from the intermediary device 100's body" (0057). This explicitly discloses a data cable with an integrated power converter. The other elements of the claim are described in the analysis for claim 1. Re Claim 11: Roy discloses wherein the output voltage is larger than the input voltage: Roy discloses an "Isolated Boost-Converter 1814" (0045), which boosts the input voltage to a higher output voltage. Re Claim 12: Roy discloses wherein the converter section includes switches for short-circuiting the electrical power wires during a first period of time, and for connecting the electrical power wires to the output during a second period of time: As explained in the analysis of claim 3, this is the inherent and well-known operating principle of a boost converter, which is disclosed in Roy (0045). Re Claim 13: Roy discloses further including a control circuit for controlling the switches: Roy discloses the "ID processor 44" (0063), which manages the operation and power management of the device, serving as the control circuit. Re Claim 15: Roy discloses further comprising a voltage regulator which is configured to receive electrical power having the output voltage from the output and to transmit electrical power having a second output voltage, wherein in particular the second output voltage is smaller than the output voltage: Roy discloses a "power management circuit 122" as part of the "ID processor 44" (0084) that "convert(s) the received voltage into different values" (0084). This functions as a voltage regulator, providing a lower voltage for internal components. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5, 7, 10 14, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Roy. Claim 5: The power converter according to claim 1, further including a storage for electrical energy which is connected with the output, in particular a capacitor. The power converter according to claim 1, further including a storage for electrical energy which is connected with the output, in particular a capacitor: Roy discloses a "power supply 128" within the "PD interface 46" (0085). The PD interface is the output stage of the device that supplies power to the PD (0062). It is well-known in the art that power supplies and converters require energy storage devices like capacitors to stabilize the voltage output. Claim 7: The power converter according to claim 6, further including a storage for electrical energy which is connected with the second output, in particular a second capacitor. The power converter according to claim 6, further including a storage for electrical energy which is connected with the second output, in particular a second capacitor: This claim describes a capacitor at the output of the voltage regulator. As described for claim 5, the use of capacitors for voltage stabilization is a fundamental aspect of electronic circuit design, and this would be a necessary component for the power management circuit 122 described in Roy. Claim 10: The data cable according to claim 9 having the form of a multimedia cable according to a HDMI standard. The data cable according to claim 9 having the form of a multimedia cable according to a HDMI standard: Roy states that "PoE is only an example" and that the intermediary device "may operate in any application in which power is supplied over a data connection" (0058). This broad teaching would make it obvious to a person having ordinary skill in the art to apply the disclosed technology to other data cables, such as an HDMI cable. Re Claim 14: Roy discloses further including a storage for electrical energy which is connected with the output, in particular a capacitor: Roy discloses a "power supply 128" within the PD interface 46 (0085), which is the output stage of the device. A capacitor for voltage stability is a standard component of such a power supply. Re Claim 16: Roy discloses further including a storage for electrical energy which is connected with the second output, in particular a second capacitor: This describes a capacitor at the output of the voltage regulator. This is a fundamental component for a voltage regulator, and its use is implied by the disclosure of the power management circuit 122. Claim 17: The data cable according to claim 15, wherein the converter section and the voltage regulator are arranged on an integrated circuit. The data cable according to claim 15, wherein the converter section and the voltage regulator are arranged on an integrated circuit: Roy describes the ID processor 44 (containing the voltage regulator) as being able to be implemented as an "ASIC" (0063). It also discusses the possibility of other components being "part of the ID processor" (0081). This makes the arrangement of the converter section and the voltage regulator on a single integrated circuit an obvious design choice. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL KESSIE whose telephone number is (571)272-4449. The examiner can normally be reached Monday-Friday 8am-5pmEst. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rexford Barnie can be reached at (571) 272-7492. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL KESSIE/Primary Examiner, Art Unit 2836
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Prosecution Timeline

Nov 06, 2023
Application Filed
Oct 16, 2025
Non-Final Rejection — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
61%
Grant Probability
86%
With Interview (+25.0%)
3y 1m
Median Time to Grant
Low
PTA Risk
Based on 685 resolved cases by this examiner. Grant probability derived from career allow rate.

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