DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1- 3 and 6-10 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Tanimura (JP 2000168060, machine translation attached) . Regarding claim 1, Tanimura teaches a resistance structure (“chip resistor” see at least the Abstract and fig. 2), comprising: a substrate (alumina substrate 1); and a metal layer ( comprise d of metal layer 2, 3 and 4 ) provided on the substrate, wherein the metal layer comprises a first metal region (solid line region directly above the second metal region and directly below the protection layer 5; see the reproduced fig. 2) the and a second metal region (comprises of the dashed line) , and the first metal region is provided in a non-electrode region on the second metal region (does not contact the electrodes 8,9) ; wherein the metal layer is provided with a first insulating layer (51) and an electrode layer (at least electrodes 8,9) , the first insulating layer (5) is configured to cover the non-electrode region, and the electrode layer i s provided in an electrode region on the second metal region (electrodes 6/8 and 7/9 in fig. 2) . Regarding claim 2, Tanimura teaches the resistance structure of claim 1, wherein: the electrode layer comprises a first racking plating metal layer (electrodes 6/8) and a second racking plating metal layer (7/9); the electrode region comprises a first electrode region (left side electrode) and a second electrode region (right side electrode) respectively provided at two ends of an upper surface of the second metal region; and the first racking plating metal layer is provided in the first electrode region, and the second racking plating metal layer is provided in the second electrode region. Regarding claim 3 , Tanimura teaches t he resistance structure of claim 2, wherein a thickness of the electrode layer is greater than a sum of a thickness of the first metal region and a thickness of the first insulating layer ( Tanimura lifts the chip resistor by having the height of the electrodes higher than the insulation layer to allow cooling of the chip resistor. See paragraph 0006-000 9, 2 nd and 3 rd page of the translation.) . Regarding claim s 6 -8 , Tanimur a teach es two -three layers of protective film (see step “S25” in page 6) on the resistor 4, wherein the protective layer (51) is composed of Al2O3, SiO2, SiN or the like and protective layer (52) is composed of epoxy-resin (5 th page of the translation). Regarding claim s 9 and 10 , Tanimura teaches a method for manufacturing the resistance structure of claim 1, comprising: obtaining a substrate (1) ; arranging a metal layer ( 2, 3 and 4) on the substrate, and etching the metal layer to obtain a convex metal layer (Etching is performed to form “the resistor into a desired shape”. 1 st paragraph in page 5. Note: the “convex” shape of Tanimura is similar to the shape of the current invention.) ; arranging a first insulating layer (5) on a non-electrode region of the convex metal layer; and racking and plating an electrode layer in an electrode region of the convex metal layer (electrodes 6 /8 and 7 /9 to the both ends of the metal layer); and after the racking and plating the electrode layer in the electrode region of the convex metal layer, further comprising: testing a current resistance value of the resistance structure through the racking plating electrode layer (resistance is adjusted by laser trimming [S24; middle of 6 th page] ) ; in response to that the current resistance value does not meet a requirement of a preset resistance value, adjusting the metal layer; and arranging a second insulating layer on the adjusted metal layer (a second and/or third protective film is applied [S25]) . Claims 1-4 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Urano (US Pat. 7,782,174) . Regarding claim 1 , Urano teaches a resistance structure (chip resistor 1; see at least fig. 1 and col. 3, line 66) , comprising: a substrate (ceramic substrate 2) ; and a metal layer (5) provided on the substrate, wherein the metal layer comprises a first metal region (region attached to the substrate ; solid line, see the reproduced fig. 1 ) and a second metal region (region attached to the protection layer 7 ; dashed line ) , and the first metal region is provided in a non-electrode region on the second metal region (non-electrode region is a region between the electrodes 6 and 6, and the first region does not come in direct contact with the electrode 6) ; wherein the metal layer is provided with a first insulating layer (7) and an electrode layer (6) , the first insulating layer is configured to cover the non-electrode region, and the electrode layer is provided in an electrode region on the second metal region (plating region [layers 10-13] being the electrode region) . Regarding claim 2 , Urano teaches t he resistance structure of claim 1, wherein: the electrode layer comprises a first racking plating metal layer (left side of the chip 1) and a second racking plating metal layer (right side) ; the electrode region comprises a first electrode region and a second electrode region respectively provided at two ends of an upper surface of the second metal region; and the first racking plating metal layer (layers 10-13) is provided in the first electrode region (left side) , and the second racking plating metal layer (also layers 10-13) is provided in the second electrode region. Regarding claim 3 , Urano teaches t he resistance structure of claim 2, wherein a thickness of the electrode layer is greater than a sum of a thickness of the first metal region and a thickness of the first insulating layer (Urano teaches the electrode layer having a greater height than that of the resistance layer and the protective layer together to prevent “inclined mounting” of the chip resistor. Thus, preventing failure. See col. 2, lines 10-29) . Regarding claim 4 , Urano teaches t he resistance structure of claim 3, wherein the first racking plating metal layer and the second racking plating metal layer both comprise: a copper layer ( copper plating layer 11; see col. 4, lines 55-60) with a first preset thickness; a nickel layer (nickel plating layer 12) with a second preset thickness provided on the copper layer (11) ; and a tin layer (tin-plating layer 13) with a third preset thickness provided on the nickel layer (12) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Urano in view of Wuyan et al. (CN 109036749, machine translation attached). Regarding claim 5 , Urano teaches the claimed invention except for a contact layer being provided on the substrate, wherein the metal layer is provided on the contact layer. Wuyan teaches a chip resistor device (see fig. 1), wherein a contact layer (2; see bottom of 7 th page) is used between the substrate 1 and the resistive layer 3 for the purpose of firmly attaching the resistive layer to the substrate. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to combine the teachings of Wuyan with Urano, since the use of a contact layer taught by Wuyan improved the physical structure for the chip device of Urano. 6. The resistance structure of claim 1, wherein a second insulating layer is provided on the first insulating layer. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Akhtman et al. teaches a flip chip having electrodes having a greater thickness of the protective layer to improve surface mounting. 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