DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanimura.
Regarding claim 1, Tanimura teaches a resistance structure ("chip resistor" see at least the Abstract and fig. 2), comprising: a substrate (alumina substrate 1); and a metal layer (comprised of metal layer 2, 3 and 4) provided on the substrate, wherein the metal layer comprises a first metal region (solid line region directly above the second metal region and directly below the protection layer 5; see the reproduced fig. 2) the and a second metal region (comprises of the dashed line), and the first metal region is provided in a non- electrode region on the second metal region (does not contact the electrodes 8,9); wherein the metal layer is provided with a first insulating layer (51) and an electrode layer (at least electrodes 8,9), the first insulating layer (5) is configured to cover the non- electrode region, and the electrode layer is provided in an electrode region on the second metal region (electrodes 6/8 and 7/9 in fig. 2).
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Regarding claim 2, Tanimura teaches the resistance structure of claim 1, wherein: the electrode layer comprises a first racking plating metal layer (electrodes 6/8) and a second racking plating metal layer (7/9); the electrode region comprises a first electrode region (left side electrode) and a second electrode region (right side electrode) respectively provided at two ends of an upper surface of the second metal region; and the first racking plating metal layer is provided in the first electrode region, and the second racking plating metal layer is provided in the second electrode region.
Regarding claim 3, Tanimura teaches the resistance structure of claim 2, wherein a thickness of the electrode layer is greater than a sum of a thickness of the first metal region and a thickness of the first insulating layer (Tanimura lifts the chip resistor by having the height of the electrodes higher than the insulation layer to allow cooling of the chip resistor. See paragraph 0006-0009, 2ⁿᵈ and 3ʳᵈ page of the translation.).
Regarding claims 6-8, Tanimura teaches two-three layers of protective film (see step "S25" in page 6) on the resistor 4, wherein the protective layer (51) is composed of A1203, SiO2, SiN or the like and protective layer (52) is composed of epoxy-resin (5th page of the translation).
Regarding claims 9 and 10, Tanimura teaches a method for manufacturing the resistance structure of claim 1, comprising: obtaining a substrate (1); arranging a metal layer (2, 3 and 4) on the substrate, and etching the metal layer to obtain a convex metal layer (Etching is performed to form "the resistor into a desired shape". 1st paragraph in page 5. Note: the "convex" shape of Tanimura is similar to the shape of the current invention.);
arranging a first insulating layer (5) on a non-electrode region of the convex metal layer; and racking and plating an electrode layer in an electrode region of the convex metal layer (electrodes 6/8 and 7/9 to the both ends of the metal layer); and
after the racking and plating the electrode layer in the electrode region of the convex metal layer, further comprising: testing a current resistance value of the resistance structure through the racking plating
testing a current resistance value of the resistance structure through the racking plating electrode layer (resistance is adjusted by laser trimming [S24; middle of 6th page]);
in response to that the current resistance value does not meet a requirement of a preset resistance value, adjusting the metal layer; and
arranging a second insulating layer on the adjusted metal layer (a second and/or third protective film is applied [S25]).
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Urano.
Regarding claim 1, Urano teaches a resistance structure (chip resistor 1; see at least fig. 1 and col. 3, line 66), comprising:
a substrate (ceramic substrate 2); and
a metal layer (5) provided on the substrate, wherein the metal layer comprises a first metal region (region attached to the substrate; solid line, see the reproduced fig. 1) and a second metal region (region attached to the protection layer 7; dashed line), and the first metal region is provided in a non-electrode region on the second metal region (non-electrode region is a region between the electrodes 6 and 6, and the first region does not come in direct contact with the electrode 6);
wherein the metal layer is provided with a first insulating layer (7) and an electrode layer (6), the first insulating layer is configured to cover the non-electrode region, and the electrode layer is provided in an electrode region on the second metal region (plating region [layers 10-13] being the electrode region).
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Regarding claim 2, Urano teaches the resistance structure of claim 1, wherein:
the electrode layer comprises a first racking plating metal layer (left side of the chip 1) and a second racking plating metal layer (right side); the electrode region comprises a first electrode region and a second electrode region respectively provided at two ends of an upper surface of the second metal region; and the first racking plating metal layer (layers 10-13) is provided in the first electrode region (left side), and the second racking plating metal layer (also layers 10-13) is provided in the second electrode region.
Regarding claim 3, Urano teaches the resistance structure of claim 2, wherein a thickness of the electrode layer is greater than a sum of a thickness of the first metal region and a thickness of the first insulating layer (Urano teaches the electrode layer having a greater height than that of the resistance layer and the protective layer together to prevent "inclined mounting" of the chip resistor. Thus, preventing failure. See col. 2, lines 10-29).
Regarding claim 4, Urano teaches the resistance structure of claim 3, wherein the first racking plating metal layer and the second racking plating metal layer both comprise:
a copper layer (copper plating layer 11; see col. 4, lines 55-60) with a first preset thickness;
a nickel layer (nickel plating layer 12) with a second preset thickness provided on the copper layer (11); and
a tin layer (tin-plating layer 13) with a third preset thickness provided on the nickel layer (12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Urano in view of Wuyan.
Regarding claim 5, Urano teaches the claimed invention except for a contact layer being provided on the substrate, wherein the metal layer is provided on the contact layer.
Wuyan teaches a chip resistor device (see fig. 1), wherein a contact layer (2; see bottom of 7th page) is used between the substrate 1 and the resistive layer 3 for the purpose of firmly attaching the resistive layer to the substrate.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to combine the teachings of Wuyan with Urano, since the use of a contact layer taught by Wuyan improved the physical structure for the chip device of Urano.
Response to Arguments
Applicant's arguments filed May 21, 2026 have been fully considered but they are not persuasive.
Regarding Applicant’s arguments to Tanimura:
Applicant argues that “the first top surface electrode 2 and the second top electrode 3 are electrode layers and thus cannot be deemed equivalent to the second metal region.” That, “The resistance value of the resistance structure in the present application is determined by both the first metal region and the second metal region, whereas only the resistor body affects the resistance value in Tanimura.”
Applicant further argues that Tanimura teaches “physically separate layers…not a single metal layer whose regions are integrated to form a convex structure.”
First, in claim 1, even as amended does not limit resistance or resistivity for the metal layer, be it the first metal region and/or the second metal region. Claim 1, as currently stands, only claims a metal layer being provided on the substrate.
Second, Tanimura teaches the “top hat” shaped metal layer (equating to the “convex” shape shown in fig. 1 of the current invention and meeting the claimed limitation) comprising of the first metal region (the layer directly under the layer 51), and the second metal region comprising of the horizontal layer extending from one end to the other on the substrate 1. The regions providing resistivity (having resistance).
Third, claim 1 further does not limit the metal layer being a “single” non-separated layer(s) or that the metal layer is formed from a single metal. That is, claim 1 does not limit the metal layer being formed from a single solid piece, that the integrated may be from multiple pieces which form a single piece layered thereon or have differing shapes and/or sizes.
Regarding Applicant’s arguments to Urano:
Applicant argues that the “protective layer 7 does not contribute to any resistance value…” Applicant further argues “the resistive element 5 cannot be simultaneously equal to both the first metal region and the second metal region of the present application (since the first metal region and the second metal region in the present application together form a convex shape.)”
First, the protective layer 7 was not used in the office action as a metal layer. The reference number 7 (which happens to be for an insulation layer) was used as a guide to the precise location of the metal layer (pointing to the first region and/or the second region). That is, the first metal region is the upper portion of the resistor 5 (the “top hat” shape which equates to the convex shape shown in fig. 1 of the current invention) and the second metal region being the lower portion of the metal layer (the resistor 5). And, as correctly stated by the Applicant, the layer 5 is resistive.
Second, in claim 1, even as amended does not limit the metal layer being formed from a single solid piece, that the integrated may be from multiple pieces which form a single piece layered thereon or have differing shapes and/or sizes.
Regarding Applicant’s arguments to Wu (prior art is Wuyan):
Applicant argues the same for Wuyan as with Tanimura and Urano for claim 1. However, Wuyan is a secondary reference used to reject dependent claim 5 for the contact layer, and therefore, does not apply to Applicant’s arguments for claim 1. See the claim 5 rejection below.
With the discussion above, the examiner believes all of Applicant’s concerns were address. Specifically, regarding the limitation of “a first metal region and a second metal region integrated with the first metal region to form a convex structure, and the first metal region is provided in a non-electrode region on the second metal region.” which are clearly taught by Tanimura and Urano.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYUNG S LEE whose telephone number is (571)272-1994. The examiner can normally be reached 7AM-3PM M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Luebke can be reached at 571-272-2009. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYUNG S LEE/Primary Examiner, Art Unit 2831
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