DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4-5, 7-8, 16-17, and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 4, the limitation "each of a third bottom FET in the third CFET structure and a fourth bottom FET in the fourth CFET structure is removed” enders the claim indefinite and unclear because it is not clear what is being claimed and what is the metes and bounds of the claim. By removal it suggests that “a third bottom FET in the third CFET structure and a fourth bottom FET in the fourth CFET structure” need to be present but claim 4 itself and claim 1 or 3 on which claim 4 depends do not suggests that and this create ambiguity.
Regarding claim 5, the limitation "each of a third bottom FET in the third CFET structure and a fourth bottom FET in the fourth CFET structure is incomplete and/or non-functional” enders the claim indefinite and unclear because it is not clear whether “a third bottom FET in the third CFET structure and a fourth bottom FET in the fourth CFET structure” recited in claim 5 is the same or different from “a third bottom FET in the third CFET structure and a fourth bottom FET in the fourth CFET structure” recited in claim 4.
Regarding claim 7, the limitation "each of a third top FET in the third CFET structure and a fourth top FET in the fourth CFET structure is removed” enders the claim indefinite and unclear because it is not clear what is being claimed and what is the metes and bounds of the claim. By removal it suggests that “each of a third top FET in the third CFET structure and a fourth top FET in the fourth CFET structure” need to be present but claim 7 itself and claim 1 or 6 on which claim 7 depends do not suggests that and this create ambiguity.
Regarding claim 8, the limitation "each of a third top FET in the third CFET structure and a fourth top FET in the fourth CFET structure is incomplete and/or non-functional” enders the claim indefinite and unclear because it is not clear whether “a third top FET in the third CFET structure and a fourth top FET in the fourth CFET structure” recited in claim 8 is the same or different from “a third top FET in the third CFET structure and a fourth top FET in the fourth CFET structure” recited in claim 7.
Regarding claim 16, the limitation " removing each of a third bottom FET in the third CFET structure and a fourth bottom FET in the fourth CFET structure” enders the claim indefinite and unclear because it is not clear what is being claimed and what is the metes and bounds of the claim. By removal it suggests that “a third bottom FET in the third CFET structure and a fourth bottom FET in the fourth CFET structure” need to be present but claim 16 itself and claim 13 or 15 on which claim 16 depends do not suggests that and this create ambiguity.
Regarding claim 17, the limitation "each of a third bottom FET in the third CFET structure and a fourth bottom FET in the fourth CFET structure is incomplete and/or non-functional” enders the claim indefinite and unclear because it is not clear whether “a third bottom FET in the third CFET structure and a fourth bottom FET in the fourth CFET structure” recited in claim 17 is the same or different from “a third bottom FET in the third CFET structure and a fourth bottom FET in the fourth CFET structure” recited in claim 16.
Regarding claim 19, the limitation " removing each of a third top FET in the third CFET structure and a fourth top FET in the fourth CFET structure” enders the claim indefinite and unclear because it is not clear what is being claimed and what is the metes and bounds of the claim. By removal it suggests that “each of a third top FET in the third CFET structure and a fourth top FET in the fourth CFET structure” need to be present but claim 19 itself and claim 13 or 18 on which claim 19 depends do not suggests that and this create ambiguity.
Regarding claim 20, the limitation "each of a third top FET in the third CFET structure and a fourth top FET in the fourth CFET structure is incomplete and/or non-functional” enders the claim indefinite and unclear because it is not clear whether “a third top FET in the third CFET structure and a fourth top FET in the fourth CFET structure” recited in claim 20 is the same or different from “a third top FET in the third CFET structure and a fourth top FET in the fourth CFET structure” recited in claim 19.
Clear explanation or claim modification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-3, 6, 9-11, 13-15, 18, and 21-23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US publication 2024/0251540 A1), hereinafter referred to as Lin540.
Regarding claim 1, Lin540 teaches a semiconductor device (fig. 2 & fig. 3a-3c and related text) comprising: a memory cell (fig. 2), comprising: a first inverter (INV1, [0040], fig. 2 & fig. 3a-3c) comprising a first top field effect transistor (FET) and a first bottom FET in a first complementary FET (CFET) structure having a first common gate as an input node of the first inverter (fig. 2 & fig. 3a-3c); and a second inverter (INV2, [0040], fig. 2 & fig. 3a-3c) comprising a second top FET and a second bottom FET in a second complementary CFET structure having a second common gate as an input node of the second inverter (fig. 2 & fig. 3a-3c), wherein an output node of the first inverter is coupled to the input node of the second inverter using a first backside metal (BM) structure and an output node of the second inverter is coupled to the input node of the first inverter using a second BM structure ([0045-0064], fig. 2 & fig. 3a-3c).
Regarding claim 2, Lin540 teaches wherein the output node of the first inverter comprises a first vertical connector that electrically couples a source/drain (S/D) region of the first top FET to an S/D region of the first bottom FET and the output node of the second inverter comprises a second vertical connector that electrically couples an S/D region of the second top FET to an S/D region of the second bottom FET (fig. 2 & fig. 3a-3c).
Regarding claim 3, Lin540 teaches wherein the memory cell further comprises a passgate comprising a third top FET in a third CFET structure and a fourth top FET in a fourth CFET structure (top and bottom depends on viewing direction, [0039-0040], fig. 2 & fig. 3a-3c).
Regarding claim 6, Lin540 teaches wherein the memory cell further comprises a passgate comprising a third bottom FET in a third CFET structure and a fourth bottom FET in a fourth CFET structure (top and bottom depends on viewing direction, [0039-0040], fig. 2 & fig. 3a-3c).
Regarding claim 9, Lin540 teaches wherein each of the first top FET and the second top FET comprises an N-type FET and wherein each of the first bottom FET and the second bottom FET comprises a P-type FET (fig. 2 & fig. 3a-3c).
Regarding claim 10, Lin540 teaches wherein each of the first top FET and the second top FET comprises a P-type FET and wherein each of the first bottom FET and the second bottom FET comprises an N-type FET (fig. 2 & fig. 3a-3c).
Regarding claim 11, Lin540 teaches wherein at least one of the first BM structure and the second BM structure comprise backside metal layer zero (BM0) (fig. 2 & fig. 3a-3c).
Regarding claim 13, Lin540 teaches a method for fabricating a semiconductor device (a method of making a device of fig. 2 & fig. 3a-3c and related text)comprising a memory cell, the method comprising: providing a first inverter (INV1, [0040], fig. 2 & fig. 3a-3c) comprising a first top field effect transistor (FET) and a first bottom FET in a first complementary FET (CFET) structure having a first common gate as an input node of the first inverter (fig. 2 & fig. 3a-3c); providing a second inverter (INV2, [0040], fig. 2 & fig. 3a-3c) comprising a second top FET and a second bottom FET in a second complementary CFET structure having a second common gate as an input node of the second inverter (fig. 2 & fig. 3a-3c); providing a first backside metal (BM) structure that couples an output node of the first inverter to the input node of the second inverter; and providing a second BM structure that couples an output node of the second inverter to the input node of the first inverter ([0045-0064], fig. 2 & fig. 3a-3c).
Regarding claim 14, Lin540 teaches wherein the output node of the first inverter comprises a first vertical connector that electrically couples a source/drain (S/D) region of the first top FET to an S/D region of the first bottom FET and the output node of the second inverter comprises a second vertical connector that electrically couples an S/D region of the second top FET to an S/D region of the second bottom FET (fig. 2 & fig. 3a-3c).
Regarding claim 15, Lin540 teaches further comprising providing a passgate comprising a third top FET in a third CFET structure and a fourth top FET in a fourth CFET structure (top and bottom depends on viewing direction, [0039-0040], fig. 2 & fig. 3a-3c).
Regarding claim 18, Lin540 teaches further comprising providing a passgate comprising a third bottom FET in a third CFET structure and a fourth bottom FET in a fourth CFET structure (top and bottom depends on viewing direction, [0039-0040], fig. 2 & fig. 3a-3c).
Regarding claim 21, Lin540 teaches wherein each of the first top FET and the second top FET comprises an N-type FET and wherein each of the first bottom FET and the second bottom FET comprises a P-type FET (fig. 2 & fig. 3a-3c).
Regarding claim 22, Lin540 teaches wherein each of the first top FET and the second top FET comprises a P-type FET and wherein each of the first bottom FET and the second bottom FET comprises an N-type FET (fig. 2 & fig. 3a-3c).
Regarding claim 23, Lin540 teaches wherein at least one of the first BM structure and the second BM structure comprise backside metal layer zero (BM0) (fig. 2 & fig. 3a-3c).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Lin540, as applied to claim 1 or 13 above, and further in view of Ma et al. (US publication 2012/0306554 A1), hereinafter referred to as Ma554.
Regarding claim 12, Lin540 discloses all the limitations of claim 1 as discussed above on which this claim depends.
Lin540 does not explicitly teach wherein the semiconductor device is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.
Ma554 teaches wherein the semiconductor device is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle ([0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin540 with that of Ma554 so that wherein the semiconductor device is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle for a desired application.
Regarding claim 24, Lin540 discloses all the limitations of claim 13 as discussed above on which this claim depends.
Lin540 does not explicitly teach further comprising incorporating the semiconductor device into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.
Ma554 teaches further comprising incorporating the semiconductor device into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle ([0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin540 with that of Ma554 so that further comprising incorporating the semiconductor device into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle for a desired application.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897