DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to applicant’s communication filed July 14, 2025 in response to PTO Office Action dated January 13, 2025. The applicant’s remarks and amendment to the specification and/or claims were considered with the results that follow.
Claims 1-6, 8-14, and 16-22 have been presented for examination in this application. In response to the last Office Action, claims 1 and 16-18 have been amended.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6, 8-14, and 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, 7-14, 16 and 17 of U.S. Patent No. 11,360,894 in view of OFFICIAL NOTICE.
18/504,545
11,360,894
1. A data access system comprising: a first memory system comprising a non-CPU memory system cache controller and a non-CPU cache memory, wherein the non-CPU cache memory of the first memory system is configured to: be accessed by the non-CPU memory system cache controller;
…
the second memory system comprising a non-volatile memory, such that the non-volatile memory is directly accessed by the non-CPU memory system cache controller; a CPU having CPU cache, the CPU in communication with a main memory module, wherein the CPU cache is separate from the main memory module; and a system bus located between the main memory module and the CPU such that the CPU communicates with the non-CPU memory system cache controller of the main memory module through the system bus; and wherein the CPU is configured to generate, in response to data required by the CPU not being cached in the CPU cache, a request for data that is sent through the system bus to the first memory system.
1. A data access system comprising: a main memory module comprising: a first memory system comprising a non-CPU memory system cache controller and a non-CPU cache memory, wherein the non-CPU cache memory of the first memory system is configured to be accessed by the non-CPU memory system cache controller; attempt to translate a physical address, received with a request for data, to a virtual address, such that the virtual address corresponds to a physical location within the non-CPU cache memory, and in response to determining the physical address to virtual address translation does not exist, the non-CPU memory system cache controller is configured to retrieve the data required by the CPU directly from a non-volatile memory;
a second memory system comprising the a non-volatile memory, such that the non- volatile memory is directly accessed by the non-CPU memory system cache controller; a CPU having CPU cache, the CPU in communication with the main memory module, wherein the CPU cache is separate from the main memory module; and a system bus located between the main memory module and the CPU such that the CPU communicates with the non-CPU memory system cache controller of the main memory module through the system bus; and wherein the CPU is configured to generate, in response to data required by the CPU not being cached in the CPU cache, the a request for data that is sent through the system bus to the cache controller of the main memory module.
What the patent fails to teach is a prefetching system to 1) perform predictive fetching of data stored in the second memory system for data that is expected to be requested by the CPU in the future and storing the fetched data in the non-CPU cache memory of the first memory system, 10) and predictive fetching of data that is predicted to be required by the CPU and retrieving, maintaining, and providing the data that is predicted to be required by the CPU to the first memory system, and storing the data that is predicted to be required by the CPU from the second memory system in the non-CPU cache of the first memory system. This concept of data prefetching is well known to one of ordinary skill in the art for the benefits of reduced data access times by way of reducing cache misses through early loading of data that is related (spatially, temporally, etc.) to previously requested data. One of ordinary skill in the art would recognize that prefetching is a popular and common way to load data from a non-volatile memory in to a volatile memory without a specific access command from the user. By prefetching data related to the data specified in an access command (such as temporally or spatially), and loading this additional data into a volatile memory, the expected data to be requested by the user need only access the volatile memory and not the non-volatile memory. This benefits the user in a quicker response time to the requested data from the volatile memory, rather than a resource intensive cache lookup, cache miss, and non-volatile memory lookup sequence otherwise. The Examiner takes OFFICIAL NOTICE of this teaching. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the caching system to include the concepts of prefetching because of the benefits disclosed supra.
Claims 19-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 18 and 19 of U.S. Patent No. 11,360,894 in view of OFFICIAL NOTICE.
18/504,545
11,360,894
19. A data access and storage system comprising:
a first memory module comprising a cache module having a non-CPU cache controller and a non-CPU cache, the non-CPU cache comprising DRAM memory and a memory controller, such that the cache module is configured to receive, over a system bus, a request for CPU required data from a CPU when the CPU required data is not in a CPU cache, wherein the first memory module and the CPU are located in a server; and a second memory module comprising non-volatile memory that is located remote from and external to the server, such that the non-CPU cache controller can access the non-CPU cache and the non-volatile memory and the second memory module is shared between the server and one or more additional servers; wherein the non-CPU cache controller is configured to: attempt to generate a virtual address based on translation of the physical address that is received from the CPU, such that the virtual address corresponds to a physical location within the non-CPU cache; in response to determining the physical address can be translated to a virtual address, the non-CPU cache controller retrieving the CPU required data from the non-CPU cache; and in response to determining the physical address can not be translated to a virtual address, the non-CPU cache controller retrieving the CPU required data from the non-volatile memory of the second memory module.
18. A data access and system comprising: a main memory module comprising:
a first memory system comprising a non-CPU memory system cache controller and a non-CPU cache memory, wherein the non-CPU cache memory of the first memory system is configured to _ be accessed by the non-CPU memory system cache controller; attempt to translate a physical address, received with a request for data, to a virtual address, such that the virtual address corresponds to a physical location within the non-CPU cache memory, and in response to determining the physical address to virtual address translation does not exist, the non-CPU memory system cache controller is configured to retrieve the data required by the CPU directly from a non-volatile memory. a second memory system comprising the non-volatile memory, such that the non- volatile memory is directly accessed by the non-CPU memory system cache controller; a CPU having CPU cache, the CPU in communication with the main memory module, wherein the CPU cache is separate from the main memory module; and a system bus located between the main memory module and the CPU such that the CPU communicates with the non-CPU memory system cache controller of the main memory module through the system bus; and wherein the CPU is configured to generate, in response to data required by the CPU not being cached in the CPU cache, the request for data that is sent through the system bus to the cache controller of the main memory module.
What the patent fails to teach is wherein the first memory module and the CPU are located in a server, that is located remote from and external to the server, and that the second memory module is shared between the server and one or more additional servers. One of ordinary skill in the art would recognize that CPUs and memory modules are commonly found within computer systems that perform functions including storage and retrieval of data for multiple local and remote users as servers. Non-volatile storage for server functionality is also commonly found attached externally to the server by way of any number of protocols and connections not limited to USB, NAS, and SAN. External storage, for example such as in the case of a NAS, is well known to be attached to a server and shared amongst any other users or servers as dictated by the appropriate security and permissions. This benefits the users at least from the point of not having to each store all of the data at all times, and allows each user/server to access only what is needed by the individual user/server from the external storage (NAS), thus requiring less monetary cost for the user/server. Should the external storage be comprised of solid-state storage devices (21), the user/server would incur the additional benefits of faster access as well as reduced drive failure due no moving parts, and these benefits would also be incurred upon a user/server accessing this external storage should it contained within a cloud-designated storage system (22). The Examiner takes OFFICIAL NOTICE of these teachings. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the storage and caching system to include the concepts of servers, external non-volatile storage, and storage sharing because of the benefits disclosed supra.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 6, 8, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yim et al. (US# 2009/0235014) in view of OFFICIAL NOTICE.
Regarding claim 1, Yim et al. teaches a data access system comprising:
a first memory system comprising a non-CPU memory system cache controller (630) and a non-CPU cache memory (640) , wherein the non-CPU cache memory of the first memory system is configured to:
be accessed by the non-CPU memory system cache controller [0150];
…
a second memory system comprising a non-volatile memory (650), such that the non-
volatile memory is directly accessed by the non-CPU memory system cache controller [0154];
a CPU (610) having CPU cache (620) , the CPU in communication with the main memory module,
wherein the CPU cache is separate from the main memory module [0152] ; and
a system bus located between the main memory module and the CPU such that the CPU
communicates with the non-CPU memory system cache controller of the main memory module
through the system bus [Fig. 6]; and
wherein the CPU is configured to generate, in response to data required by the CPU not
being cached in the CPU cache, a request for data that is sent through the system bus to the first memory system [0152, 0149].
What Yim et al. fails to teach is a prefetching system to perform predictive fetching of data stored in the second memory system for data that is expected to be requested by the CPU in the future and storing the fetched data in the non-CPU cache memory of the first memory system. This concept of data prefetching is well known to one of ordinary skill in the art for the benefits of reduced data access times by way of reducing cache misses through early loading of data that is related (spatially, temporally, etc.) to previously requested data. One of ordinary skill in the art would recognize that prefetching is a popular and common way to load data from a non-volatile memory in to a volatile memory without a specific access command from the user. By prefetching data related to the data specified in an access command (such as temporally or spatially), and loading this additional data into a volatile memory, the expected data to be requested by the user need only access the volatile memory and not the non-volatile memory. This benefits the user in a quicker response time to the requested data from the volatile memory, rather than a resource intensive cache lookup, cache miss, and non-volatile memory lookup sequence otherwise. The Examiner takes OFFICIAL NOTICE of this teaching. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the caching system of Yim et al. to include the concepts of prefetching because of the benefits disclosed supra.
Regarding claim 5, Yim et al. teaches wherein data stored in the non-CPU cache memory is data that has recently been used by the CPU [0007, 0152].
Regarding claim 6, Yim et al. teaches wherein the first memory system comprises DRAM [0106] and the second memory system comprises solid state drive (SSD) [0182].
Regarding claim 8, Yim et al. teaches wherein the non-volatile memory functions as the main memory [0150; NVM functions as main memory for cache misses to volatile memories].
Regarding claim 9, Yim et al. teaches wherein the non-CPU memory system cache controller has one or more fully associative lookup tables [0130].
Response to Arguments
Applicant's arguments filed July 14, 2025 have been fully considered but they are not persuasive.
Regarding Applicant’s argument on page 9 of the response attributed to the two Double Patenting rejections, the Examiner respectfully disagrees. As can be seen above, the claimed subject matter of the instant application was previously recited in Patent No. 11,360,894 except language that is both well known and obvious to one of ordinary skill in the art. Applicant has argued that,
“… the rejections under Nonstatutory Double Patenting are not appropriate based on the prior presented arguments and in view of the current claims claiming specific and enhanced memory architecture details not disclosed in the '894 patent. In particular, the final level cache (FLC) system as presently claimed defines multiple tiers of volatile memory caches combined with a non-volatile main memory replacement functioning as a coherent, integrated memory system-not merely a hybrid system with separate volatile/non-volatile operations.”
The claimed subject matter of the claims of the application and patent relied upon for the Double Patenting rejection do not recite a final level cache or multiple tiers of volatile memory caches, but contain similar language save for a few limitations that have been addressed . Therefore the rejections are proper and maintained.
Regarding Applicant’s argument on page 9 of the response attributed to the 35 USC 103 rejection to Yim et al., the Examiner respectfully disagrees. Applicant has argued that,
The Applicant respectfully traverses all of the rejections because the cited reference, alone or in combination, does not teach or suggest all of the claimed limitations.
The Applicant asserts that Yim describes a memory system in which volatile memory is optionally used to improve access speeds to storage devices. Yim discloses a processor needing to store or access data from a storage device. The Yim system also appears to be one where either volatile memory is accessed or non-volatile memory is accessed depending on temporal locality of the memory addresses being accessed. However, the architecture of Yim does not describe a coherent replacement for main memory based on a hierarchical system comprising multiple tiers of volatile caches backed by a large-capacity, non-volatile memory system, as claimed in the present application. (emphasis added)
As can be seen in the claims filed July 14, 2025, the claim language does not recite a coherent replacement for main memory or a hierarchical system comprising multiple tiers of volatile caches, as argued by Applicant. Furthermore, on page 10 of the response Applicant has argued that the Yim et al. reference does not teach a FLC memory system, automatic propagation for cache misses through a cache hierarchy, and access times for a full memory system that are approximate to those of a fast cache. The Yim et al. reference has not been used to teach these limitations as they are not found within the language of the filed claims that are being rejected. Therefore the rejection is proper and is maintained.
For Applicant’s convenience, two references have been included with the rejection that further teach and expand upon well known prefetching and distributed hardware fundamentals in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art of Sun and Rodriguez teach prefetching and distributed hardware architecture.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Brian R. Peugh whose telephone number is (571) 272-4199. The examiner can normally be reached on Monday-Friday from 7:30am to 3:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Rocio Del Mar Perez-Velez, phone number 571-270-5935, can be reached. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is 571-272-2100.
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/BRIAN R PEUGH/Primary Examiner, Art Unit 2133