DETAILED ACTION
Response to Amendment
Amendment filed on 26 February 2026 has been entered. Claims 1-12 are now pending in the application.
Amendments to the claim 1 to overcome the rejections under U.S.C 112(b) have been fully considered and the rejection under 35 U.S.C. 112(b) of claims 1-8 has been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1- are rejected under 35 U.S.C. 103 as being unpatentable over Ishimaru (US 20090096069) in view of Ishii (US 20120033395).
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Annotated Figs. 5d and 5e, Ishimaru.
Regarding claim 1, Ishimaru teaches, a method for producing a wiring circuit board (COF board 1, Fig. 5) comprising:
a support layer (reinforcing layer 4, Figs. 5a);
an insulating layer forming step (Fig. 5b) of forming an insulating layer (insulating base layer 2, Fig. 5b) on the support layer at least in the pattern forming region;
a pattern step (Figs. 5c to 5e) of forming a conductive pattern (first inner leads 12, Figs. 5c to 5e, para. [0034], metal thin film 17 is formed first on the entire surface of the insulating base layer 2… dummy leads 16 are formed between the adjacent first inner leads 12, para. [0069-0070], plurality of the first inner leads 12 are each formed in a generally rectangular shape, para. [0034]) on an opposite side to the support layer with respect to the insulating layer in the pattern forming region; and
an etching step of etching at least a portion of the support layer in the opening forming region (openings 19 in the reinforcing layer 4, the portions of the reinforcing layer 4 opposing the wiring portions 3 are opened by a known method such as, e.g., chemical etching, wet etching, para. [0076]),
wherein the conductive pattern has:
a first conductive layer (first inner leads 12, Figs. 5c to 5e) having a first thickness (thickness of the first inner lead 12, para. [0070]); and
a second conductive layer (second inner leads 13) having a second thickness different from the first thickness (the thickness of the first inner lead 12 and that of the second inner lead 13 are slightly different, the difference therebetween is in a range of, e.g., not more than 2.0 µm, or preferably not more than 1.0 µm, para. [0072]),
wherein the pattern step includes:
a first pattern step of forming the first conductive layer (metal thin film 17 is formed first on the entire surface of the insulating base layer 2 by a sputtering method or the like, para. [0069]); and
a second pattern step of forming the second conductive layer (metal thin film 17,…dipped in a plating solution of the metal material mentioned above, and electrolytic plating is performed, para. [0069]); and
wherein in at least one of the first pattern step and the second pattern step, a dummy pattern (dummy leads 16, Fig. 5e, dummy leads 16 are formed between the adjacent first inner leads 12, para. [0069-0070) is formed in the opening forming region (see annotated Fig. 5e).
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Annotated Fig. 4, Ishii.
Ishimaru does not teach, a region setting step of setting a pattern forming region and an opening forming region in a support layer. However, Ishii teaches a method for producing a wiring circuit board in Figs. 1 to 10, including forming a support layer 10, forming an insulating layer 11, a pattern step of forming a first conductive layer 12, a second conductive layer 14, and an opening forming region 16, in which,
a region setting step (see Fig. 4 and Abstract) of setting a pattern forming region (suspension boards 1, Figs. 1 and 4) and an opening forming region (see separation groove TR, Fig. 4) in a support layer; wherein in at least one of the first pattern step and the second pattern step, a dummy pattern (dummy trace portion 2, see Abstract) is formed in the opening forming region. Though, Ishimaru teaches in para. [0069], metal thin film 17 is formed first on the entire surface of the insulating base layer 2, from the teaching of Ishimaru in para. [0069], a plating resist is formed on the metal layer 17 in a pattern reverse to the conductive patterns 6, and to a pattern of the dummy leads 16, and forming metal layer 16 by electrolytic plating, one of ordinary skill in the art would have known that the first conductive layer is formed by sputtering, which is a first pattern step and the second conductive layer is formed by electroplating, which is a second pattern step. Therefore, in view of the teachings of Ishii, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of producing a wiring board of Ishimaru and to include a region setting step as taught by Ishii in Fig. 4 so that it enables reducing the residual stress in the region between the conductor traces, which results in sufficiently inhibiting the warpage of the printed circuit board as Ishii disclosed in para. [0013]. Moreover, the recited limitation “a region setting step of setting a pattern forming region and an opening forming region in a support layer” does not contribute over the prior art because, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in forming the region, or setting a region in a region setting step. Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success.
Regarding claim 2, Ishimaru in view of Ishii teaches the recited limitations with respect to claim 1. Ishimaru further teaches, the method for producing a wiring circuit board according to claim 1, wherein in the first pattern step, a dummy first conductive layer having the first thickness and constituting at least a portion of the dummy pattern is formed in the opening forming region (the conductive patterns 6 and the dummy leads 16 are formed simultaneously…respective thicknesses of the conductive patterns 6 and the dummy leads 16 thus formed are in a range of, e.g., not less than 5 µm, or preferably 8 to 15 µm…When the thickness of the first inner lead 12 and that of the second inner lead 13 are slightly different, the difference therebetween is in a range of, e.g., not more than 2.0 µm, or preferably not more than 1.0 µm, para. [0069-0072], in which it is obvious that the dummy conductive layer having a first thickness).
Regarding claim 4, Ishimaru in view of Ishii teaches the recited limitations with respect to claim 1. Ishimaru further teaches, the method for producing a wiring circuit board according to claim 1 further comprising: a cover insulating layer (insulating cover layer 11, see Figs. 5d and 5e below) forming step of forming a cover insulating layer covering the conductive pattern and the dummy pattern (insulating cover layer 11 is formed in a generally rectangular shape…the insulating cover layer 11 are each formed with a metal plating layer not shown, para. [0055-0057]).
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Annotated Figs. 5d and 5e, Ishimaru.
Regarding claim 5, Ishimaru in view of Ishii teaches the recited limitations with respect to claim 1. Ishimaru further teaches, the method for producing a wiring circuit board according to claim 1, wherein in the insulating layer forming step, the insulating layer is formed in the pattern forming region and the opening forming region (see Figs. 5a to 5e), and in at least one of the first pattern step and the second pattern step, the dummy pattern is formed on the insulating layer in the opening forming region (dummy leads 16 are formed between the adjacent first inner leads 12…to form the conductive patterns 6 and the dummy leads 16, a known patterning method such as, e.g., an additive method or a subtractive method is used, para. [0069-0070]).
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Annotated Fig. 1, Ishii.
Regarding claim 6, Ishimaru does not teach the recited limitations. However, Ishii further teaches, the method for producing a wiring circuit board according to claim 5, wherein
in the region setting step, a product region (see annotated Fig. 1 above) including the pattern forming region (suspension boards 1, Fig. 1) and the opening forming region (dummy trace portions 2, see annotated Fig. 1), and a frame region (support frame FR, Fig. 1) connected to the product region are further set in the support layer (plurality of suspension boards 1 are formed within the support frame FR…two dummy trace portions 2 are formed in respective portions between suspension boards 1 positioned at both ends and the end frames f1, f2 of the support frame FR, para. [0043]);
in the etching step (etching with an etching resist, para. [0062]), the entire support layer in the opening forming region is etched to form an opening, and a portion of the support layer between the product region and the frame region is etched to form an outer shape of a wiring circuit board along a shape of the product region and to form a frame connected to the wiring circuit board along the shape of the frame region (regions of the support substrate 10 excluding regions of the suspension bodies 1a of FIG. 3, the dummy trace portions 2 and the support portions SU of FIG. 2 are removed by etching, thereby forming the separation grooves TR shown in FIG. 2 and the opening 40 and the holes H shown in FIG. 3, para. [0064]); and
the method for producing a wiring circuit board further includes a cutting step of cutting the wiring circuit board from the frame and cutting the insulating layer in the opening from the wiring circuit board (each of the suspension boards 1 is then cut and separated from the support frame FR at the coupling portions J of the assembly sheet 100, para. [0066]).
Therefore, in view of the teachings of Ishii, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of producing of a wiring circuit of Ishimaru and set a pattern forming region and an opening foreign region and a frame region connected to the product region as Ishii taught in Fig. 1 so that it enables the forming the printed circuit board assembly sheet inhibited from being warped.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ishimaru in view of Ishii as applied to claim 1 above, and further in view of Lee (US 20240006945).
Regarding claim 3, modified Ishimaru does not teach, a dummy second conductive layer having the second thickness. However, Lee teaches a method for producing a wiring circuit board including an insulating layer and circuit patterns in which, the method for producing a wiring circuit board according to claim 1, wherein in the second pattern step, a dummy second conductive layer having the second thickness (see Fig. 23 below, first-first dummy pattern 401 may have a fifth thickness T5, and the first-second dummy pattern 402 may have a sixth thickness T6, para. [0261]) and constituting at least a portion of the dummy pattern is formed in the opening forming region.
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Annotated Fig. 23, Lee.
Therefore, in view of the teachings of Lee, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of producing of a wiring circuit of Ishimaru and to include a dummy second conductive layer as Lee taught in Fig. 23 so that it enables forming dummy patterns having a desired thickness that improves the electrical characteristics as Lee disclosed in para. [0254].
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 8 is allowable by virtue of its dependency.
The following is an examiner’s statement of reasons for indicating allowable subject matter:
Claim 7 would be allowable for disclosing a method for producing a wiring circuit board, wherein in the insulating layer forming step, the insulating layer is formed in the pattern forming region and the insulating layer is not formed in the opening forming region, and in at least one of the first pattern step and the second pattern step, the dummy pattern is formed on the support layer in the opening forming region.
Though, prior art of record Ishimaru teaches an insulating layer forming step and the insulating layer is formed in the pattern forming region, Ishimaru does not teach, the insulating layer is not formed in the opening forming region, and in at least one of the first pattern step and the second pattern step, the dummy pattern is formed on the support layer in the opening forming region.
Though, prior art of record Ishii teaches an insulating layer forming step and insulating layer is not formed in the opening forming region, Ishii fails to teach in at least one of the first pattern step and the second pattern step, the dummy pattern is formed on the support layer in the opening forming region.
Therefore, claim 7 would be allowable. Claim 8 would be allowable by virtue of its dependency.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSE K ABRAHAM/Examiner, Art Unit 3729 /THOMAS J HONG/Supervisory Patent Examiner, Art Unit 3729
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