DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1.
Pending: 1-11.
Information Disclosure Statement
The information disclosure statement filed 11/8/2023 have been considered please see attach document form 1449.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: ELECTRONIC PACKAGE WITH ENLARGED SECONDARY PORTION.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-7 10 and 11 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Seki US PG pub. 20130105964 A1.
Re: Independent Claim 1, Seki discloses an electronic component (20, fig. 1a) can be mounted, comprising:
a first portion (portion of 20, fig. 1a) having defined therein a mounting region (region where integrated circuit 20 is mounted on to substrate 11, fig. 1a) in which the electronic component (20, fig. 1a) is mounted; and
a second portion (portion of 31, fig. 1a) connected to the first portion (portion of 20, fig. 1a), wherein
an area (area of 30 as shown in figure 1a-1c) of the second portion (portion of 31, fig. 1a) is larger than an area (area of 20, fig. 1a) of the first portion (portion of 20, fig. 1a) in plain view viewed from a direction normal to a surface through which the first portion (portion of 20, fig. 1a) and the second portion (portion of 31, fig. 1a) are connected.
Re: Claim 4, Seki disclose(s) all the limitations of claim 1 on which this claim depends. Seki further discloses: both surfaces of the second portion (portion of 31, fig. 1a) are defined by a first surface (top surface 20 contact with 51, fig. 1a) connected to the first portion (portion of 20, fig. 1a) and a second surface (bottom surface 20 in contact with 22 , fig. 1a) facing the first surface (surface contact with 51, fig. 1a), and
the first surface (surface contact with 51, fig. 1a) and the mounting region (region where integrated circuit 20 is mounted on to substrate 11, fig. 1a) are thermally connected.
Re: Claim 5, Seki disclose(s) all the limitations of claim 4 on which this claim depends. Seki further discloses: the first portion (portion of 20, fig. 1a) is arranged in the center of the first surface (surface contact with 51, fig. 1a) of the second portion (portion of 31, fig. 1a).
Re: Claim 6, Seki disclose(s) all the limitations of claim 1 on which this claim depends. Seki further discloses: a heat sink (40, fig. 1) facing the second portion (portion of 31, fig. 1a).
Re: Claim 7, Seki disclose(s) all the limitations of claim 6 on which this claim depends. Seki further discloses: an insulating heat conduction sheet (51, fig. 1a) disposed between the second portion (portion of 31, fig. 1a) and the heat sink (40, fig. 1).
Re: Claim 11, Seki disclose(s) all the limitations of claim 1 on which this claim depends. Seki further discloses: which is configured to be able to be incorporated on a surface of a wiring substrate, the package further comprising:
a column (32, fig. 1a) that is disposed on the second portion (portion of 31, fig. 1a) in a remaining part of a region in which the first portion (portion of 20, fig. 1a) is disposed, and extends in the direction normal to the surface, wherein
the column (32, fig. 1a) has one end connected to the second portion (portion of 31, fig. 1a) and the other end connected to the wiring substrate (11, fig. 1a) facing the first portion (portion of 20, fig. 1a).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Seki US PG pub. 20130105964 A1; in view of Kim et al., US PG pub. 20050088092 A1.
Re: Claim 2, Seki discloses all the limitations of claim 1 on which this claim depends. Seki is silent regarding: wherein the first portion (portion of 20, fig. 1a) includes a first plate and a second plate which are apart from and opposite from each other,
the mounting region (region where integrated circuit 20 is mounted on to substrate 11, fig. 1a) is set on a surface of the second plate facing the first plate, and
the second plate is connected to the second portion (portion of 31, fig. 1a).
Kim discloses in figure 5 an IC element 23 including top plated, bottom plated and sides plated 332 surround the IC element 23.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include plated surround the electronic component since this can improve the effectiveness of heat dissipation (¶0003).
Re: Claim 3, Seki and Kim discloses all the limitations of claim 2 on which this claim depends. Seki is silent regarding: the first portion (portion of 20, fig. 1a) includes a side plate that connects the first plate and the second plate, and
the electronic component (20, fig. 1a) arranged in the mounting region (region where integrated circuit 20 is mounted on to substrate 11, fig. 1a) is in contact with the side plate.
Kim discloses in figure 5 an IC element 23 including top plated, bottom plated and sides plated 332 surround the IC element 23.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include plated surround the electronic component since this can improve the effectiveness of heat dissipation (¶0003).
Claim(s) 10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Seki US PG pub. 20130105964 A1; in view of Sato US patent 7875971 B2.
Re: Claim 10, Seki disclose(s) all the limitations of claim 1 on which this claim depends. Seki further discloses: wherein the first portion (portion of 20, fig. 1a).
Seki is silent regarding: the first portion is provided in plurality, the plurality of first portions are separated from each other and are connected to the second portion.
Sato discloses in figure 5 and figure 6, multiple of semiconductor elements/first portions 30 are separated from each other and are connected to the second portion 50.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include multiple of semiconductor elements that are form separated in a semiconductor package since this can reduces power for signal transmission with a separated packages and improves heat release abilities (column 4, lines 61-67;column 5, lines 1-34).
Claim(s) 8 and 9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Seki US PG pub. 20130105964 A1.
Re: Claim 8, Seki discloses all the limitations of claim 7 on which this claim depends. Seki further discloses: the first portion (portion of 20, fig. 1a) and the second portion (portion of 31, fig. 1a) have a parallelepiped shape (as shown in figure 1A and figure 9,¶0061), and
assuming that the first portion (portion of 20, fig. 1a) has a width Wm1 and a depth dm1, and the second portion (portion of 31, fig. 1a) has a width Wm2, a depth dm2, and a height hm2.
Seki is silent regarding: the relationships of formulas shown below are satisfied
Wm2 ≥ Wm1 + 2 * hm2 dm2 ≥ dm1 + 2 * hm2.
The general dimensions of Seki are shaped for proper heat dissipation (¶0035-¶0038, ¶0043), such that where the general conditions of a claim are disclosed in the prior art (radiant heat spreading), it is not inventive to discover the optimum or workable ranges (dimensions) by routine experimentation. MPEP 2144.05. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to size the width and depth relationships of Seki, to properly dissipate heat (¶0048).
Re: Claim 9, Seki discloses all the limitations of claim 7 on which this claim depends. Seki further discloses: the first portion (portion of 20, fig. 1a) and the second portion (portion of 31, fig. 1a) have a parallelepiped shape (as shown in figure A1 and 9 that the portion has four sided plane that has straight lines),
assuming that the first portion (portion of 20, fig. 1a) has a width Wm1 and a depth dm1, and the second portion (portion of 31, fig. 1a) has a width Wm2, a depth dm2, and a height hm2.
Seki is silent regarding: when heat is transferred from the first portion (portion of 20, fig. 1a) to the second portion (portion of 31, fig. 1a) by forming an angle θ with a surface of the second portion (portion of 31, fig. 1a) facing a surface connected to the first portion (portion of 20, fig. 1a),
the relationships of formulas shown below are satisfied,
hm2 ≥ (Wm2 − Wm1) / 2 * sinθ / cosθ
hm2≥ (dm2 − dm1) / 2 * sinθ / cosθ.
However, although these limitations have been considered by the Examiner, they pertain to the manner in which the device operates. It has been held that a claim containing a recitation pertaining to the manner of operation is not deemed to patentably distinguish the claimed device from a prior art device that is structurally identical. MPEP 2114. The device of Seki is structurally identical to the Applicant’s claimed device in claim 1 and claim 7. In addition, since the only distinction between the Applicant's claimed device and Seki's is recited in functional language, it is incumbent upon the Applicant to demonstrate that Seki's device is not capable of operating as claimed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that such functional distinctions do not confer patentability when compared with prior art devices like Seki’s.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Ihara et al., US Patent 8962394 B2”) Discloses a semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.
* (“Ankireddi US Patent 7449775 B1”) discloses a decoupling package stack including a circuit board, a substrate mounted on and electrically coupled to the circuit board, a semiconductor die mounted on and electrically coupled to the substrate a deformable elastomeric support mounted on the substrate, one or more mounts coupled to the circuit board and a heatsink. The heatsink includes a contoured heatsink base having a spacer attached thereto, the spacer operable to determine and maintain a desired bondline of a first thermal interface material (TIM) between the semiconductor die and the contoured heatsink base. The heatsink also includes one or more contact portions for contacting the deformable elastomeric support and one or more compressing surfaces coupled to the one or more mounts. A method for assembling a decoupling package stack.
* (“Mania et al., US PG pub. 20050022970 A1”) discloses a mounting plate that is secured between a substrate and a component is used to mount a heat sink. The plate includes holes to accommodate the leads of the component and mounting flanges that partially surround the component and are used to mount the heat sink. In the mounted position, the heat sink is held in thermal communication with the component directly or through a thermally conductive material.
* (“Bhagwagar et al., US PG pub. 20030194537 A1”) discloses a phase change composition comprises: a matrix comprising a silicone-organic block copolymer, and a thermally conductive filler. The composition can be used as a thermal interface material in electronic devices. The composition is formulated to have any desired phase change temperature.
* (“Refai-Ahmed et al., US Patent 11330738 B1”) discloses an electronic device is provided that balances the force applied to temperature control elements such that stress within components of the electronic device can be effectively managed. In one example, an electronic device is provided that includes a printed circuit board (PCB), a chip package, a thermal management system, a thermal spreader, and first and second biasing members. The chip package is mounted to the PCB. The thermal management system and spreader are disposed the opposite of the chip package relative to the PCB. The first biasing member is configured to control a first force sandwiching the chip package between the thermal spreader and the PCB. The second biasing member is configured to control a second force applied by the thermal management system against the thermal spreader. The first force can be adjusted separately from the second force so that total forces applied to the chip package and PCB may be effectively balanced.
* (“Wanha US Patent 10375859 B2”) discloses a ganged shielding cage assembly include a plurality of passageways that allows modules to be inserted into the assembly. Walls between the passageways have a heat transfer passages that extends between the front and back ends and allows for coolant to flow through the assembly. Because of the dimensions, heat can be transferred from an inserted module to the walls and then to the coolant flowing through the heat transfer passages.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898