DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/15/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 7, 13-15, 17, 19, 25-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pemmaraju et al (US 20210319298) in view of Nimmagadda et al (US 20210390460), and in further view of Tomioka (US 12093791 B2).
Regarding claim 1, Pemmaraju discloses a processor-implemented method of graphical machine learning (¶14 deep learning models by selectively providing for subgraphs; ¶15 Given a deep learning model and a target backend device to be executed on, the technology creates subgraphs that are based on supported operators or nodes.), comprising:
receiving a graph for a machine learning model (¶15 The technology helps improve the overall performance of deep learning models by selectively providing for subgraphs to be run on a backend in a manner to reduce or eliminate unnecessary fallbacks between the default runtime and the backend), the graph for the machine learning model including a plurality of subgraphs representing different portions of the machine learning model (¶19 The graph partitioner 120 takes the pretrained model architecture, as marked by the operator capability manager 110, and partitions (e.g., divides) the model into subgraphs (i.e., groups of operators, or clusters). The subgraphs are allocated into two groups—supported subgraphs and unsupported subgraphs);
generating an inference based on executing the machine learning model across the plurality of process domains (¶23 The inference engine 170 controls execution of the model code on the various hardware units that are employed for the particular model optimization. The inference engine 170 reads the input data and compiled graphs, instantiates inference on the selected hardware, and returns the output of the inference; ¶35-37 running the efficient subgraphs on the hardware backend, where the efficient subgraphs are as selected based on the compute-based graph partitioning process).
Pemmaraju fails to teach where Nimmagadda teaches instantiating the machine learning model across a plurality of process domains associated with a same application based on the plurality of subgraphs in the graph for the machine learning model (¶24 The graph partitioner 120 takes the pretrained model architecture, as marked by the operator capability manager 110, and partitions (e.g., divides) the model into subgraphs (i.e., groups of operators, or clusters). The subgraphs are allocated into two groups—supported subgraphs and unsupported subgraphs; ¶66 The system 158 may partition and distribute subgraphs of the AI model to execute across the AI accelerators 148, graphics processor 132, host processor 134 and/or the one or more edge nodes) and on maximum addressable memory spaces of the plurality of process domains (¶20 an AI model graph (or IR of the AI model graph) may be partitioned based on computations and required memory resources of the AI model graph as well as supported computations and memory capacities of edge devices to reduce network communication and load balance; ¶42 a first portion 356a of the first subgraph 356 is maintained as part of the first subgraph 356. The first portion 356a may include a maximum amount of layers that have memory resource requirements less than the memory capacity of the first accelerator 360a. In contrast, a second portion 356b from the first subgraph 356 are reassigned and pushed into the second subgraph 358 for execution);
taking one or more actions based on the generated inference (¶28 The inference engine 170 reads the input data and compiled graphs, instantiates inference on the selected hardware, and returns the output of the inference).
The combination of Pemmaraju and Nimmagadda fails to teach where Tomioka teaches wherein at least two of the process domains are instantiated by a single processor (col 5 lines 14-30 A plurality of machines M1 to M6 are connected to one another via a communications link 206 and also are connected to a control node 200. The control node is connected to a constraint solver 208. The constraint solver 208 receives as input constraints which are computed by a constraint generator 207. The constraint generator 207 takes as input a computation graph 210 representing a machine learning model. The constraint generator also has access to information about the machines. The control node 200 is in communication with a store 202 of training data in examples where the machine learning model is to be trained. The control node receives a partitioning of the computation graph 210 from the constraint solver 208 and runs the computation specified in the computation graph according to the partition over the machines in the execution pipeline; col 16 lines 11-20 FIG. 9 illustrates various components of an exemplary computing-based device 900 which are implemented as any form of a computing and/or electronic device, and in which embodiments of a control node 200 or a machine M1 to M6 are implemented in some examples; Computing-based device 900 comprises one or more processors 902 which are microprocessors).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of instantiating the machine learning model across a plurality of process domains associated with a same application based on the plurality of subgraphs in the graph for the machine learning model, and on maximum addressable memory spaces of the plurality of process domains, and taking one or more actions based on the generated inference from Nimmagadda, and the teaching of wherein at least two of the process domains are instantiated by a single processor from Tomioka into the method as disclosed by Pemmaraju. The motivation for doing this is to improve processing architectures that execute artificial intelligence (AI) processing, and further to ensure efficient computation processing.
Regarding claim 2, the combination of Pemmaraju, Nimmagadda, and Tomioka disclose the method of claim 1, wherein instantiating the machine learning model across the plurality of process domains comprises instantiating a portion of the machine learning model represented by a corresponding subgraph from the plurality of subgraphs based on an amount of memory associated with the portion of the machine learning model and an available amount of memory on a process domain from the plurality of process domains (Nimmagadda ¶20 an AI model graph (or IR of the AI model graph) may be partitioned based on computations and required memory resources of the AI model graph as well as supported computations and memory capacities of edge devices to reduce network communication and load balance; ¶40 The process 350 modifies the first subgraph 356 based on a memory capacity of the first accelerator 360a, 362. That is, the process 350 modifies the first subgraph 356 based on memory resources (e.g., size of weights and activation tensor sizes) required by the first subgraph 356 and a memory capacity of a first accelerator 360a.; the first subgraph 356 may be readjusted and modified to reduce the memory requirements of the first subgraph 356). The motivation to combine the references is discussed above in the rejection of claim 1.
Regarding claim 3, the combination of Pemmaraju, Nimmagadda, and Tomioka disclose the method of claim 1, wherein instantiating the machine learning model across the plurality of process domains comprises mapping outputs of a first subgraph from the plurality of subgraphs to inputs of a second subgraph of the plurality of subgraphs (Pemmaraju ¶51 block 310 provides for generating a first set of subgraphs based on supported nodes of a model graph, wherein the supported nodes have operators that are supported by a hardware backend device separate from a default runtime; Illustrated processing block 330 provides for selecting, from the first set of subgraphs, a second set of subgraphs to be run on the hardware backend device based on the evaluated compute efficiency).
Regarding claim 5, the combination of Pemmaraju, Nimmagadda, and Tomioka disclose the method of claim 1, wherein executing the machine learning model across the plurality of process domains comprises sequentially executing the plurality of subgraphs based on outputs of a first subgraph in the plurality of subgraphs corresponding to inputs of a second subgraph in the plurality of subgraphs (Pemmaraju Fig. 3A & ¶51 illustrated processing block 310 provides for generating a first set of subgraphs based on supported nodes of a model graph, wherein the supported nodes have operators that are supported by a hardware backend device separate from a default runtime. Illustrated processing block 320 provides for evaluating a compute efficiency of each subgraph of the first set of subgraphs relative to the hardware backend device and to a default CPU associated with the default runtime. Illustrated processing block 330 provides for selecting, from the first set of subgraphs, a second set of subgraphs to be run on the hardware backend device based on the evaluated compute efficiency.).
Regarding claim 7, the combination of Pemmaraju, Nimmagadda, and Tomioka disclose the method of claim 1, further comprising releasing the plurality of process domains to terminate execution of the machine learning model (Pemmaraju ¶66 After completion of execution of the operations specified by the code instructions, back end logic 58 retires the instructions of code 42).
Regarding claim(s) 13-15, 17 and 19 (drawn to a system):
The rejection/proposed combination of Pemmaraju, Nimmagadda, and Tomioka, explained in the rejection of methods claim(s) 1-3, 5 and 7, anticipates/renders obvious the steps of the system of claim(s) 13-15, 17 and 19 because these steps occur in the operation of the proposed combination as discussed above. Thus, the arguments similar to that presented above for claim(s) 1-3, 5 and 7 is/are equally applicable to claim(s) 13-15, 17 and 19. See further Pemmaraju ¶55-56.
Regarding claim(s) 25-29 (drawn to a system):
The rejection/proposed combination of Pemmaraju, Nimmagadda, and Tomioka, explained in the rejection of method claim(s) 1-3, 5 and 7, anticipates/renders obvious the steps of the system of claim(s) 25-29 because these steps occur in the operation of the proposed combination as discussed above. Thus, the arguments similar to that presented above for claim(s) 1-3, 5 and 7 is/are equally applicable to claim(s) 25-29. See further Pemmaraju ¶55-56.
Regarding claim(s) 30 (drawn to a CRM):
The rejection/proposed combination of Pemmaraju, Nimmagadda, and Tomioka, explained in the rejection of method claim(s) 1, anticipates/renders obvious the steps of the computer readable medium of claim(s) 30 because these steps occur in the operation of the proposed combination as discussed above. Thus, the arguments similar to that presented above for claim(s) 1 is/are equally applicable to claim(s) 30. See further Pemmaraju ¶55-56.
Claim(s) 4 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pemmaraju, Nimmagadda, and Tomioka as applied to claim 1 and 13 above, and further in view of Kovvuri et al (US 20190286973).
Regarding claim 4, the combination of Pemmaraju, Nimmagadda, and Tomioka disclose the method of claim 1, but fail to teach where Kovvuri teaches wherein each respective subgraph of the plurality of subgraphs is associated with a respective memory space shared within the same application (Kovvuri ¶43 techniques can be applied to such operations to reduce the demands for computation as well as memory bandwidth in a given system; ¶49 the memory interface 140 manages allocation of virtual memory, expanding the available main memory 145).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of wherein each respective subgraph of the plurality of subgraphs is associated with a respective memory space shared within the same application from Kovvuri into the method as disclosed by the combination of Pemmaraju, Nimmagadda, and Tomioka. The motivation for doing this is to improve performance and cost of machine learning models.
Regarding claim(s) 16 (drawn to a system):
The rejection/proposed combination of Pemmaraju, Nimmagadda, Tomioka and Kovvuri, explained in the rejection of methods claim(s) 4, anticipates/renders obvious the steps of the system of claim(s) 16 because these steps occur in the operation of the proposed combination as discussed above. Thus, the arguments similar to that presented above for claim(s) 4 is/are equally applicable to claim(s) 16. See further Pemmaraju ¶55-56.
Claim(s) 6 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pemmaraju, Nimmagadda, and Tomioka as applied to claim 5 and 17 above, and further in view of Eidelman et al (US 20230214754).
Regarding claim 6, the combination of Pemmaraju, Nimmagadda, and Tomioka disclose the method of claim 5, but fail to teach where Eidelman teaches wherein sequentially executing the plurality of subgraphs comprises an atomic operation (¶441-442 Subgraph merging module may create a subgraph with a mix of keyed and non-keyed nodes and keyed and non-keyed relationships; subgraph merging module may execute the merging logic as an atomic operation).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of wherein sequentially executing the plurality of subgraphs comprises an atomic operation from Eidelman into the method as disclosed by the combination of Pemmaraju, Nimmagadda, and Tomioka. The motivation for doing this is to improve merging logic of graphs and subgraphs.
Regarding claim(s) 18 (drawn to a system):
The rejection/proposed combination of Pemmaraju, Nimmagadda, Tomioka and Eidelman, explained in the rejection of method claim(s) 6, anticipates/renders obvious the steps of the system of claim(s) 18 because these steps occur in the operation of the proposed combination as discussed above. Thus, the arguments similar to that presented above for claim(s) 6 is/are equally applicable to claim(s) 18. See further Pemmaraju ¶55-56.
Claim(s) 8-9 and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pemmaraju, Nimmagadda, and Tomioka as applied to claim 1 and 13 above, and further in view of Freed et al (US 20240378666).
Regarding claim 8, the combination of Pemmaraju, Nimmagadda, and Tomioka disclose the method of claim 1, but fail to teach where Freed teaches wherein the machine learning model comprises a generative artificial intelligence model (¶29 a generative artificial intelligence model may be developed to provide analysis and assist users).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of wherein the machine learning model comprises a generative artificial intelligence model from Freed into the method as disclosed by the combination of Pemmaraju, Nimmagadda, and Tomioka. The motivation for doing this is to improve methods for providing insight and analysis of data.
Regarding claim 9, the combination of Pemmaraju, Nimmagadda, Tomioka, and Freed disclose the method of claim 8, wherein the one or more actions comprise generating a response to an input query using the generative artificial intelligence model (Freed ¶8-9 a generative artificial intelligence model configured to receive as input query and the borrower profile and generate predictive responses to the query).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of wherein the one or more actions comprise generating a response to an input query using the generative artificial intelligence model from Freed into the method as disclosed by the combination of Pemmaraju, Nimmagadda, and Tomioka. The motivation for doing this is to improve methods for providing insight and analysis of data.
Regarding claim(s) 20-21 (drawn to a system):
The rejection/proposed combination of Pemmaraju, Nimmagadda, Tomioka and Freed, explained in the rejection of method claim(s) 8-9, anticipates/renders obvious the steps of the system of claim(s) 20-21 because these steps occur in the operation of the proposed combination as discussed above. Thus, the arguments similar to that presented above for claim(s) 8-9 is/are equally applicable to claim(s) 20-21. See further Pemmaraju ¶55-56.
Claim(s) 10-12 and 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pemmaraju, Nimmagadda, and Tomioka as applied to claim 1 and 13 above, and further in view of Michalakis et al (US 20190384291).
Regarding claim 10, the combination of Pemmaraju, Nimmagadda, and Tomioka disclose the method of claim 1, but fail to teach where Michalakis teaches wherein the machine learning model comprises a classifier neural network (¶79 the artificial neural network 508 may include a feature extractor 510, a classifier 512).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of wherein the machine learning model comprises a classifier neural network from Michalakis into the method as disclosed by the combination of Pemmaraju, Nimmagadda, and Tomioka. The motivation for doing this is to improve machine learning models, such as the object detection models.
Regarding claim 11, the combination of Pemmaraju, Nimmagadda, Tomioka and Michalakis disclose the method of claim 10, wherein the one or more actions comprise generating one or more control signals to control an autonomous vehicle based on a classification of one or more objects in a scene generated by the classifier neural network (Michalakis ¶88 at block 612, the autonomous vehicle controls one or more actions based on the adjusted autonomous driving system).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of wherein the one or more actions comprise generating one or more control signals to control an autonomous vehicle based on a classification of one or more objects in a scene generated by the classifier neural network from Michalakis into the method as disclosed by the combination of Pemmaraju, Nimmagadda, and Tomioka. The motivation for doing this is to improve machine learning models, such as the object detection models.
Regarding claim 12, the combination of Pemmaraju, Nimmagadda, Tomioka and Michalakis disclose the method of claim 10, wherein the one or more actions comprise applying different levels of compression to different portions of an image based on classifications of different objects in the image generated by the classifier neural network (Michalakis ¶46 the sub-sampling may compress the frame via a compression standard, such as Dirac, moving picture experts group (MPEG)-4, high efficiency video coding (HEVC), etc. Furthermore, the sub-sampling may adjust the video's frame-rate. For example, the frame rate may be adjusted from thirty frames per second to three frames per second; ¶67 At block 408, the sub-sampling model sub-samples the frame corresponding to the extracted features. The sub-sampling may include reducing a frame rate, reducing the frame's resolution, adjusting attributes of objects in the frame, compressing the frame, encoding the frame, reducing a number of channels of the frame, filtering elements out of the frame, and/or other techniques from reducing a memory footprint of the frame.).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of wherein the one or more actions comprise applying different levels of compression to different portions of an image based on classifications of different objects in the image generated by the classifier neural network from Michalakis into the method as disclosed by the combination of Pemmaraju, Nimmagadda, and Tomioka. The motivation for doing this is to improve machine learning models, such as the object detection models.
Regarding claim(s) 22-24 (drawn to a system):
The rejection/proposed combination of Pemmaraju, Nimmagadda, Tomioka and Michalakis, explained in the rejection of method claim(s) 10-12, anticipates/renders obvious the steps of the system of claim(s) 22-24because these steps occur in the operation of the proposed combination as discussed above. Thus, the arguments similar to that presented above for claim(s) 10-12 is/are equally applicable to claim(s) 22-24. See further Pemmaraju ¶55-56.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/KEVIN KY/Primary Examiner, Art Unit 2671
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