DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: In paragraph [00151], line 11, "the first part 310_A1 and the second part 310_A1" should be changed to "the first part 310_A1 and the second part 310_A2" for formality clarification.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-14 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US Patent 11,527,534 B2).
Regarding claim 1, Cheng teaches a semiconductor device (figs. 14-27) comprising:
a substrate (202; fig 26);
a first lower pattern (L_P; annotated fig. 26(A)) on the substrate;
a second lower pattern (2080B; fig. 26) on the first lower pattern;
channel patterns (2080; fig. 26) on the second lower pattern;
a first field insulating layer (211; annotated fig. 26(A)) on a first side surface of the first lower pattern;
a second field insulating layer (214; fig. 26) on a second side surface of the first lower pattern;
a buried insulating structure (218; fig. 26) on the first field insulating layer and on side surfaces of the channel patterns;
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a protective layer (262/264/272; fig. 23) on the second field insulating layer;
source/drain patterns (256; fig. 14 and 27) on opposite sides of each of the channel patterns; and
a gate electrode (286 in fig. 23; 280-1 and 280-2 in fig. 26) extending around at least some portions of the channel patterns and the buried insulating structure,
wherein the protective layer comprises:
a protective insulating layer (262/264; fig. 23) between the first lower pattern and the second lower pattern, and between the gate electrode and the second field insulating layer; and
a protective liner (272; fig. 23) extending around the protective insulating layer.
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Regarding claim 2, Cheng teaches. The semiconductor device of claim 1, wherein
the protective insulating layer comprises:
a first part (P1; annotated fig. 26(B)) between the first lower pattern and the second lower pattern; and
a second part (P2; annotated fig. 26(B)) between the second field insulating layer and the gate electrode, and
a first thickness (T1; annotated fig. 26(B)) of the first part of the protective insulating layer is smaller than or equal to a second thickness (T2; annotated fig. 26(B)) of the second part of the protective insulating layer.
Regarding claim 3, Cheng teaches the semiconductor device of claim 2, wherein
an upper surface (US_P1; annotated fig. 26(B)) of the first part of the protective insulating layer is closer to an upper surface of the substrate than an upper surface (US_P2; annotated fig. 26(B)) of the second part of the protective insulating layer, or the upper surface of the first part of the protective insulating layer is at a same distance from the upper surface of the substrate as the upper surface of the second part of the protective insulating layer.
Regarding claim 4, Cheng teaches the semiconductor device of claim 3, wherein
a lower surface (LS_P1; annotated fig. 26(B)) of the first part of the protective insulating layer is farther from the upper surface of the substrate than a lower surface (LS_P2; annotated fig. 26(B)) of the second part of the protective insulating layer, or the lower surface of the first part of the protective insulating layer is at a same distance from the upper surface of the substrate as the lower surface of the second part of the protective insulating layer.
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Regarding claim 5, Cheng teaches the semiconductor device of claim 1, wherein
the protective liner further comprises:
a first horizontal part (H1; annotated fig. 23(A)) between the protective insulating layer and the second lower pattern; and
a second horizontal part (H2; annotated fig. 23(A)) between the protective insulating layer and the gate electrode,
wherein an upper surface (US_H1; annotated fig. 23(B)) of the first horizontal part is closer to an upper surface of the substrate than an upper surface (US_H2; annotated fig. 23) of the second horizontal part.
Regarding claim 6, Cheng teaches the semiconductor device of claim 5, wherein
the upper surface (US_H1; annotated fig. 23(B)) of the first horizontal part is closer to the upper surface of the substrate than a lower surface (286; fig. 23) of the gate electrode.
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Regarding claim 7, Cheng teaches the semiconductor device of claim 5, wherein
the first horizontal part (P1; annotated fig. 26(B) which is also part of the 272; fig. 27) overlaps the source/drain patterns (256; fig. 27) in a direction perpendicular to the upper surface of the substrate.
Regarding claim 8, Cheng teaches the semiconductor device of claim 5, wherein
the protective liner comprises:
a third horizontal part (H3; annotated fig. 23(A)) between the protective insulating layer and the first lower pattern; and
a fourth horizontal part (H4; annotated fig. 23(A)) between the protective insulating layer and the second field insulating layer,
wherein a lower surface (LS_H3; annotated fig. 23(B)) of the third horizontal part is farther from the upper surface of the substrate than a lower surface (LS_H4; annotated fig. 23(B)) of the fourth horizontal part.
Regarding claim 9, Cheng teaches the semiconductor device of claim 8, wherein
the lower surface (LS_H3; annotated fig. 23(B)) of the third horizontal part is farther from the upper surface of the substrate than an upper surface of the second field insulating layer.
Regarding claim 10, Cheng teaches a semiconductor device comprising:
a substrate (202; fig 26);
a first lower pattern (L_P; annotated fig. 26(A)) extending in a first direction (perpendicular to the substrate) on the substrate;
a second lower pattern (2080B; fig. 26) on the first lower pattern;
channel patterns (2080; fig. 26) on the second lower pattern;
a first field insulating layer (211; annotated fig. 26(A)) on a first side surface of the first lower pattern;
a second field insulating layer (214; fig. 26) on a second side surface of the first lower pattern;
a buried insulating structure (218; fig. 26) extending in the first direction on the first field insulating layer (211; annotated fig. 26(A)) and on side surfaces of the channel patterns;
source/drain patterns (256; fig. 27) on opposite sides of each of the channel patterns;
a gate electrode (286; fig. 23) extending in a second direction (parallel to the substrate) intersecting with the first direction and extending around at least some portions of the channel patterns and the buried insulating structure; and
a protective layer (262/264; fig. 23) between the first lower pattern and the second lower pattern,
and between the second field insulating layer and the gate electrode, wherein
a first thickness (T1; annotated fig. 26(B)) of the protective layer between the first lower pattern and the
second lower pattern is smaller than or equal to a second thickness (T2; annotated fig. 26(B)) of the protective layer between the second field insulating layer and the gate electrode.
Regarding claim 11, Cheng teaches the semiconductor device of claim 10, wherein
an upper surface (US_P2; annotated fig. 26(B)) of the protective layer between the second field insulating layer and the gate electrode is farther from an upper surface of the substrate than a lower surface (2080B; fig. 26) of the second lower pattern.
Regarding claim 12, Cheng teaches the semiconductor device of claim 11, wherein
a lower surface (286; fig. 23) of the gate electrode is farther from the upper surface of the substrate than an upper surface (L_P; annotated fig. 26(A)) of the first lower pattern.
Regarding claim 13, Cheng teaches. The semiconductor device of claim 11, further comprising:
gate spacers (225: 222,224; fig. 26; column 7, line 51, states 224 may be made of dielectric/oxide) on opposite sides of the gate electrode, wherein
the gate spacers and the protective layer (262/264/272; fig. 23; dielectric/oxide) include a same material.
Regarding claim 14, Cheng teaches the semiconductor device of claim 10, wherein
the protective layer includes a protective insulating layer (262/264; fig 23) in a recess between the first lower pattern and the second lower pattern and between the gate electrode
and the second field insulating layer, and
the protective insulating layer comprises:
a first part of the protective insulating layer (P1; annotated fig. 26(B)) between the second lower pattern and the first lower pattern; and
a second part of the protective insulating layer (P2; annotated fig. 26(B)) extending in the second direction (parallel to the substrate) from the first part of the protective insulating layer between the gate electrode and the second field insulating layer,
wherein a second thickness (T2; annotated fig. 26(B)) of the second part of the protective insulating layer is larger than or equal to a first thickness (T1; annotated fig. 26(B)) of the first part of the protective insulating layer.
Regarding claim 16, Cheng teaches a semiconductor device comprising:
a substrate (202; fig. 26);
a first lower pattern (L_P; annotated fig. 26(A)) on the substrate;
a second lower pattern (2080B; fig. 26) on the first lower pattern;
channel patterns (2080; fig. 26) on the second lower pattern;
a first field insulating layer (211; annotated fig. 26(A)) on a first side surface of the first lower pattern;
a second field insulating layer (214; fig 26) on a second side surface of the first lower pattern;
a buried insulating structure (218; fig. 26) on the first field insulating layer and on side
surfaces of the channel patterns;
a protective layer (262/264; fig. 23) on the second field insulating layer;
source/drain patterns (256; fig. 14 and 27) on opposite sides of each of the channel patterns; and
a gate electrode (286; fig. 23) extending around at least some portions of the channel
patterns and the buried insulating structure, wherein
the protective layer comprises:
a protective insulating layer (262/264; fig. 23) between the first lower pattern and the second lower pattern, and between the gate electrode and the second field insulating layer;
and
a protective liner (272; fig. 23) extending around the protective insulating layer, and
wherein a first distance (D1; annotated fig. 26(C)) between the second lower pattern and the first lower pattern is smaller than or equal to a second distance (D2; annotated fig. 26(C)) between the gate electrode and the second field insulating layer.
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Regarding claim 17, Cheng teaches the semiconductor device of claim 16, wherein
the protective insulating layer comprises:
a first part (P1; annotated fig. 26(B)) between the first lower pattern and the second lower pattern; and
a second part (P2; annotated fig. 26(B)) between the second field insulating layer and the gate electrode,
wherein a first thickness (T1; annotated fig. 26(B)) of the first part of the protective insulating layer is smaller than or equal to a second thickness (T2; annotated fig. 26(B)) of the second part of the protective insulating layer.
Regarding claim 18, Cheng teaches the semiconductor device of claim 17, wherein
a lower surface (LS_P1; annotated fig. 26(B)) of the first part of the protective insulating layer is farther from an upper surface of the substrate than a lower surface (LS_P2; annotated fig. 26(B)) of the second part of the protective insulating layer, or the lower surface of the first part of the protective insulating layer is at a same distance from the upper surface of the substrate as the lower surface of the second part of the protective insulating layer.
Regarding claim 19, Cheng teaches the semiconductor device of claim 16, further comprising:
an insulating pattern (216; fig. 26) between the buried insulating structure (218; fig. 26) and the first field insulating layer (211; annotated fig. 26(A)),
wherein the insulating pattern is on a side surface of the protective layer.
Regarding claim 20, Cheng teaches the semiconductor device of claim 19, wherein
the buried insulating structure (218; fig. 26) is on a side surface of the second lower pattern (2080B; fig. 26).
Although the drawings are not to scale, they may be relied upon for what reasonably teach one of ordinary skill in the art when interpreted in view of the specification. (MPEP 2125(II), in re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US Patent 11,527,534 B2).
Regarding claim 15 Cheng teaches the semiconductor device of claim 14, wherein
the protective layer further includes a protective liner (272; annotated fig. 23) on a lower surface, side surfaces, and an upper surface of the protective insulating layer.
Cheng does not explicitly teach the protective liner includes silicon nitride, and the protective insulating layer includes silicon oxycarbonitride.
However, Cheng teaches that the protective liner (272) and the protective insulating layer (264) are in general high dielectric constant (high-K) layers (col 12, line 40 and, col 11, line 45).
Materials which are generally substituted for the same purpose in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characterization during fabrication.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng by substituting the high-k dielectric materials of silicon nitride as the protective liner and silicon oxycarbonnitride as the protective insulating layer for the high-k materials taught by Cheng, with the motivation that silicon nitride and silicon oxycarbonnitride are also high-k dielectric materials and would be expected to achieve similar device characteristics in Cheng device. Additionally, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RUDRA B CHAUDHARY whose telephone number is (571)272-9292. The examiner can normally be reached mon-fri 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R. B. C./Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811