DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosset at al. U.S. Patent Publication No. 2022/0014691 (hereinafter Bosset) in view of Gohara et al. U.S. Patent Publication No. 2017/0111563 (hereinafter Gohara).
Consider claim 1, Bosset teaches an input sensing device comprising (Figure 2): a plurality of sensor pixels connected to a reset control line (Figure 2, Phi_ran(i)), wherein each sensor pixel of the plurality of sensor pixels is connected to one of a plurality of driving lines (Figure 2, Phi_ligne(i)); a reset circuit configured to apply a reset signal through the reset control line (Figure 2, Phi_ran(i)); and a horizontal driver configured to sequentially apply a horizontal driving signal to the sensor pixels through the driving lines (Figure 2, [0007] and [0041], Phi_ligne(i)), wherein the reset circuit applies the reset signal to the plurality of sensor pixels [0042], and wherein at least one of the plurality of sensor pixels further comprises: a first transistor including a first electrode connected to a reset voltage power line, a second electrode connected to a first node, and a gate electrode connected to the reset control line (Figure 2, T1 and respective connections); a photodiode including an anode electrode connected to a bias voltage power line and a cathode electrode directly connected to the first node, wherein a constant bias voltage is applied to the bias voltage power line (Figure 2, D and respective connections); a second transistor including a first electrode connected to a common voltage power line and a gate electrode connected to the first node (Figure 2, T2 and respective connections), wherein the common voltage power line is different from the reset voltage power line, and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another (Figure 2, V_ran and Vdd); and a third transistor including a first electrode connected to a second node, a second electrode connected to a signal input line, and a gate electrode connected to a corresponding one of the driving lines (Figure 2, T3 and respective connections), wherein, during a reset period within a single frame period, a gate-on voltage of the reset signal is applied to the gate electrode of the first transistor ([0042-0043], reset operation; Figure 2, T1), and during a reminder of the single frame period following the reset period, a gate-off voltage of the signal reset signal is continuously applied to the gate electrode of the first transistor ([0043], image capture phase and read phase (which takes place after a reset operation) do not reset photodiode D or transistor T2. Thus, T1 is inactive during these phases in order to prevent a reset phase, and perform image capture phase and read phase), wherein, during a sensing period within the single frame period, a gate-on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor ([0043], read phase; Figure 2, T3), and wherein the reset period and the sensing period are not overlapped [0043].
Bosset does not appear to specifically disclose pixels disposed in different rows and directly connected to a single reset, simultaneously applies the single reset signal to the plurality of sensor pixels.
However, in a related field of endeavor, Gohara teaches an imaging unit (abstract) and further teaches pixels disposed in different rows and directly connected to a single reset (Figure 3, Reset and 303), simultaneously applies the single reset signal to the plurality of sensor pixels (Figure 3, Reset and 303).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a single reset as taught by Gohara with the benefit that all of the pixels P that make up the unit group 131 start accumulation of charge at the same timing and stop accumulation of charge at the same timing as suggested in [0091].
Consider claim 2, Bosset and Gohara teach all the limitations of clam 1. In addition, Bosset teaches wherein the reset circuit applies the reset signal to the plurality of sensor pixels a plurality of times before applying the horizontal driving signal to the sensor pixels (Figure 2 and [0042-0043], reset for a plurality of frames before a Phi_ligne). In addition, Gohara teaches a single reset signal (Figure 3, Reset).
Consider claim 10, Bosset and Gohara teach all the limitations of clam 1. In addition, Bosset teaches during the sensing period within the single frame period, the gate-on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor a plurality of times (Figure 2 and [0043], when T3 is ON (e.g. during X seconds comprises a plurality of milliseconds).
Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosset in view of Gohara and further in view of Iwasaki et al. U.S. Patent Publication No. 2011/0181754 (hereafter Iwasaki).
Consider claim 4, Bosset teaches an input sensing method comprising: applying a reset signal to a plurality of sensor pixels (Figure 2, Phi_ran(i)), wherein each of the plurality of sensor pixels comprises a first transistor and a second transistor (Figure 2, T1-T2), wherein a gate-on voltage of the reset signal is applied to a gate electrode of the first transistor during a reset period within a single frame period, and wherein a reset voltage power line is electrically connected to a gate electrode of the second transistor via the first transistor; applying a reset voltage to the gate electrode of the second transistor in response to the reset signal (Figure 2, T1-T2, Phi_ran(i) and respective connections), wherein each of the plurality of sensor pixels further comprises a photodiode and a third transistor, wherein the photodiode is directly connected to the gate electrode of the second transistor, wherein a common voltage power line is electrically connected to the third transistor via the second transistor (Figure 2, D, T3 and T2 and respective connections), wherein the common voltage power line is different from the reset voltage power line, wherein each of the common voltage power line and the reset voltage power line extends into a same one of the plurality of sensor pixels separately from one another (Figure 2, V_ran and Vdd), and wherein a constant voltage is applied to an anode electrode of the photodiode (Figure 2, D and respective connections); sequentially applying a horizontal driving signal to the plurality of sensor pixels, such that during a sensing period within the single frame period, a gate-on voltage of the horizontal driving signal is applied to a gate electrode of the third transistor (Figure 2, [0007] and [0041], Phi_ligne(i)); receiving the sensing signal sequentially outputted in response to the horizontal driving signal (Figure 2, [0007] and [0041], Phi_ligne(i)); generating a sensing data signal corresponding to the received sensing signal (Figure 2, [0007] and [0041], Phi_ligne(i)); and wherein the reset period and the sensing period are not overlapped [0043].
Bosset does not appear to specifically disclose pixels disposed in different rows and directly connected to a single reset control line supplying the single reset signal, simultaneously applies the single reset signal to the plurality of sensor pixels.
However, in a related field of endeavor, Gohara teaches an imaging unit (abstract) and further teaches pixels disposed in different rows and directly connected to a single reset control line supplying the single reset signal (Figure 3, Reset and 303), simultaneously applies the single reset signal to the plurality of sensor pixels (Figure 3, Reset and 303).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a single reset as taught by Gohara with the benefit that all of the pixels P that make up the unit group 131 start accumulation of charge at the same timing and stop accumulation of charge at the same timing as suggested in [0091].
Bosset does not appear to specifically disclose correcting the sensing data signal of one of the plurality of sensor pixels, wherein the correcting of the sensing data signal includes dividing the sensing data signal by a value proportional to an amount of time in which the one sensor pixel is exposed to light.
However, in a related field of endeavor, Iwasaki teaches an image pickup device (abstract) and further teaches correcting the sensing data signal of one of the plurality of sensor pixels ([0065], corrects the exposure variation), wherein the correcting of the sensing data signal includes dividing the sensing data signal by a value proportional to an amount of time in which the one sensor pixel is exposed to light ([0078], SIGcorrect=SIGraw*Gi, where Gi=TSh/Treal_i (see also [0077])).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to correct the sensing signal as taught by Iwasaki in order to cope with deterioration of image quality. In addition, high-speed processing is made possible as suggested in [0065] and [0078].
Consider claim 5, Bosset, Gohara and Iwasaki teach all the limitations of claim 4. In addition, Iwasaki teaches wherein an amplitude of the sensing signal increases in proportion to a period between a time point the reset signal is applied and a time point the horizontal driving signal is applied (Figure 12, Treal(i+1) is longer than Treal(i-1) and thus larger amplitude. [0073], Tesht indicating the electronic reset timing. [0074-0075], read from the image pickup device (see motivation to combine in claim 4)).
Consider claim 6, it includes the limitations of claim 2 and thus rejected by the same reasoning.
Consider claim 7, Bosset teaches an input sensing device comprising: a plurality of sensor pixels connected to a reset control line (Figure 2, Phi_ran(i)), wherein each sensor pixel of the plurality of sensor pixels is connected to one of a plurality of driving lines (Figure 2, Phi_ligne(i)); a reset circuit configured to apply a reset signal through the reset control line (Figure 2, Phi_ran(i)); and a horizontal driver configured to sequentially apply a horizontal driving signal to the sensor pixels through the driving lines (Figure 2, [0007] and [0041], Phi_ligne(i)), and wherein at least one of the plurality of sensor pixels further comprises: a first transistor including a first electrode connected to a reset voltage power line, a second electrode connected to a first node, and a gate electrode connected to the reset control line (Figure 2, T1 and respective connections); a photodiode including an anode electrode connected to a bias voltage power line and a cathode electrode directly connected to the first node, wherein a constant bias voltage is applied to the bias voltage power line (Figure 2, D and respective connections); a second transistor including a first electrode connected to a common voltage power line and a gate electrode connected to the first node (Figure 2, T2 and respective connections), wherein the common voltage power line is different from the reset voltage power line, and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another (Figure 2, V_ran and Vdd); and a third transistor including a first electrode connected to a second node, a second electrode connected to a signal input line, and a gate electrode connected to a corresponding one of the driving lines (Figure 2, T3 and respective connections), wherein, during a reset period within a single frame period, a gate-on voltage of the reset signal is applied to the gate electrode of the first transistor ([0042-0043], reset operation; Figure 2, T1), wherein, during a sensing period within the single frame period, a gate-on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor ([0043], read phase; Figure 2, T3), and wherein the reset period and the sensing period are not overlapped [0043].
Bosset does not appear to specifically disclose pixels disposed in different rows and directly connected to a single reset control line, simultaneously applies the single reset signal to the plurality of sensor pixels.
However, in a related field of endeavor, Gohara teaches an imaging unit (abstract) and further teaches pixels disposed in different rows and directly connected to a single reset control line (Figure 3, Reset and 303), simultaneously applies the single reset signal to the plurality of sensor pixels (Figure 3, Reset and 303).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a single reset as taught by Gohara with the benefit that all of the pixels P that make up the unit group 131 start accumulation of charge at the same timing and stop accumulation of charge at the same timing as suggested in [0091].
Bosset does not appear to specifically disclose a display device comprising: an input sensing device.
However, Iwasaki teaches a display device comprising: an input sensing device ([0030], display section).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a display device as taught by Iwasaki the display section is intended to display the image photographed and processed for display as suggested in [0037].
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (see new reference Gohara).
Allowable Subject Matter
Claims 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: Prior arts do not appear to disclose the limitations of the fifth transistor in combination to other limitations of the base claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERTO W FLORES whose telephone number is (571)272-5512. The examiner can normally be reached Monday-Friday, 7am-4pm, EST.
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
