DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/05/2026 has been entered.
This office action is a response to an application filed on 01/05/2026, in which claims 1-20 are pending and ready for examination.
Response to Amendment
Claims 1, 13, and 18 are currently amended.
Response to Argument
Applicant’s arguments with respect to claims rejected under 35 USC 103 in Remarks filed on 01/05/2026 have been considered but are moot upon further consideration and a new ground of rejection made under 35 USC 103 based on Xi (CN 103780914 A, English equivalent document cited) in view of Shibayama (US Pub. 20150092849 A1), and further in view of Huang (US Pub. 20120106652 A1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xi (CN 103780914 A, English equivalent document cited) in view of Shibayama (US Pub. 20150092849 A1), and further in view of Huang (US Pub. 20120106652 A1).
Regarding claim 1, Xi discloses a system, comprising (Xi; Fig. 1, Para. [0029]. A video coding system/method is used.):
a computational storage device, the computational storage device comprising (Xi; Fig. 1, Para. [0029]. A video coding system/method includes processors and memories.):
non-volatile storage (Xi; Fig. 1, Para. [0029]. A video coding system/method includes non-volatile storage.); and
a processing circuit (Xi; Fig. 1, Para. [0029]. A video coding system/method includes processor circuits.),
the processing circuit being configured (Xi; Fig. 1, Para. [0029]. A processor circuit is used to code video.):
to process a first data unit (Xi; Fig. 1, Para. [0029]. A process circuit is used to process video data, including at least a first data unit, see Para. [0098]); and
to process a second data unit, in parallel with the first data unit (Xi; Fig. 1, Para. [0029]. A process circuit is used to process video, including at least a second data unit in parallel with a first data unit, see Para. [0111]).
But it does not specifically disclose to process, in a first pipeline, a first data unit comprisinq a first slice of macroblocks; and to process, in a second pipeline, a second data unit comprisinq a second slice of macroblocks
However, Shibayama teaches to process, in a first pipeline, a first data unit comprisinq a first slice of macroblocks (Shibayama; Fig. 2; Para. [0131]. A first data unit of a first slice of blocks is processed in a first pipeline.); and
to process, in a second pipeline, a second data unit comprisinq a second slice of macroblocks (Shibayama; Fig. 2; Para. [0131]. A first data unit of a first slice of blocks is processed in a first pipeline.).
Therefore, it would have been obvious to a person with ordinary skill in the pertinent before the effective filing date of the claimed invention to modify the video coding system of Xi to adapt a parallel processing approach, by incorporating Shibayama’s teaching wherein slices are processed by different pipelines, for the motivation to parse syntax elements for parallel processing different image segments (Shibayama; Abstract.).
But modified Xi does not specifically teach the first slice comprising more than one row of macroblocks.
However, Huang teaches the first slice comprising more than one row of macroblocks (Huang; Fig. 2. A first slice includes more than one row of macroblocks.).
Therefore, it would have been obvious to a person with ordinary skill in the pertinent before the effective filing date of the claimed invention to modify the video coding system of Xi to adapt a parallel processing approach, by incorporating Huang’s teaching wherein each slice is divided into multiple rows of macroblocks, for the motivation to allow flexible slice structure (Huang; Abstract.).
Regarding claim 2, modified Xi teaches wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image); and
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.).
Regarding claim 3, Xi discloses wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first component of a first piece of the image (Xi; Para. [0111]. A first part of an image includes a first component of at least a block of an image.); and
the second portion of the image is a second component of the first piece of the image (Xi; Para. [0111]. A second part of an image includes a second component of at least a block of an image.).
Regarding claim 4, Xi discloses wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first component of a first piece of the image (Xi; Para. [0111]. A first part of an image includes a first component of at least a block of an image.);
the second portion of the image is a second component of the first piece of the image (Xi; Para. [0111]. A second part of an image includes a second component of at least a block of an image.);
the first component is a luma component (Xi; Para. [0111]. A first component is a luma component.); and
the second component is a chroma component (Xi; Para. [0111]. A second component is a chroma component.).
Regarding claim 5, Xi discloses wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first component of a first piece of the image (Xi; Para. [0111]. A first part of an image includes a first component of at least a block of an image.);
the second portion of the image is a second component of the first piece of the image (Xi; Para. [0111]. A second part of an image includes a second component of at least a block of an image.);
the first component is a luma component (Xi; Para. [0111]. A first component is a luma component.);
the second component is a chroma component (Xi; Para. [0111]. A second component is a chroma component.);
the processing circuit is configured to process the first data unit using an inverse discrete cosine transform (Xi; Para. [0092]. A processor circuit is used to process a first data using an inverse discrete cosine transform.); and
the processing circuit is configured to process the second data unit using an inverse discrete cosine transform (Xi; Para. [0092]. A processor circuit is used to process a second data using an inverse discrete cosine transform.).
Regarding claim 6, Xi discloses wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first component of a first piece of the image (Xi; Para. [0111]. A first part of an image includes a first component of at least a block of an image.);
the second portion of the image is a second component of the first piece of the image (Xi; Para. [0111]. A second part of an image includes a second component of at least a block of an image.);
the first component is a luma component (Xi; Para. [0111]. A first component is a luma component.);
the second component is a chroma component (Xi; Para. [0111]. A second component is a chroma component.);
the processing circuit is configured to process the first data unit using a deblocking filter (Xi; Para. [0111]. A processor circuit is used to process a first data unit using a deblock filter.); and
the processing circuit is configured to process the second data unit using a deblocking filter (Xi; Para. [0111]. A processor circuit is used to process a second data unit using a deblock filter.).
Regarding claim 7, Xi discloses wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image.);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first piece of the image (Xi; Para. [0111]. A first part of an image is a first block of an image.); and
the second portion of the image is a second piece of the image (Xi; Para. [0111]. A second part of an image is a second block of an image.).
Regarding claim 8, Xi discloses wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image.);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first piece of the image (Xi; Para. [0111]. A first part of an image is a first block of an image.);
the second portion of the image is a second piece of the image (Xi; Para. [0111]. A second part of an image is a second block of an image.);
the processing circuit is configured to process the first data unit using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a first data unit using entropy coding.); and
the processing circuit is configured to process the second data unit using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a second data unit using entropy coding.).
Regarding claim 9, Xi discloses wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image.);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first piece of the image (Xi; Para. [0111]. A first part of an image is a first block of an image.);
the second portion of the image is a second piece of the image (Xi; Para. [0111]. A second part of an image is a second block of an image.);
the processing circuit is configured to process the first data unit using a deblocking filter (Xi; Para. [0111]. A processor circuit is used to process a first data unit using a deblock filter.); and
the processing circuit is configured to process the second data unit using a deblocking filter (Xi; Para. [0111]. A processor circuit is used to process a second data unit using a deblock filter.).
Regarding claim 10, Xi discloses wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image.);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first piece of the image (Xi; Para. [0111]. A first part of an image is a first block of an image.);
the second portion of the image is a second piece of the image (Xi; Para. [0111]. A second part of an image is a second block of an image.);
the processing circuit is configured to process the first data unit using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a first data unit using entropy coding.);
the processing circuit is configured to process the second data unit using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a second data unit using entropy coding.);
the processing circuit is further configured to process the first data unit using an inverse discrete cosine transform (Xi; Para. [0092]. A processor circuit is used to process a first data using an inverse discrete cosine transform.); and
the processing circuit is further configured to process the second data unit using an inverse discrete cosine transform (Xi; Para. [0092]. A processor circuit is used to process a second data using an inverse discrete cosine transform.).
Regarding claim 11, Xi discloses the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image.);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first piece of the image (Xi; Para. [0111]. A first part of an image is a first block of an image.);
the second portion of the image is a second piece of the image (Xi; Para. [0111]. A second part of an image is a second block of an image.);
the processing circuit is configured to process the first data unit using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a first data unit using entropy coding.);
the processing circuit is configured to process the second data unit using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a second data unit using entropy coding.);
the processing circuit is further configured to process the first data unit using an inverse discrete cosine transform (Xi; Para. [0092]. A processor circuit is used to process a first data using an inverse discrete cosine transform.);
the processing circuit is further configured to process the second data unit using an inverse discrete cosine transform (Xi; Para. [0092]. A processor circuit is used to process a second data using an inverse discrete cosine transform.);
the processing circuit is further configured to process the first data unit using a deblocking filter (Xi; Para. [0092]. A processor circuit is used to process a first data using a deblocking filter.); and
the processing circuit is further configured to process the second data unit using a deblocking filter (Xi; Para. [0092]. A processor circuit is used to process a second data using a deblocking filter.).
Regarding claim 12, Xi discloses a storage memory (Xi; Para. [0068, 110-111]. A storage memory is used.),
wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image.);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first piece of the image (Xi; Para. [0111]. A first part of an image is a first block of an image.);
the second portion of the image is a second piece of the image (Xi; Para. [0111]. A second part of an image is a second block of an image.);
the processing circuit is configured to process the first data unit using entropy decoding (Xi; Para. [0092-3]. A processor circuit is used to process a first data unit using entropy coding.);
the processing circuit is configured to process the second data unit using entropy decoding (Xi; Para. [0092-3]. A processor circuit is used to process a second data unit using entropy coding.);
the processing circuit is further configured to process the first data unit using an inverse discrete cosine transform to form a first pixel value (Xi; Para. [0092-93]. A processor circuit is used to process a first data unit using an inverse discrete cosine transform to form a first pixel value.);
the processing circuit is further configured to process the second data unit using an inverse discrete cosine transform to form a second pixel value (Xi; Para. [0092-93]. A processor circuit is used to process a second data unit using an inverse discrete cosine transform to form a second pixel value.);
the processing circuit is further configured to store the first pixel value in the storage memory (Xi; Para. [0110-111]. A processor circuit is used to store a first pixel value in a storage memory.);
the processing circuit is further configured to store the second pixel value in the storage memory (Xi; Para. [0068, 110-111]. A processor circuit is used to store a second pixel value in a storage memory.);
the processing circuit is further configured to read the first pixel value from the storage memory (Xi; Para. [0068, 110-111]. A processor circuit is used to obtain a first pixel value from a storage memory.);
the processing circuit is further configured to read the second pixel value from the storage memory (Xi; Para. [0068, 110-111]. A processor circuit is used to obtain a second pixel value from a storage memory.);
the processing circuit is further configured to process the first pixel value using a deblocking filter (Xi; Para. [0068, 110-111]. A processor circuit is used to store a first pixel value using a deblocking filter.); and
the processing circuit is further configured to process the second pixel value using a deblocking filter (Xi; Para. [0068, 110-111]. A processor circuit is used to store a second pixel value using a deblocking filter.).
Regarding claim 13, Xi discloses a method, comprising (Xi; Fig. 1, Para. [0029]. A video coding system/method is used.):
reading, by a processing circuit of a computational storage device, a first data unit from a non-volatile memory of the computational storage device (Xi; Fig. 1, Para. [0029]. A first data unit is obtained from a non-volatile memory via a processor circuit.);
reading, by the processing circuit, a second data unit from the non-volatile memory (Xi; Fig. 1, Para. [0029]. A second data unit is obtained from a non-volatile memory via a processor circuit.);
processing the first data unit (Xi; Fig. 1, Para. [0029]. A process circuit is used to process video data, including at least a first data unit, see Para. [0098]); and
processing the second data unit, in parallel with the first data unit (Xi; Fig. 1, Para. [0029]. A process circuit is used to process video, including at least a second data unit in parallel with a first data unit, see Para. [0111]).
But it does not specifically disclose the first data unit comprising a first slice of macroblocks; reading, by the processing circuit, a second data unit from the non-volatile memory, the second data unit comprising a second slice of macroblocks; processing, in a first pipeline, the first data unit; and processing, in a second pipeline, the second data unit .
However, the first data unit comprising a first slice of macroblocks (Shibayama; Fig. 2; Para. [0131]. A first data unit includes a first slice of blocks.);
reading, by the processing circuit, a second data unit from the non-volatile memory, the second data unit comprising a second slice of macroblocks (Shibayama; Fig. 2; Para. [0131]. A second data unit, including a second slice of blocks, is obtained/read.);
processing, in a first pipeline, the first data unit (Shibayama; Fig. 2; Para. [0131]. A first data unit, including a first slice of blocks, is processed.); and
processing, in a second pipeline, the second data unit (Shibayama; Fig. 2; Para. [0131]. A second data unit, including a second slice of blocks, is processed.).
But modified Xi does not specifically teach the first slice comprising more than one row of macroblocks.
However, Huang teaches the first slice comprising more than one row of macroblocks (Huang; Fig. 2. A first slice includes more than one row of macroblocks.).
Therefore, it would have been obvious to a person with ordinary skill in the pertinent before the effective filing date of the claimed invention to modify the video coding system of Xi to adapt a parallel processing approach, by incorporating Huang’s teaching wherein each slice is divided into multiple rows of macroblocks, for the motivation to allow flexible slice structure (Huang; Abstract.).
Regarding claim 14, Xi discloses the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first piece of the image (Xi; Para. [0111]. A first part of an image includes a first component of at least a block of an image.);
the second portion of the image is a second piece of the image (Xi; Para. [0111]. A second part of an image includes a second component of at least a block of an image.);
the processing of the first data unit comprises using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a first data unit using entropy coding.); and
the processing of the second data unit comprises using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a second data unit using entropy coding.).
Regarding claim 15, Xi discloses wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image.);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first piece of the image (Xi; Para. [0111]. A first part of an image is a first block of an image.);
the second portion of the image is a second piece of the image (Xi; Para. [0111]. A second part of an image is a second block of an image.);
the processing of the first data unit further comprises using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a first data unit using entropy coding.);
the processing of the second data unit further comprises using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a second data unit using entropy coding.);
the processing of the first data unit further comprises using an inverse discrete cosine transform (Xi; Para. [0092]. A processor circuit is used to process a first data using an inverse discrete cosine transform.); and
the processing of the second data unit further comprises using an inverse discrete cosine transform (Xi; Para. [0092]. A processor circuit is used to process a second data using an inverse discrete cosine transform.).
Regarding claim 16, Xi discloses the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image.);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first piece of the image (Xi; Para. [0111]. A first part of an image is a first block of an image.);
the second portion of the image is a second piece of the image (Xi; Para. [0111]. A second part of an image is a second block of an image.);
the processing of the first data unit further comprises using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a first data unit using entropy coding.);
the processing of the second data unit further comprises using entropy decoding (Xi; Para. [0093]. A processor circuit is used to process a second data unit using entropy coding.);
the processing of the first data unit further comprises using an inverse discrete cosine transform (Xi; Para. [0092]. A processor circuit is used to process a first data using an inverse discrete cosine transform.);
the processing of the second data unit further comprises using an inverse discrete cosine transform (Xi; Para. [0092]. A processor circuit is used to process a second data using an inverse discrete cosine transform.);
the processing of the first data unit further comprises using a deblocking filter (Xi; Para. [0092]. A processor circuit is used to process a first data using a deblocking filter.); and
the processing of the second data unit further comprises using a deblocking filter (Xi; Para. [0092]. A processor circuit is used to process a second data using a deblocking filter.).
Regarding claim 17, Xi discloses a storage memory (Xi; Para. [0068, 110-111]. A storage memory is used.),
wherein: the first data unit comprises a first portion of an image (Xi; Para. [0111]. A first data unit includes at least a first part of an image.);
the second data unit comprises a second portion of the image (Xi; Para. [0111]. A second data unit includes at least a second part of an image.);
the first portion of the image is a first piece of the image (Xi; Para. [0111]. A first part of an image is a first block of an image.);
the second portion of the image is a second piece of the image (Xi; Para. [0111]. A second part of an image is a second block of an image.);
the processing of the first data unit further comprises using entropy decoding (Xi; Para. [0092-3]. A processor circuit is used to process a first data unit using entropy coding.);
the processing of the second data unit further comprises using entropy decoding (Xi; Para. [0092-3]. A processor circuit is used to process a second data unit using entropy coding.);
the processing of the first data unit further comprises using an inverse discrete cosine transform to form a first pixel value (Xi; Para. [0092-93]. A processor circuit is used to process a first data unit using an inverse discrete cosine transform to form a first pixel value.);
the processing of the second data unit further comprises using an inverse discrete cosine transform to form a second pixel value (Xi; Para. [0092-93]. A processor circuit is used to process a second data unit using an inverse discrete cosine transform to form a second pixel value.);
the processing of the first data unit further comprises storing the first pixel value in the storage memory (Xi; Para. [0110-111]. A processor circuit is used to store a first pixel value in a storage memory.);
the processing circuit is further configured to store the second pixel value in the storage memory (Xi; Para. [0068, 110-111]. A processor circuit is used to store a second pixel value in a storage memory.);
the processing circuit is further configured to read the first pixel value from the storage memory (Xi; Para. [0068, 110-111]. A processor circuit is used to obtain a first pixel value from a storage memory.);
the processing circuit is further configured to read the second pixel value from the storage memory (Xi; Para. [0068, 110-111]. A processor circuit is used to obtain a second pixel value from a storage memory.);
the processing circuit is further configured to process the first pixel value using a deblocking filter (Xi; Para. [0068, 110-111]. A processor circuit is used to store a first pixel value using a deblocking filter.); and
the processing circuit is further configured to process the second pixel value using a deblocking filter (Xi; Para. [0068, 110-111]. A processor circuit is used to store a second pixel value using a deblocking filter.).
Claims 18-20 are directed to a computational storage device comprising: non-volatile storage; a storage memory; and a processing circuit, the processing circuit being configured to perform a sequence of processing steps corresponding to the same as claimed in claims 1, 5-6, and are rejected for the same reason of anticipation as outlined above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure
Matsubara (US Pub. 20150117549 A1) teaches a video coding device that performs decoding using multiple decoding processing units.
Chao (US Pub. 20160191922 A1) teaches a video coding system that performs multi-core parallel video coding system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT KIR whose telephone number is (571)272-6245. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/ALBERT KIR/ Primary Examiner, Art Unit 2485