Detailed Action
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
2. Applicant’s arguments/remarks, filed on 10/14/2025, are acknowledged. Amended
claim 1 is acknowledged. Claims 1-11 remain pending and have been examined.
Response to Arguments
3. Applicant’s arguments, see pages 1-2, with respect to the rejection of claim 1 under U.S.C. 102 (a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Soundrapandian et al (US11330204B1).
Applicant states, in accordance with amended subject matter regarding claim 1, that Chen fails to disclose, at least, the features of:
“…the data transmitting interface circuits simultaneously provide, upon being triggered according to the first control signal and the second control signal, the exposure parameter data to the image sensors,
the exposure parameter data comprise
an exposure time and shutter speed…”.
4. Response
In accordance with newly introduced prior art, Soundrapandian teaches:
a data transmitting interface circuits simultaneously provide, upon being triggered according to the first control signal and the second control signal, the exposure parameter data to the image sensors (…wherein column 16 (lines 41-62) teaches a first exposure timing engine 230 for a first image sensor and a second exposure timing engine 235 for the second image sensor 225 (see Fig. 2A); column 28 (35-49) in accordance with Fig. 6A, teaches a contemporaneous image exposure timing (as a whole) for a first and second sensor (which may be viewed as the same sensors as in Fig. 2A); wherein nevertheless a start of exposure of a particular ROI may be evident by a “time difference”. Further, column 29 (lines 23-52). Further, column 29 (lines 23-52), in accordance with Fig. 6B, teaches exposure timing for a particular ROI, between two image sensors, can be synchronized based on detecting the “time difference” that is determined as in Fig. 6A. The difference may be comparable to a threshold so to adjust and synchronize image capturing in accordance with Fig. 6B.
the exposure parameter data comprise
an exposure time and shutter speed (…wherein columns 11-12 (lines 62-6) teach a control mechanism 125A (as part of control mechanism 120) which obtains exposure settings which include exposure time or shutter speed…)
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1, 3, 5, 7, and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0366398 A1) in view of Soundrapandian et al (US11330204B1).
7. Regarding claim 1, an image system, comprising:
a plurality of data transmitting interface circuits (…Chen, in [0033] and Fig. 2, teaches control circuit 235; including circuits 232, 234, and 236; which all may transmit data…),
each of the data transmitting interface circuits triggered according to a first control signal
and a second control signal to provide exposure parameter data to a corresponding one of a
plurality of image sensors (…[0040] teaches AE circuit 232 may provide an indication (a first control signal) to synchronization driver circuit 234 regarding adjustment to be made; wherein AE circuit 232 may adjust the exposure time according to or otherwise taking into account of a first frame rate, second frame rate, and difference between the
first frame rate and second frame rate.
[0038] teaches synchronization driver circuit 234 may determine whether the
difference between the first frame rate and the second frame rate is greater than a first
(and second) threshold (thus, the determination that the difference is greater than the
thresholds is viewed as a second control signal), so to adjust and match the first and
second frame rates. [0040] further teaches synchronization driver circuit 234 may
constantly or periodically communicate to or otherwise inform AE circuit 232 of the first
frame rate, second frame rate, and difference between the first frame rate and second
frame rate. [0040] further teaches that as conditions of lighting requiring adjustment to
exposure time change, circuit 232 adjusts exposure time with regards to frame rates and
difference between the frame rates…);
a plurality of video input interface circuits, receiving a plurality of sets of image data from
the image sensors, respectively (…wherein [0035] teaches processor 230 may receive first
data representative of first images captured by first image sensor 210 as well as second
data representative of second images captured by second image sensor 220; wherein
processor 230 includes a plurality of circuits which intake image sensor data for
processing (Fig. 2) …),
wherein the second control signal is associated with a frame timing of at least one set of
the image data (…wherein as taught in [0038], the first or second thresholds relate to a
first and second frame rate and corresponding first and second image sensors…); and
an auto-exposure control circuit, receiving the image data from the video input interface circuits (…[0035] teaches AE circuit 232 which detects brightness conditions from received image sensors 210 and 220…),
updating the exposure parameter data according to the image data (…wherein [0035]
teaches AE circuit 232 may be configured to adjust an exposure time associated with a
respective shutter of each of first image sensor 210 and the second image sensor 220
…), and
generating the first control signal after the exposure parameter data is updated
(…wherein [0075] teaches AE may indicate to each of image sensor 1 and image
sensor 2 a need to change frame rate, as a result of adjustment to exposure time due to a
change in ambient lighting …).
Chen does not further teach wherein
the data transmitting interface circuits simultaneously provide, upon being triggered according to the first control signal and the second control signal, the exposure parameter data to the image sensors (…however, Soundrapandian, in column 16 (lines 41-62), teaches a first exposure timing engine 230 for a first image sensor and a second exposure timing engine 235 for the second image sensor 225 (see Fig. 2A); column 28 (35-49) in accordance with Fig. 6A, teaches a contemporaneous image exposure timing (as a whole) for a first and second sensor (which may be viewed as the same sensors as in Fig. 2A); wherein nevertheless a start of exposure of a particular ROI may be evident by a “time difference”. Further, column 29 (lines 23-52). Further, column 29 (lines 23-52), in accordance with Fig. 6B, teaches exposure timing for a particular ROI, between two image sensors, can be synchronized based on detecting the “time difference” that is determined as in Fig. 6A. The difference may be comparable to a threshold so to adjust and synchronize image capturing in accordance with Fig. 6B.
the exposure parameter data comprise
an exposure time and shutter speed (…wherein columns 11-12 (lines 62-6) teach a control mechanism 125A (as part of control mechanism 120) which obtains exposure settings which include exposure time or shutter speed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a contemporaneous image exposure timing, as taught by Soundrapandian could be applied to two image sensors so to synchronize image capturing for different zoom levels of an imaging scene…).
8. Regarding claim 3, Chen in view of Soundrapandian teaches the image system according to claim 1 (see claim 1 above), wherein
the auto-exposure control circuit transits the first control signal to a central
processor (…wherein [0035] teaches that the AE circuit 232 may be configured to detect a
change in brightness in ambient lighting based at least in part on either or both of the
first data and the second data received from first image sensor 210 and/second image
sensor 220 and [0075] further teaches AE may indicate to each of image sensor 1 and
image sensor 2 a need to change frame rate, as a result of adjustment to exposure time
due to a change in ambient lighting; [0078] also teaches, at 1010 , process 1000 may
involve processor 230 of apparatus 200 detecting a change in brightness [0061] teaches
processor 230 and AE circuit 232 working in tandem (as depicted in Fig. 2)…),
the central processor generates a trigger signal according to the first control signal and
the second control signal (…as taught in [0097], at 1134 , process 1100 may involve
processor 230 synchronizing the first frame rate of first image sensor 210 and the
second frame rate of second image sensor 220 with AE circuit 232 and synchronization
driver circuit 234 collaborating with each other; as a result of having detected a change
in brightness and having determined a difference of frame rates of a certain threshold…),
and
each of the data transmitting interface circuits is triggered according to the trigger signal
so as to provide the exposure parameter data to the corresponding one of the image sensors
(…[0097] teaches at 1134 , process 1100 may involve processor 230 synchronizing the
first frame rate of first image sensor 210 and the second frame rate of second image
sensor 220 with AE circuit 232 and synchronization driver circuit 234 collaborating with
each other; as a result of having detected a change in brightness and having determined
a difference of frame rates of a certain threshold (viewed as triggering factor); as such in
tandem with an AE circuit 232 and synchronization driver circuit 234…).
9. Regarding claim 5, Chen in view of Soundrapandian teaches the image system according to claim 1 (see claim 1 above), wherein
one of the video input interface circuits detects the frame timing of a corresponding set of the image data to generate the second control signal (…Chen, in [0036-0037] teaches an image frame synchronization wherein a synchronization driver circuit 234 may be configured to synchronize a first and second frame rate of corresponding image sensors in response to changes in detected brightness; wherein circuit 234 detects a change of frame rate due to a change in exposure time…).
10. Regarding claim 7, Chen in view of Soundrapandian teaches the image system according to claim 1 (see claim 1 above), wherein
a corresponding one of the video input interface circuits generates the second
control signal according to a corresponding set of the image data, and transmits the second
control signal to the data transmitting interface circuits (…Chen, in [0038], teaches
synchronization driver circuit 234 may monitor the first frame rate and second frame rate,
and determine a difference between the first frame rate and second frame rate.
Synchronization driver circuit 234 may constantly or periodically communicate to or
otherwise inform AE circuit 232 of the first frame rate, second frame rate, and difference
between the first frame rate and second frame rate and determine whether the difference between the first frame rate and the second frame rate is greater than a first (and second)
threshold (wherein, the determination that the difference is greater than the thresholds is
viewed as a second control signal), so to adjust and match the first and second frame
rates…).
11. Regarding claim 10, Chen in view of Soundrapandian teaches the image system according to claim 1 (see claim 1 above), further comprising:
a synchronization circuit, generating a synchronization signal to control the image
sensors to synchronously generate the image data (…Chen teaches image frame
synchronization for dynamic image frame rate, wherein [0009] teaches a synchronization
driver circuit configured to synchronize a first frame rate and a second frame rate
responsive to a detected change in brightness in ambient lighting; similarly, [0037]
teaches synchronization driver circuit 234 may be configured to adjust the first frame
rate to synchronize the first frame rate and the second frame rate…).
12. Regarding claim 11, Chen in view of Soundrapandian teaches, the image system according to claim 10 (see claim 10 above), wherein
the synchronization circuit further generates the second control signal (…wherein Chen, in [0038], teaches synchronization driver circuit 234 may determine
whether the difference between the first frame rate and the second frame rate is greater
than a first and second threshold…).
13. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US
2016/0366398 A1) in view of Soundrapandian et al (US11330204B1) and further view of Quast et al. (US 2013/0208140).
14. Regarding claim 2, Chen in view of Soundrapandian teaches the image system according to claim 1 (see claim 1 above), wherein
the image data is for being stitched into one single image (…though Chen, in [0042], teaches an image processing circuit 238 which performs signal processing on a first and second image data of corresponding image sensors 210 and 220, so to provide corresponding image frame(s),
Chen does not explicitly each image stitching.
However, Quast teaches a brightness adjustment system (of a similar teaching as
Chen), wherein [0030] teaches image stitching after adjustments to image data is made
from two image sensors (e.g., sensors 11 and 12, Fig. 2), wherein the adjustment to
image data relates to adjusting exposure time of the image sensors.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that exposure time control unit may be further configured to control the exposure times of the image sensors such that the brightness parameter(s) determined for a first image sensor at least approximately matches one or more corresponding brightness parameters determined for the second image sensor, so to adequately combine/stitch image frames together as taught by Quast…).
15. Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US
2016/0366398 A1) in view of in view of Soundrapandian et al (US11330204B1) and further view of Quast et al. (US 2013/0208140 A1) and further view of Wikipedia-Direct memory access https://en.wikipedia.org/w/index.php?title=Direct_memory_access&oldid=828116596 (further referred to as “Wikipedia DMA”).
16. Regarding claim 4, Chen in view of Soundrapandian teaches the image system according to claim 1 (see claim 1 above), wherein
the exposure parameter data is stored in a memory (…wherein Chen in [0044] teaches a storage device which stores one or more sets of data; Quast, in [0042], further teaches instructions 524 which may embody BAS (brightness adjustment system) 525, Fig. 5. The instructions 524 may reside completely, or partially, within the memory 504 or within the processor 502 during execution by the computer system 500…),
each of the data transmitting interface circuits comprises a direct memory access (DMA)
circuit, and the DMA circuit is triggered according to the first control signal and the second
control signal so as to transmit the exposure parameter data to the corresponding one of the
image sensors (…wherein Quast in [0022] teaches exposure times of individual image
sensors may be adjusted by a process of “brightness adjustment system” (BAS); [0034]
further teaches the BAS, one or more aspects of the BAS, or any other device or BAS
operating in conjunction with the BAS may include a portion or all of one or more
computing devices of various kinds, such as the computer system 500 in FIG. 5.
Further, Wikipedia DMA teaches direct memory access as a feature a computer
system that allows certain hardware subsystems to access main memory (Random-
access memory), independent of the central processing unit.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that storing data relative to an adjustment
system as taught by Quast in view of Wikipedia DMA could have easily been
implemented in a system as taught by Chen, thus giving a processing unit more time to
process other data...).
17. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US
2016/0366398 A1) in view of in view of Soundrapandian et al (US11330204B1) and further view of Wu et al. (US 2015/0009288 A1; further referred to as Wu).
18. Regarding claim 6, Chen in view of Soundrapandian teaches the image system according to claim 5 (see claim 5 above). Though Chen, in [0034], teaches a periodic timing control signal detector 236 configured to detect a vertical synchronization signal, associated with given image sensors,
Chen does not further teach:
the image system wherein the one of the video input interface circuits detects the
number of lines of the corresponding set of the image data, and generates the second control
signal when the number of lines meets a target number (…however, Wu teaches a
synchronization controller for a multi-sensor camera, to include ISP 601 and associated
components as depicted in Fig. 6. As taught in [0026-0027], a horizontal synchronization
signal HS 1(2) and a vertical synchronization signal VS 1(2) respectively associated with
corresponding image sensors (wherein HS 1(2) indicate an end of transmission of each
line in a frame generated from a respective sensor, and VS 1(2) indicate an end of
transmission of the last line in a frame generated from a respective sensor) are transmitted from respective sensors to a timing generator of ISP 601. As a result the timing generator 608 may generate a sensor reset signal to reset the image sensors.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that frame rates can be tracked by means of
a combination of synchronization signals as taught by Wu and further be used to
measure a frame rate difference between varying frames of images, thus to track a
threshold value of a rate difference as taught by Chen…).
19. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US
2016/0366398 A1) in view of Soundrapandian et al (US11330204B1) Renschler (WO2022177745A1) and further view of Quast et al. (US 2013/0208140 A1).
20. Regarding claim 8, Chen ) in view of Soundrapandian teaches the image system according to claim 1 (see claim 1 above). Though Chen teaches a storage device 250, in [0044], to store data and receive processed images,
Chen does not specify to teach wherein
each of the data transmitting interface circuits comprises a buffer, and the buffer stores the exposure parameter data to be received by the corresponding one of the image sensors (…however, Renschler teaches image processing of low latency image frame delivery, wherein [0056] teaches an exposure control mechanism 125 which obtains exposure setting which are stored in a memory register (which may be viewed a buffer), thus to be applied to an image sensor as image capture settings.
Further, applying dedicated circuitries for different image sensors within an image
capturing device is taught by Quast. Wherein Quast teaches an exposure control
adjustment system, Fig. 2 depicts dedicated exposure controls for image sensors 11-14.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that memory registers, as taught by Renschler, can be used as temporary storage spaces of quick access of image capture settings, in conjunction with exposure control circuits as taught by Quast…).
21. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US
2016/0366398 A1) in view of in view of Soundrapandian et al (US11330204B1) and further view of Renschler (WO2022177745A1).
22. Regarding claim 9, Chen in view of Soundrapandian teaches the image system according to claim 1 (see claim 1 above). Though Chen teaches storage device 250,
Chen does not further specify wherein
one of the data transmitting interface circuits comprises a buffer, the buffer stores the exposure parameter data to be received by each of the image sensors, and the rest of the data
transmitting interface circuits reads the exposure parameter data from the buffer (…however, Renschler teaches image processing of low latency image frame delivery, wherein [0056] teaches an exposure control mechanism 125 which obtains exposure setting which are stored in a memory register (which may be viewed a buffer), thus to be applied to an image sensor as image capture settings.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that memory registers can be used as a
temporary storage spaces of quick access for exposure control of image capturing…).
Conclusion
23. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURAFEL YILMAKASSAYE whose telephone number is (703)756-1910. The examiner can normally be reached Monday-Friday 8:30am-5:00pm.
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/SURAFEL YILMAKASSAYE/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639